si5351.h (3634B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Si5351A/B/C programmable clock generator platform_data. 4 */ 5 6#ifndef __LINUX_PLATFORM_DATA_SI5351_H__ 7#define __LINUX_PLATFORM_DATA_SI5351_H__ 8 9/** 10 * enum si5351_pll_src - Si5351 pll clock source 11 * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config 12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input 13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only) 14 */ 15enum si5351_pll_src { 16 SI5351_PLL_SRC_DEFAULT = 0, 17 SI5351_PLL_SRC_XTAL = 1, 18 SI5351_PLL_SRC_CLKIN = 2, 19}; 20 21/** 22 * enum si5351_multisynth_src - Si5351 multisynth clock source 23 * @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config 24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0 25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO 26 */ 27enum si5351_multisynth_src { 28 SI5351_MULTISYNTH_SRC_DEFAULT = 0, 29 SI5351_MULTISYNTH_SRC_VCO0 = 1, 30 SI5351_MULTISYNTH_SRC_VCO1 = 2, 31}; 32 33/** 34 * enum si5351_clkout_src - Si5351 clock output clock source 35 * @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config 36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N 37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4) 38 * or 4 (N>=4) 39 * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL 40 * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only) 41 */ 42enum si5351_clkout_src { 43 SI5351_CLKOUT_SRC_DEFAULT = 0, 44 SI5351_CLKOUT_SRC_MSYNTH_N = 1, 45 SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2, 46 SI5351_CLKOUT_SRC_XTAL = 3, 47 SI5351_CLKOUT_SRC_CLKIN = 4, 48}; 49 50/** 51 * enum si5351_drive_strength - Si5351 clock output drive strength 52 * @SI5351_DRIVE_DEFAULT: default, do not change eeprom config 53 * @SI5351_DRIVE_2MA: 2mA clock output drive strength 54 * @SI5351_DRIVE_4MA: 4mA clock output drive strength 55 * @SI5351_DRIVE_6MA: 6mA clock output drive strength 56 * @SI5351_DRIVE_8MA: 8mA clock output drive strength 57 */ 58enum si5351_drive_strength { 59 SI5351_DRIVE_DEFAULT = 0, 60 SI5351_DRIVE_2MA = 2, 61 SI5351_DRIVE_4MA = 4, 62 SI5351_DRIVE_6MA = 6, 63 SI5351_DRIVE_8MA = 8, 64}; 65 66/** 67 * enum si5351_disable_state - Si5351 clock output disable state 68 * @SI5351_DISABLE_DEFAULT: default, do not change eeprom config 69 * @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled 70 * @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled 71 * @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when 72 * disabled 73 * @SI5351_DISABLE_NEVER: CLKx is NEVER disabled 74 */ 75enum si5351_disable_state { 76 SI5351_DISABLE_DEFAULT = 0, 77 SI5351_DISABLE_LOW, 78 SI5351_DISABLE_HIGH, 79 SI5351_DISABLE_FLOATING, 80 SI5351_DISABLE_NEVER, 81}; 82 83/** 84 * struct si5351_clkout_config - Si5351 clock output configuration 85 * @clkout: clkout number 86 * @multisynth_src: multisynth source clock 87 * @clkout_src: clkout source clock 88 * @pll_master: if true, clkout can also change pll rate 89 * @pll_reset: if true, clkout can reset its pll 90 * @drive: output drive strength 91 * @rate: initial clkout rate, or default if 0 92 */ 93struct si5351_clkout_config { 94 enum si5351_multisynth_src multisynth_src; 95 enum si5351_clkout_src clkout_src; 96 enum si5351_drive_strength drive; 97 enum si5351_disable_state disable_state; 98 bool pll_master; 99 bool pll_reset; 100 unsigned long rate; 101}; 102 103/** 104 * struct si5351_platform_data - Platform data for the Si5351 clock driver 105 * @clk_xtal: xtal input clock 106 * @clk_clkin: clkin input clock 107 * @pll_src: array of pll source clock setting 108 * @clkout: array of clkout configuration 109 */ 110struct si5351_platform_data { 111 enum si5351_pll_src pll_src[2]; 112 struct si5351_clkout_config clkout[8]; 113}; 114 115#endif