cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pmc_atom.h (4372B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Intel Atom SOC Power Management Controller Header File
      4 * Copyright (c) 2014, Intel Corporation.
      5 */
      6
      7#ifndef PMC_ATOM_H
      8#define PMC_ATOM_H
      9
     10/* ValleyView Power Control Unit PCI Device ID */
     11#define	PCI_DEVICE_ID_VLV_PMC	0x0F1C
     12/* CherryTrail Power Control Unit PCI Device ID */
     13#define	PCI_DEVICE_ID_CHT_PMC	0x229C
     14
     15/* PMC Memory mapped IO registers */
     16#define	PMC_BASE_ADDR_OFFSET	0x44
     17#define	PMC_BASE_ADDR_MASK	0xFFFFFE00
     18#define	PMC_MMIO_REG_LEN	0x100
     19#define	PMC_REG_BIT_WIDTH	32
     20
     21/* BIOS uses FUNC_DIS to disable specific function */
     22#define	PMC_FUNC_DIS		0x34
     23#define	PMC_FUNC_DIS_2		0x38
     24
     25/* CHT specific bits in FUNC_DIS2 register */
     26#define	BIT_FD_GMM		BIT(3)
     27#define	BIT_FD_ISH		BIT(4)
     28
     29/* S0ix wake event control */
     30#define	PMC_S0IX_WAKE_EN	0x3C
     31
     32#define	BIT_LPC_CLOCK_RUN		BIT(4)
     33#define	BIT_SHARED_IRQ_GPSC		BIT(5)
     34#define	BIT_ORED_DEDICATED_IRQ_GPSS	BIT(18)
     35#define	BIT_ORED_DEDICATED_IRQ_GPSC	BIT(19)
     36#define	BIT_SHARED_IRQ_GPSS		BIT(20)
     37
     38#define	PMC_WAKE_EN_SETTING	~(BIT_LPC_CLOCK_RUN | \
     39				BIT_SHARED_IRQ_GPSC | \
     40				BIT_ORED_DEDICATED_IRQ_GPSS | \
     41				BIT_ORED_DEDICATED_IRQ_GPSC | \
     42				BIT_SHARED_IRQ_GPSS)
     43
     44/* The timers accumulate time spent in sleep state */
     45#define	PMC_S0IR_TMR		0x80
     46#define	PMC_S0I1_TMR		0x84
     47#define	PMC_S0I2_TMR		0x88
     48#define	PMC_S0I3_TMR		0x8C
     49#define	PMC_S0_TMR		0x90
     50/* Sleep state counter is in units of of 32us */
     51#define	PMC_TMR_SHIFT		5
     52
     53/* Power status of power islands */
     54#define	PMC_PSS			0x98
     55
     56#define PMC_PSS_BIT_GBE			BIT(0)
     57#define PMC_PSS_BIT_SATA		BIT(1)
     58#define PMC_PSS_BIT_HDA			BIT(2)
     59#define PMC_PSS_BIT_SEC			BIT(3)
     60#define PMC_PSS_BIT_PCIE		BIT(4)
     61#define PMC_PSS_BIT_LPSS		BIT(5)
     62#define PMC_PSS_BIT_LPE			BIT(6)
     63#define PMC_PSS_BIT_DFX			BIT(7)
     64#define PMC_PSS_BIT_USH_CTRL		BIT(8)
     65#define PMC_PSS_BIT_USH_SUS		BIT(9)
     66#define PMC_PSS_BIT_USH_VCCS		BIT(10)
     67#define PMC_PSS_BIT_USH_VCCA		BIT(11)
     68#define PMC_PSS_BIT_OTG_CTRL		BIT(12)
     69#define PMC_PSS_BIT_OTG_VCCS		BIT(13)
     70#define PMC_PSS_BIT_OTG_VCCA_CLK	BIT(14)
     71#define PMC_PSS_BIT_OTG_VCCA		BIT(15)
     72#define PMC_PSS_BIT_USB			BIT(16)
     73#define PMC_PSS_BIT_USB_SUS		BIT(17)
     74
     75/* CHT specific bits in PSS register */
     76#define	PMC_PSS_BIT_CHT_UFS		BIT(7)
     77#define	PMC_PSS_BIT_CHT_UXD		BIT(11)
     78#define	PMC_PSS_BIT_CHT_UXD_FD		BIT(12)
     79#define	PMC_PSS_BIT_CHT_UX_ENG		BIT(15)
     80#define	PMC_PSS_BIT_CHT_USB_SUS		BIT(16)
     81#define	PMC_PSS_BIT_CHT_GMM		BIT(17)
     82#define	PMC_PSS_BIT_CHT_ISH		BIT(18)
     83#define	PMC_PSS_BIT_CHT_DFX_MASTER	BIT(26)
     84#define	PMC_PSS_BIT_CHT_DFX_CLUSTER1	BIT(27)
     85#define	PMC_PSS_BIT_CHT_DFX_CLUSTER2	BIT(28)
     86#define	PMC_PSS_BIT_CHT_DFX_CLUSTER3	BIT(29)
     87#define	PMC_PSS_BIT_CHT_DFX_CLUSTER4	BIT(30)
     88#define	PMC_PSS_BIT_CHT_DFX_CLUSTER5	BIT(31)
     89
     90/* These registers reflect D3 status of functions */
     91#define	PMC_D3_STS_0		0xA0
     92
     93#define	BIT_LPSS1_F0_DMA	BIT(0)
     94#define	BIT_LPSS1_F1_PWM1	BIT(1)
     95#define	BIT_LPSS1_F2_PWM2	BIT(2)
     96#define	BIT_LPSS1_F3_HSUART1	BIT(3)
     97#define	BIT_LPSS1_F4_HSUART2	BIT(4)
     98#define	BIT_LPSS1_F5_SPI	BIT(5)
     99#define	BIT_LPSS1_F6_XXX	BIT(6)
    100#define	BIT_LPSS1_F7_XXX	BIT(7)
    101#define	BIT_SCC_EMMC		BIT(8)
    102#define	BIT_SCC_SDIO		BIT(9)
    103#define	BIT_SCC_SDCARD		BIT(10)
    104#define	BIT_SCC_MIPI		BIT(11)
    105#define	BIT_HDA			BIT(12)
    106#define	BIT_LPE			BIT(13)
    107#define	BIT_OTG			BIT(14)
    108#define	BIT_USH			BIT(15)
    109#define	BIT_GBE			BIT(16)
    110#define	BIT_SATA		BIT(17)
    111#define	BIT_USB_EHCI		BIT(18)
    112#define	BIT_SEC			BIT(19)
    113#define	BIT_PCIE_PORT0		BIT(20)
    114#define	BIT_PCIE_PORT1		BIT(21)
    115#define	BIT_PCIE_PORT2		BIT(22)
    116#define	BIT_PCIE_PORT3		BIT(23)
    117#define	BIT_LPSS2_F0_DMA	BIT(24)
    118#define	BIT_LPSS2_F1_I2C1	BIT(25)
    119#define	BIT_LPSS2_F2_I2C2	BIT(26)
    120#define	BIT_LPSS2_F3_I2C3	BIT(27)
    121#define	BIT_LPSS2_F4_I2C4	BIT(28)
    122#define	BIT_LPSS2_F5_I2C5	BIT(29)
    123#define	BIT_LPSS2_F6_I2C6	BIT(30)
    124#define	BIT_LPSS2_F7_I2C7	BIT(31)
    125
    126#define	PMC_D3_STS_1		0xA4
    127#define	BIT_SMB			BIT(0)
    128#define	BIT_OTG_SS_PHY		BIT(1)
    129#define	BIT_USH_SS_PHY		BIT(2)
    130#define	BIT_DFX			BIT(3)
    131
    132/* CHT specific bits in PMC_D3_STS_1 register */
    133#define	BIT_STS_GMM		BIT(1)
    134#define	BIT_STS_ISH		BIT(2)
    135
    136/* PMC I/O Registers */
    137#define	ACPI_BASE_ADDR_OFFSET	0x40
    138#define	ACPI_BASE_ADDR_MASK	0xFFFFFE00
    139#define	ACPI_MMIO_REG_LEN	0x100
    140
    141#define	PM1_CNT			0x4
    142#define	SLEEP_TYPE_MASK		0xFFFFECFF
    143#define	SLEEP_TYPE_S5		0x1C00
    144#define	SLEEP_ENABLE		0x2000
    145
    146extern int pmc_atom_read(int offset, u32 *value);
    147
    148#endif /* PMC_ATOM_H */