xilinx-ll-temac.h (1320B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __LINUX_XILINX_LL_TEMAC_H 3#define __LINUX_XILINX_LL_TEMAC_H 4 5#include <linux/if_ether.h> 6#include <linux/phy.h> 7#include <linux/spinlock.h> 8 9struct ll_temac_platform_data { 10 bool txcsum; /* Enable/disable TX checksum */ 11 bool rxcsum; /* Enable/disable RX checksum */ 12 u8 mac_addr[ETH_ALEN]; /* MAC address (6 bytes) */ 13 /* Clock frequency for input to MDIO clock generator */ 14 u32 mdio_clk_freq; 15 unsigned long long mdio_bus_id; /* Unique id for MDIO bus */ 16 int phy_addr; /* Address of the PHY to connect to */ 17 phy_interface_t phy_interface; /* PHY interface mode */ 18 bool reg_little_endian; /* Little endian TEMAC register access */ 19 bool dma_little_endian; /* Little endian DMA register access */ 20 /* Pre-initialized mutex to use for synchronizing indirect 21 * register access. When using both interfaces of a single 22 * TEMAC IP block, the same mutex should be passed here, as 23 * they share the same DCR bus bridge. 24 */ 25 spinlock_t *indirect_lock; 26 /* DMA channel control setup */ 27 u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */ 28 u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */ 29 u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */ 30 u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */ 31}; 32 33#endif /* __LINUX_XILINX_LL_TEMAC_H */