cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pmbus.h (2543B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Hardware monitoring driver for PMBus devices
      4 *
      5 * Copyright (c) 2010, 2011 Ericsson AB.
      6 */
      7
      8#ifndef _PMBUS_H_
      9#define _PMBUS_H_
     10
     11#include <linux/bits.h>
     12
     13/* flags */
     14
     15/*
     16 * PMBUS_SKIP_STATUS_CHECK
     17 *
     18 * During register detection, skip checking the status register for
     19 * communication or command errors.
     20 *
     21 * Some PMBus chips respond with valid data when trying to read an unsupported
     22 * register. For such chips, checking the status register is mandatory when
     23 * trying to determine if a chip register exists or not.
     24 * Other PMBus chips don't support the STATUS_CML register, or report
     25 * communication errors for no explicable reason. For such chips, checking
     26 * the status register must be disabled.
     27 */
     28#define PMBUS_SKIP_STATUS_CHECK	BIT(0)
     29
     30/*
     31 * PMBUS_WRITE_PROTECTED
     32 * Set if the chip is write protected and write protection is not determined
     33 * by the standard WRITE_PROTECT command.
     34 */
     35#define PMBUS_WRITE_PROTECTED	BIT(1)
     36
     37/*
     38 * PMBUS_NO_CAPABILITY
     39 *
     40 * Some PMBus chips don't respond with valid data when reading the CAPABILITY
     41 * register. For such chips, this flag should be set so that the PMBus core
     42 * driver doesn't use CAPABILITY to determine it's behavior.
     43 */
     44#define PMBUS_NO_CAPABILITY			BIT(2)
     45
     46/*
     47 * PMBUS_READ_STATUS_AFTER_FAILED_CHECK
     48 *
     49 * Some PMBus chips end up in an undefined state when trying to read an
     50 * unsupported register. For such chips, it is necessary to reset the
     51 * chip pmbus controller to a known state after a failed register check.
     52 * This can be done by reading a known register. By setting this flag the
     53 * driver will try to read the STATUS register after each failed
     54 * register check. This read may fail, but it will put the chip in a
     55 * known state.
     56 */
     57#define PMBUS_READ_STATUS_AFTER_FAILED_CHECK	BIT(3)
     58
     59/*
     60 * PMBUS_NO_WRITE_PROTECT
     61 *
     62 * Some PMBus chips respond with invalid data when reading the WRITE_PROTECT
     63 * register. For such chips, this flag should be set so that the PMBus core
     64 * driver doesn't use the WRITE_PROTECT command to determine its behavior.
     65 */
     66#define PMBUS_NO_WRITE_PROTECT			BIT(4)
     67
     68/*
     69 * PMBUS_USE_COEFFICIENTS_CMD
     70 *
     71 * When this flag is set the PMBus core driver will use the COEFFICIENTS
     72 * register to initialize the coefficients for the direct mode format.
     73 */
     74#define PMBUS_USE_COEFFICIENTS_CMD		BIT(5)
     75
     76struct pmbus_platform_data {
     77	u32 flags;		/* Device specific flags */
     78
     79	/* regulator support */
     80	int num_regulators;
     81	struct regulator_init_data *reg_init_data;
     82};
     83
     84#endif /* _PMBUS_H_ */