cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpu.h (3989B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * IXP4XX cpu type detection
      4 *
      5 * Copyright (C) 2007 MontaVista Software, Inc.
      6 */
      7
      8#ifndef __SOC_IXP4XX_CPU_H__
      9#define __SOC_IXP4XX_CPU_H__
     10
     11#include <linux/io.h>
     12#include <linux/regmap.h>
     13#ifdef CONFIG_ARM
     14#include <asm/cputype.h>
     15#endif
     16
     17/* Processor id value in CP15 Register 0 */
     18#define IXP42X_PROCESSOR_ID_VALUE	0x690541c0 /* including unused 0x690541Ex */
     19#define IXP42X_PROCESSOR_ID_MASK	0xffffffc0
     20
     21#define IXP43X_PROCESSOR_ID_VALUE	0x69054040
     22#define IXP43X_PROCESSOR_ID_MASK	0xfffffff0
     23
     24#define IXP46X_PROCESSOR_ID_VALUE	0x69054200 /* including IXP455 */
     25#define IXP46X_PROCESSOR_ID_MASK	0xfffffff0
     26
     27/* Feature register in the expansion bus controller */
     28#define IXP4XX_EXP_CNFG2		0x2c
     29
     30/* "fuse" bits of IXP_EXP_CFG2 */
     31/* All IXP4xx CPUs */
     32#define IXP4XX_FEATURE_RCOMP		(1 << 0)
     33#define IXP4XX_FEATURE_USB_DEVICE	(1 << 1)
     34#define IXP4XX_FEATURE_HASH		(1 << 2)
     35#define IXP4XX_FEATURE_AES		(1 << 3)
     36#define IXP4XX_FEATURE_DES		(1 << 4)
     37#define IXP4XX_FEATURE_HDLC		(1 << 5)
     38#define IXP4XX_FEATURE_AAL		(1 << 6)
     39#define IXP4XX_FEATURE_HSS		(1 << 7)
     40#define IXP4XX_FEATURE_UTOPIA		(1 << 8)
     41#define IXP4XX_FEATURE_NPEB_ETH0	(1 << 9)
     42#define IXP4XX_FEATURE_NPEC_ETH		(1 << 10)
     43#define IXP4XX_FEATURE_RESET_NPEA	(1 << 11)
     44#define IXP4XX_FEATURE_RESET_NPEB	(1 << 12)
     45#define IXP4XX_FEATURE_RESET_NPEC	(1 << 13)
     46#define IXP4XX_FEATURE_PCI		(1 << 14)
     47#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT	(3 << 16)
     48#define IXP4XX_FEATURE_XSCALE_MAX_FREQ	(3 << 22)
     49#define IXP42X_FEATURE_MASK		(IXP4XX_FEATURE_RCOMP            | \
     50					 IXP4XX_FEATURE_USB_DEVICE       | \
     51					 IXP4XX_FEATURE_HASH             | \
     52					 IXP4XX_FEATURE_AES              | \
     53					 IXP4XX_FEATURE_DES              | \
     54					 IXP4XX_FEATURE_HDLC             | \
     55					 IXP4XX_FEATURE_AAL              | \
     56					 IXP4XX_FEATURE_HSS              | \
     57					 IXP4XX_FEATURE_UTOPIA           | \
     58					 IXP4XX_FEATURE_NPEB_ETH0        | \
     59					 IXP4XX_FEATURE_NPEC_ETH         | \
     60					 IXP4XX_FEATURE_RESET_NPEA       | \
     61					 IXP4XX_FEATURE_RESET_NPEB       | \
     62					 IXP4XX_FEATURE_RESET_NPEC       | \
     63					 IXP4XX_FEATURE_PCI              | \
     64					 IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
     65					 IXP4XX_FEATURE_XSCALE_MAX_FREQ)
     66
     67
     68/* IXP43x/46x CPUs */
     69#define IXP4XX_FEATURE_ECC_TIMESYNC	(1 << 15)
     70#define IXP4XX_FEATURE_USB_HOST		(1 << 18)
     71#define IXP4XX_FEATURE_NPEA_ETH		(1 << 19)
     72#define IXP43X_FEATURE_MASK		(IXP42X_FEATURE_MASK             | \
     73					 IXP4XX_FEATURE_ECC_TIMESYNC     | \
     74					 IXP4XX_FEATURE_USB_HOST         | \
     75					 IXP4XX_FEATURE_NPEA_ETH)
     76
     77/* IXP46x CPU (including IXP455) only */
     78#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3	(1 << 20)
     79#define IXP4XX_FEATURE_RSA		(1 << 21)
     80#define IXP46X_FEATURE_MASK		(IXP43X_FEATURE_MASK             | \
     81					 IXP4XX_FEATURE_NPEB_ETH_1_TO_3  | \
     82					 IXP4XX_FEATURE_RSA)
     83
     84#ifdef CONFIG_ARCH_IXP4XX
     85#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
     86				IXP42X_PROCESSOR_ID_VALUE)
     87#define cpu_is_ixp42x()	((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
     88			 IXP42X_PROCESSOR_ID_VALUE)
     89#define cpu_is_ixp43x()	((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
     90			 IXP43X_PROCESSOR_ID_VALUE)
     91#define cpu_is_ixp46x()	((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
     92			 IXP46X_PROCESSOR_ID_VALUE)
     93static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
     94{
     95	u32 val;
     96
     97	regmap_read(rmap, IXP4XX_EXP_CNFG2, &val);
     98	/* For some reason this register is inverted */
     99	val = ~val;
    100	if (cpu_is_ixp42x_rev_a0())
    101		return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
    102					       IXP4XX_FEATURE_AES);
    103	if (cpu_is_ixp42x())
    104		return val & IXP42X_FEATURE_MASK;
    105	if (cpu_is_ixp43x())
    106		return val & IXP43X_FEATURE_MASK;
    107	return val & IXP46X_FEATURE_MASK;
    108}
    109#else
    110#define cpu_is_ixp42x_rev_a0()		0
    111#define cpu_is_ixp42x()			0
    112#define cpu_is_ixp43x()			0
    113#define cpu_is_ixp46x()			0
    114static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
    115{
    116	return 0;
    117}
    118#endif
    119
    120#endif  /* _ASM_ARCH_CPU_H */