switchtec.h (11161B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Microsemi Switchtec PCIe Driver 4 * Copyright (c) 2017, Microsemi Corporation 5 */ 6 7#ifndef _SWITCHTEC_H 8#define _SWITCHTEC_H 9 10#include <linux/pci.h> 11#include <linux/cdev.h> 12 13#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 14#define SWITCHTEC_MAX_PFF_CSR 255 15 16#define SWITCHTEC_EVENT_OCCURRED BIT(0) 17#define SWITCHTEC_EVENT_CLEAR BIT(0) 18#define SWITCHTEC_EVENT_EN_LOG BIT(1) 19#define SWITCHTEC_EVENT_EN_CLI BIT(2) 20#define SWITCHTEC_EVENT_EN_IRQ BIT(3) 21#define SWITCHTEC_EVENT_FATAL BIT(4) 22#define SWITCHTEC_EVENT_NOT_SUPP BIT(31) 23 24#define SWITCHTEC_DMA_MRPC_EN BIT(0) 25 26#define MRPC_GAS_READ 0x29 27#define MRPC_GAS_WRITE 0x87 28#define MRPC_CMD_ID(x) ((x) & 0xffff) 29 30enum { 31 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, 32 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, 33 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800, 34 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000, 35 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200, 36 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000, 37 SWITCHTEC_GAS_NTB_OFFSET = 0x10000, 38 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000, 39}; 40 41enum switchtec_gen { 42 SWITCHTEC_GEN3, 43 SWITCHTEC_GEN4, 44}; 45 46struct mrpc_regs { 47 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 48 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 49 u32 cmd; 50 u32 status; 51 u32 ret_value; 52 u32 dma_en; 53 u64 dma_addr; 54 u32 dma_vector; 55 u32 dma_ver; 56} __packed; 57 58enum mrpc_status { 59 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1, 60 SWITCHTEC_MRPC_STATUS_DONE = 2, 61 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF, 62 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100, 63}; 64 65struct sw_event_regs { 66 u64 event_report_ctrl; 67 u64 reserved1; 68 u64 part_event_bitmap; 69 u64 reserved2; 70 u32 global_summary; 71 u32 reserved3[3]; 72 u32 stack_error_event_hdr; 73 u32 stack_error_event_data; 74 u32 reserved4[4]; 75 u32 ppu_error_event_hdr; 76 u32 ppu_error_event_data; 77 u32 reserved5[4]; 78 u32 isp_error_event_hdr; 79 u32 isp_error_event_data; 80 u32 reserved6[4]; 81 u32 sys_reset_event_hdr; 82 u32 reserved7[5]; 83 u32 fw_exception_hdr; 84 u32 reserved8[5]; 85 u32 fw_nmi_hdr; 86 u32 reserved9[5]; 87 u32 fw_non_fatal_hdr; 88 u32 reserved10[5]; 89 u32 fw_fatal_hdr; 90 u32 reserved11[5]; 91 u32 twi_mrpc_comp_hdr; 92 u32 twi_mrpc_comp_data; 93 u32 reserved12[4]; 94 u32 twi_mrpc_comp_async_hdr; 95 u32 twi_mrpc_comp_async_data; 96 u32 reserved13[4]; 97 u32 cli_mrpc_comp_hdr; 98 u32 cli_mrpc_comp_data; 99 u32 reserved14[4]; 100 u32 cli_mrpc_comp_async_hdr; 101 u32 cli_mrpc_comp_async_data; 102 u32 reserved15[4]; 103 u32 gpio_interrupt_hdr; 104 u32 gpio_interrupt_data; 105 u32 reserved16[4]; 106 u32 gfms_event_hdr; 107 u32 gfms_event_data; 108 u32 reserved17[4]; 109} __packed; 110 111enum { 112 SWITCHTEC_GEN3_CFG0_RUNNING = 0x04, 113 SWITCHTEC_GEN3_CFG1_RUNNING = 0x05, 114 SWITCHTEC_GEN3_IMG0_RUNNING = 0x03, 115 SWITCHTEC_GEN3_IMG1_RUNNING = 0x07, 116}; 117 118enum { 119 SWITCHTEC_GEN4_MAP0_RUNNING = 0x00, 120 SWITCHTEC_GEN4_MAP1_RUNNING = 0x01, 121 SWITCHTEC_GEN4_KEY0_RUNNING = 0x02, 122 SWITCHTEC_GEN4_KEY1_RUNNING = 0x03, 123 SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04, 124 SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05, 125 SWITCHTEC_GEN4_CFG0_RUNNING = 0x06, 126 SWITCHTEC_GEN4_CFG1_RUNNING = 0x07, 127 SWITCHTEC_GEN4_IMG0_RUNNING = 0x08, 128 SWITCHTEC_GEN4_IMG1_RUNNING = 0x09, 129}; 130 131enum { 132 SWITCHTEC_GEN4_KEY0_ACTIVE = 0, 133 SWITCHTEC_GEN4_KEY1_ACTIVE = 1, 134 SWITCHTEC_GEN4_BL2_0_ACTIVE = 0, 135 SWITCHTEC_GEN4_BL2_1_ACTIVE = 1, 136 SWITCHTEC_GEN4_CFG0_ACTIVE = 0, 137 SWITCHTEC_GEN4_CFG1_ACTIVE = 1, 138 SWITCHTEC_GEN4_IMG0_ACTIVE = 0, 139 SWITCHTEC_GEN4_IMG1_ACTIVE = 1, 140}; 141 142struct sys_info_regs_gen3 { 143 u32 reserved1; 144 u32 vendor_table_revision; 145 u32 table_format_version; 146 u32 partition_id; 147 u32 cfg_file_fmt_version; 148 u16 cfg_running; 149 u16 img_running; 150 u32 reserved2[57]; 151 char vendor_id[8]; 152 char product_id[16]; 153 char product_revision[4]; 154 char component_vendor[8]; 155 u16 component_id; 156 u8 component_revision; 157} __packed; 158 159struct sys_info_regs_gen4 { 160 u16 gas_layout_ver; 161 u8 evlist_ver; 162 u8 reserved1; 163 u16 mgmt_cmd_set_ver; 164 u16 fabric_cmd_set_ver; 165 u32 reserved2[2]; 166 u8 mrpc_uart_ver; 167 u8 mrpc_twi_ver; 168 u8 mrpc_eth_ver; 169 u8 mrpc_inband_ver; 170 u32 reserved3[7]; 171 u32 fw_update_tmo; 172 u32 xml_version_cfg; 173 u32 xml_version_img; 174 u32 partition_id; 175 u16 bl2_running; 176 u16 cfg_running; 177 u16 img_running; 178 u16 key_running; 179 u32 reserved4[43]; 180 u32 vendor_seeprom_twi; 181 u32 vendor_table_revision; 182 u32 vendor_specific_info[2]; 183 u16 p2p_vendor_id; 184 u16 p2p_device_id; 185 u8 p2p_revision_id; 186 u8 reserved5[3]; 187 u32 p2p_class_id; 188 u16 subsystem_vendor_id; 189 u16 subsystem_id; 190 u32 p2p_serial_number[2]; 191 u8 mac_addr[6]; 192 u8 reserved6[2]; 193 u32 reserved7[3]; 194 char vendor_id[8]; 195 char product_id[24]; 196 char product_revision[2]; 197 u16 reserved8; 198} __packed; 199 200struct sys_info_regs { 201 u32 device_id; 202 u32 device_version; 203 u32 firmware_version; 204 union { 205 struct sys_info_regs_gen3 gen3; 206 struct sys_info_regs_gen4 gen4; 207 }; 208} __packed; 209 210struct partition_info { 211 u32 address; 212 u32 length; 213}; 214 215struct flash_info_regs_gen3 { 216 u32 flash_part_map_upd_idx; 217 218 struct active_partition_info_gen3 { 219 u32 address; 220 u32 build_version; 221 u32 build_string; 222 } active_img; 223 224 struct active_partition_info_gen3 active_cfg; 225 struct active_partition_info_gen3 inactive_img; 226 struct active_partition_info_gen3 inactive_cfg; 227 228 u32 flash_length; 229 230 struct partition_info cfg0; 231 struct partition_info cfg1; 232 struct partition_info img0; 233 struct partition_info img1; 234 struct partition_info nvlog; 235 struct partition_info vendor[8]; 236}; 237 238struct flash_info_regs_gen4 { 239 u32 flash_address; 240 u32 flash_length; 241 242 struct active_partition_info_gen4 { 243 unsigned char bl2; 244 unsigned char cfg; 245 unsigned char img; 246 unsigned char key; 247 } active_flag; 248 249 u32 reserved[3]; 250 251 struct partition_info map0; 252 struct partition_info map1; 253 struct partition_info key0; 254 struct partition_info key1; 255 struct partition_info bl2_0; 256 struct partition_info bl2_1; 257 struct partition_info cfg0; 258 struct partition_info cfg1; 259 struct partition_info img0; 260 struct partition_info img1; 261 struct partition_info nvlog; 262 struct partition_info vendor[8]; 263}; 264 265struct flash_info_regs { 266 union { 267 struct flash_info_regs_gen3 gen3; 268 struct flash_info_regs_gen4 gen4; 269 }; 270}; 271 272enum { 273 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000, 274 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000, 275 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000, 276}; 277 278struct ntb_info_regs { 279 u8 partition_count; 280 u8 partition_id; 281 u16 reserved1; 282 u64 ep_map; 283 u16 requester_id; 284 u16 reserved2; 285 u32 reserved3[4]; 286 struct nt_partition_info { 287 u32 xlink_enabled; 288 u32 target_part_low; 289 u32 target_part_high; 290 u32 reserved; 291 } ntp_info[48]; 292} __packed; 293 294struct part_cfg_regs { 295 u32 status; 296 u32 state; 297 u32 port_cnt; 298 u32 usp_port_mode; 299 u32 usp_pff_inst_id; 300 u32 vep_pff_inst_id; 301 u32 dsp_pff_inst_id[47]; 302 u32 reserved1[11]; 303 u16 vep_vector_number; 304 u16 usp_vector_number; 305 u32 port_event_bitmap; 306 u32 reserved2[3]; 307 u32 part_event_summary; 308 u32 reserved3[3]; 309 u32 part_reset_hdr; 310 u32 part_reset_data[5]; 311 u32 mrpc_comp_hdr; 312 u32 mrpc_comp_data[5]; 313 u32 mrpc_comp_async_hdr; 314 u32 mrpc_comp_async_data[5]; 315 u32 dyn_binding_hdr; 316 u32 dyn_binding_data[5]; 317 u32 intercomm_notify_hdr; 318 u32 intercomm_notify_data[5]; 319 u32 reserved4[153]; 320} __packed; 321 322enum { 323 NTB_CTRL_PART_OP_LOCK = 0x1, 324 NTB_CTRL_PART_OP_CFG = 0x2, 325 NTB_CTRL_PART_OP_RESET = 0x3, 326 327 NTB_CTRL_PART_STATUS_NORMAL = 0x1, 328 NTB_CTRL_PART_STATUS_LOCKED = 0x2, 329 NTB_CTRL_PART_STATUS_LOCKING = 0x3, 330 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4, 331 NTB_CTRL_PART_STATUS_RESETTING = 0x5, 332 333 NTB_CTRL_BAR_VALID = 1 << 0, 334 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4, 335 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5, 336 337 NTB_CTRL_REQ_ID_EN = 1 << 0, 338 339 NTB_CTRL_LUT_EN = 1 << 0, 340}; 341 342struct ntb_ctrl_regs { 343 u32 partition_status; 344 u32 partition_op; 345 u32 partition_ctrl; 346 u32 bar_setup; 347 u32 bar_error; 348 u16 lut_table_entries; 349 u16 lut_table_offset; 350 u32 lut_error; 351 u16 req_id_table_size; 352 u16 req_id_table_offset; 353 u32 req_id_error; 354 u32 reserved1[7]; 355 struct { 356 u32 ctl; 357 u32 win_size; 358 u64 xlate_addr; 359 } bar_entry[6]; 360 struct { 361 u32 win_size; 362 u32 reserved[3]; 363 } bar_ext_entry[6]; 364 u32 reserved2[192]; 365 u32 req_id_table[512]; 366 u32 reserved3[256]; 367 u64 lut_entry[512]; 368} __packed; 369 370#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32) 371#define NTB_DBMSG_IMSG_MASK BIT_ULL(40) 372 373struct ntb_dbmsg_regs { 374 u32 reserved1[1024]; 375 u64 odb; 376 u64 odb_mask; 377 u64 idb; 378 u64 idb_mask; 379 u8 idb_vec_map[64]; 380 u32 msg_map; 381 u32 reserved2; 382 struct { 383 u32 msg; 384 u32 status; 385 } omsg[4]; 386 387 struct { 388 u32 msg; 389 u8 status; 390 u8 mask; 391 u8 src; 392 u8 reserved; 393 } imsg[4]; 394 395 u8 reserved3[3928]; 396 u8 msix_table[1024]; 397 u8 reserved4[3072]; 398 u8 pba[24]; 399 u8 reserved5[4072]; 400} __packed; 401 402enum { 403 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0, 404 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1, 405 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2, 406 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3, 407}; 408 409struct pff_csr_regs { 410 u16 vendor_id; 411 u16 device_id; 412 u16 pcicmd; 413 u16 pcists; 414 u32 pci_class; 415 u32 pci_opts; 416 union { 417 u32 pci_bar[6]; 418 u64 pci_bar64[3]; 419 }; 420 u32 pci_cardbus; 421 u32 pci_subsystem_id; 422 u32 pci_expansion_rom; 423 u32 pci_cap_ptr; 424 u32 reserved1; 425 u32 pci_irq; 426 u32 pci_cap_region[48]; 427 u32 pcie_cap_region[448]; 428 u32 indirect_gas_window[128]; 429 u32 indirect_gas_window_off; 430 u32 reserved[127]; 431 u32 pff_event_summary; 432 u32 reserved2[3]; 433 u32 aer_in_p2p_hdr; 434 u32 aer_in_p2p_data[5]; 435 u32 aer_in_vep_hdr; 436 u32 aer_in_vep_data[5]; 437 u32 dpc_hdr; 438 u32 dpc_data[5]; 439 u32 cts_hdr; 440 u32 cts_data[5]; 441 u32 uec_hdr; 442 u32 uec_data[5]; 443 u32 hotplug_hdr; 444 u32 hotplug_data[5]; 445 u32 ier_hdr; 446 u32 ier_data[5]; 447 u32 threshold_hdr; 448 u32 threshold_data[5]; 449 u32 power_mgmt_hdr; 450 u32 power_mgmt_data[5]; 451 u32 tlp_throttling_hdr; 452 u32 tlp_throttling_data[5]; 453 u32 force_speed_hdr; 454 u32 force_speed_data[5]; 455 u32 credit_timeout_hdr; 456 u32 credit_timeout_data[5]; 457 u32 link_state_hdr; 458 u32 link_state_data[5]; 459 u32 reserved4[174]; 460} __packed; 461 462struct switchtec_ntb; 463 464struct dma_mrpc_output { 465 u32 status; 466 u32 cmd_id; 467 u32 rtn_code; 468 u32 output_size; 469 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 470}; 471 472struct switchtec_dev { 473 struct pci_dev *pdev; 474 struct device dev; 475 struct cdev cdev; 476 477 enum switchtec_gen gen; 478 479 int partition; 480 int partition_count; 481 int pff_csr_count; 482 char pff_local[SWITCHTEC_MAX_PFF_CSR]; 483 484 void __iomem *mmio; 485 struct mrpc_regs __iomem *mmio_mrpc; 486 struct sw_event_regs __iomem *mmio_sw_event; 487 struct sys_info_regs __iomem *mmio_sys_info; 488 struct flash_info_regs __iomem *mmio_flash_info; 489 struct ntb_info_regs __iomem *mmio_ntb; 490 struct part_cfg_regs __iomem *mmio_part_cfg; 491 struct part_cfg_regs __iomem *mmio_part_cfg_all; 492 struct pff_csr_regs __iomem *mmio_pff_csr; 493 494 /* 495 * The mrpc mutex must be held when accessing the other 496 * mrpc_ fields, alive flag and stuser->state field 497 */ 498 struct mutex mrpc_mutex; 499 struct list_head mrpc_queue; 500 int mrpc_busy; 501 struct work_struct mrpc_work; 502 struct delayed_work mrpc_timeout; 503 bool alive; 504 505 wait_queue_head_t event_wq; 506 atomic_t event_cnt; 507 508 struct work_struct link_event_work; 509 void (*link_notifier)(struct switchtec_dev *stdev); 510 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR]; 511 512 struct switchtec_ntb *sndev; 513 514 struct dma_mrpc_output *dma_mrpc; 515 dma_addr_t dma_mrpc_dma_addr; 516}; 517 518static inline struct switchtec_dev *to_stdev(struct device *dev) 519{ 520 return container_of(dev, struct switchtec_dev, dev); 521} 522 523extern struct class *switchtec_class; 524 525#endif