r8a66597.h (18069B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R8A66597 driver platform data 4 * 5 * Copyright (C) 2009 Renesas Solutions Corp. 6 * 7 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 * 22 */ 23 24#ifndef __LINUX_USB_R8A66597_H 25#define __LINUX_USB_R8A66597_H 26 27#define R8A66597_PLATDATA_XTAL_12MHZ 0x01 28#define R8A66597_PLATDATA_XTAL_24MHZ 0x02 29#define R8A66597_PLATDATA_XTAL_48MHZ 0x03 30 31struct r8a66597_platdata { 32 /* This callback can control port power instead of DVSTCTR register. */ 33 void (*port_power)(int port, int power); 34 35 /* This parameter is for BUSWAIT */ 36 u16 buswait; 37 38 /* set one = on chip controller, set zero = external controller */ 39 unsigned on_chip:1; 40 41 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */ 42 unsigned xtal:2; 43 44 /* set one = 3.3V, set zero = 1.5V */ 45 unsigned vif:1; 46 47 /* set one = big endian, set zero = little endian */ 48 unsigned endian:1; 49 50 /* (external controller only) set one = WR0_N shorted to WR1_N */ 51 unsigned wr0_shorted_to_wr1:1; 52 53 /* set one = using SUDMAC */ 54 unsigned sudmac:1; 55}; 56 57/* Register definitions */ 58#define SYSCFG0 0x00 59#define SYSCFG1 0x02 60#define SYSSTS0 0x04 61#define SYSSTS1 0x06 62#define DVSTCTR0 0x08 63#define DVSTCTR1 0x0A 64#define TESTMODE 0x0C 65#define PINCFG 0x0E 66#define DMA0CFG 0x10 67#define DMA1CFG 0x12 68#define CFIFO 0x14 69#define D0FIFO 0x18 70#define D1FIFO 0x1C 71#define CFIFOSEL 0x20 72#define CFIFOCTR 0x22 73#define CFIFOSIE 0x24 74#define D0FIFOSEL 0x28 75#define D0FIFOCTR 0x2A 76#define D1FIFOSEL 0x2C 77#define D1FIFOCTR 0x2E 78#define INTENB0 0x30 79#define INTENB1 0x32 80#define INTENB2 0x34 81#define BRDYENB 0x36 82#define NRDYENB 0x38 83#define BEMPENB 0x3A 84#define SOFCFG 0x3C 85#define INTSTS0 0x40 86#define INTSTS1 0x42 87#define INTSTS2 0x44 88#define BRDYSTS 0x46 89#define NRDYSTS 0x48 90#define BEMPSTS 0x4A 91#define FRMNUM 0x4C 92#define UFRMNUM 0x4E 93#define USBADDR 0x50 94#define USBREQ 0x54 95#define USBVAL 0x56 96#define USBINDX 0x58 97#define USBLENG 0x5A 98#define DCPCFG 0x5C 99#define DCPMAXP 0x5E 100#define DCPCTR 0x60 101#define PIPESEL 0x64 102#define PIPECFG 0x68 103#define PIPEBUF 0x6A 104#define PIPEMAXP 0x6C 105#define PIPEPERI 0x6E 106#define PIPE1CTR 0x70 107#define PIPE2CTR 0x72 108#define PIPE3CTR 0x74 109#define PIPE4CTR 0x76 110#define PIPE5CTR 0x78 111#define PIPE6CTR 0x7A 112#define PIPE7CTR 0x7C 113#define PIPE8CTR 0x7E 114#define PIPE9CTR 0x80 115#define PIPE1TRE 0x90 116#define PIPE1TRN 0x92 117#define PIPE2TRE 0x94 118#define PIPE2TRN 0x96 119#define PIPE3TRE 0x98 120#define PIPE3TRN 0x9A 121#define PIPE4TRE 0x9C 122#define PIPE4TRN 0x9E 123#define PIPE5TRE 0xA0 124#define PIPE5TRN 0xA2 125#define DEVADD0 0xD0 126#define DEVADD1 0xD2 127#define DEVADD2 0xD4 128#define DEVADD3 0xD6 129#define DEVADD4 0xD8 130#define DEVADD5 0xDA 131#define DEVADD6 0xDC 132#define DEVADD7 0xDE 133#define DEVADD8 0xE0 134#define DEVADD9 0xE2 135#define DEVADDA 0xE4 136 137/* System Configuration Control Register */ 138#define XTAL 0xC000 /* b15-14: Crystal selection */ 139#define XTAL48 0x8000 /* 48MHz */ 140#define XTAL24 0x4000 /* 24MHz */ 141#define XTAL12 0x0000 /* 12MHz */ 142#define XCKE 0x2000 /* b13: External clock enable */ 143#define PLLC 0x0800 /* b11: PLL control */ 144#define SCKE 0x0400 /* b10: USB clock enable */ 145#define PCSDIS 0x0200 /* b9: not CS wakeup */ 146#define LPSME 0x0100 /* b8: Low power sleep mode */ 147#define HSE 0x0080 /* b7: Hi-speed enable */ 148#define DCFM 0x0040 /* b6: Controller function select */ 149#define DRPD 0x0020 /* b5: D+/- pull down control */ 150#define DPRPU 0x0010 /* b4: D+ pull up control */ 151#define USBE 0x0001 /* b0: USB module operation enable */ 152 153/* System Configuration Status Register */ 154#define OVCBIT 0x8000 /* b15-14: Over-current bit */ 155#define OVCMON 0xC000 /* b15-14: Over-current monitor */ 156#define SOFEA 0x0020 /* b5: SOF monitor */ 157#define IDMON 0x0004 /* b3: ID-pin monitor */ 158#define LNST 0x0003 /* b1-0: D+, D- line status */ 159#define SE1 0x0003 /* SE1 */ 160#define FS_KSTS 0x0002 /* Full-Speed K State */ 161#define FS_JSTS 0x0001 /* Full-Speed J State */ 162#define LS_JSTS 0x0002 /* Low-Speed J State */ 163#define LS_KSTS 0x0001 /* Low-Speed K State */ 164#define SE0 0x0000 /* SE0 */ 165 166/* Device State Control Register */ 167#define EXTLP0 0x0400 /* b10: External port */ 168#define VBOUT 0x0200 /* b9: VBUS output */ 169#define WKUP 0x0100 /* b8: Remote wakeup */ 170#define RWUPE 0x0080 /* b7: Remote wakeup sense */ 171#define USBRST 0x0040 /* b6: USB reset enable */ 172#define RESUME 0x0020 /* b5: Resume enable */ 173#define UACT 0x0010 /* b4: USB bus enable */ 174#define RHST 0x0007 /* b1-0: Reset handshake status */ 175#define HSPROC 0x0004 /* HS handshake is processing */ 176#define HSMODE 0x0003 /* Hi-Speed mode */ 177#define FSMODE 0x0002 /* Full-Speed mode */ 178#define LSMODE 0x0001 /* Low-Speed mode */ 179#define UNDECID 0x0000 /* Undecided */ 180 181/* Test Mode Register */ 182#define UTST 0x000F /* b3-0: Test select */ 183#define H_TST_PACKET 0x000C /* HOST TEST Packet */ 184#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 185#define H_TST_K 0x000A /* HOST TEST K */ 186#define H_TST_J 0x0009 /* HOST TEST J */ 187#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 188#define P_TST_PACKET 0x0004 /* PERI TEST Packet */ 189#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 190#define P_TST_K 0x0002 /* PERI TEST K */ 191#define P_TST_J 0x0001 /* PERI TEST J */ 192#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 193 194/* Data Pin Configuration Register */ 195#define LDRV 0x8000 /* b15: Drive Current Adjust */ 196#define VIF1 0x0000 /* VIF = 1.8V */ 197#define VIF3 0x8000 /* VIF = 3.3V */ 198#define INTA 0x0001 /* b1: USB INT-pin active */ 199 200/* DMAx Pin Configuration Register */ 201#define DREQA 0x4000 /* b14: Dreq active select */ 202#define BURST 0x2000 /* b13: Burst mode */ 203#define DACKA 0x0400 /* b10: Dack active select */ 204#define DFORM 0x0380 /* b9-7: DMA mode select */ 205#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 206#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 207#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 208#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 209#define DENDA 0x0040 /* b6: Dend active select */ 210#define PKTM 0x0020 /* b5: Packet mode */ 211#define DENDE 0x0010 /* b4: Dend enable */ 212#define OBUS 0x0004 /* b2: OUTbus mode */ 213 214/* CFIFO/DxFIFO Port Select Register */ 215#define RCNT 0x8000 /* b15: Read count mode */ 216#define REW 0x4000 /* b14: Buffer rewind */ 217#define DCLRM 0x2000 /* b13: DMA buffer clear mode */ 218#define DREQE 0x1000 /* b12: DREQ output enable */ 219#define MBW_8 0x0000 /* 8bit */ 220#define MBW_16 0x0400 /* 16bit */ 221#define MBW_32 0x0800 /* 32bit */ 222#define BIGEND 0x0100 /* b8: Big endian mode */ 223#define BYTE_LITTLE 0x0000 /* little dendian */ 224#define BYTE_BIG 0x0100 /* big endifan */ 225#define ISEL 0x0020 /* b5: DCP FIFO port direction select */ 226#define CURPIPE 0x000F /* b2-0: PIPE select */ 227 228/* CFIFO/DxFIFO Port Control Register */ 229#define BVAL 0x8000 /* b15: Buffer valid flag */ 230#define BCLR 0x4000 /* b14: Buffer clear */ 231#define FRDY 0x2000 /* b13: FIFO ready */ 232#define DTLN 0x0FFF /* b11-0: FIFO received data length */ 233 234/* Interrupt Enable Register 0 */ 235#define VBSE 0x8000 /* b15: VBUS interrupt */ 236#define RSME 0x4000 /* b14: Resume interrupt */ 237#define SOFE 0x2000 /* b13: Frame update interrupt */ 238#define DVSE 0x1000 /* b12: Device state transition interrupt */ 239#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 240#define BEMPE 0x0400 /* b10: Buffer empty interrupt */ 241#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 242#define BRDYE 0x0100 /* b8: Buffer ready interrupt */ 243 244/* Interrupt Enable Register 1 */ 245#define OVRCRE 0x8000 /* b15: Over-current interrupt */ 246#define BCHGE 0x4000 /* b14: USB us chenge interrupt */ 247#define DTCHE 0x1000 /* b12: Detach sense interrupt */ 248#define ATTCHE 0x0800 /* b11: Attach sense interrupt */ 249#define EOFERRE 0x0040 /* b6: EOF error interrupt */ 250#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 251#define SACKE 0x0010 /* b4: SETUP ACK interrupt */ 252 253/* BRDY Interrupt Enable/Status Register */ 254#define BRDY9 0x0200 /* b9: PIPE9 */ 255#define BRDY8 0x0100 /* b8: PIPE8 */ 256#define BRDY7 0x0080 /* b7: PIPE7 */ 257#define BRDY6 0x0040 /* b6: PIPE6 */ 258#define BRDY5 0x0020 /* b5: PIPE5 */ 259#define BRDY4 0x0010 /* b4: PIPE4 */ 260#define BRDY3 0x0008 /* b3: PIPE3 */ 261#define BRDY2 0x0004 /* b2: PIPE2 */ 262#define BRDY1 0x0002 /* b1: PIPE1 */ 263#define BRDY0 0x0001 /* b1: PIPE0 */ 264 265/* NRDY Interrupt Enable/Status Register */ 266#define NRDY9 0x0200 /* b9: PIPE9 */ 267#define NRDY8 0x0100 /* b8: PIPE8 */ 268#define NRDY7 0x0080 /* b7: PIPE7 */ 269#define NRDY6 0x0040 /* b6: PIPE6 */ 270#define NRDY5 0x0020 /* b5: PIPE5 */ 271#define NRDY4 0x0010 /* b4: PIPE4 */ 272#define NRDY3 0x0008 /* b3: PIPE3 */ 273#define NRDY2 0x0004 /* b2: PIPE2 */ 274#define NRDY1 0x0002 /* b1: PIPE1 */ 275#define NRDY0 0x0001 /* b1: PIPE0 */ 276 277/* BEMP Interrupt Enable/Status Register */ 278#define BEMP9 0x0200 /* b9: PIPE9 */ 279#define BEMP8 0x0100 /* b8: PIPE8 */ 280#define BEMP7 0x0080 /* b7: PIPE7 */ 281#define BEMP6 0x0040 /* b6: PIPE6 */ 282#define BEMP5 0x0020 /* b5: PIPE5 */ 283#define BEMP4 0x0010 /* b4: PIPE4 */ 284#define BEMP3 0x0008 /* b3: PIPE3 */ 285#define BEMP2 0x0004 /* b2: PIPE2 */ 286#define BEMP1 0x0002 /* b1: PIPE1 */ 287#define BEMP0 0x0001 /* b0: PIPE0 */ 288 289/* SOF Pin Configuration Register */ 290#define TRNENSEL 0x0100 /* b8: Select transaction enable period */ 291#define BRDYM 0x0040 /* b6: BRDY clear timing */ 292#define INTL 0x0020 /* b5: Interrupt sense select */ 293#define EDGESTS 0x0010 /* b4: */ 294#define SOFMODE 0x000C /* b3-2: SOF pin select */ 295#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ 296#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 297#define SOF_DISABLE 0x0000 /* SOF OUT Disable */ 298 299/* Interrupt Status Register 0 */ 300#define VBINT 0x8000 /* b15: VBUS interrupt */ 301#define RESM 0x4000 /* b14: Resume interrupt */ 302#define SOFR 0x2000 /* b13: SOF frame update interrupt */ 303#define DVST 0x1000 /* b12: Device state transition interrupt */ 304#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 305#define BEMP 0x0400 /* b10: Buffer empty interrupt */ 306#define NRDY 0x0200 /* b9: Buffer not ready interrupt */ 307#define BRDY 0x0100 /* b8: Buffer ready interrupt */ 308#define VBSTS 0x0080 /* b7: VBUS input port */ 309#define DVSQ 0x0070 /* b6-4: Device state */ 310#define DS_SPD_CNFG 0x0070 /* Suspend Configured */ 311#define DS_SPD_ADDR 0x0060 /* Suspend Address */ 312#define DS_SPD_DFLT 0x0050 /* Suspend Default */ 313#define DS_SPD_POWR 0x0040 /* Suspend Powered */ 314#define DS_SUSP 0x0040 /* Suspend */ 315#define DS_CNFG 0x0030 /* Configured */ 316#define DS_ADDS 0x0020 /* Address */ 317#define DS_DFLT 0x0010 /* Default */ 318#define DS_POWR 0x0000 /* Powered */ 319#define DVSQS 0x0030 /* b5-4: Device state */ 320#define VALID 0x0008 /* b3: Setup packet detected flag */ 321#define CTSQ 0x0007 /* b2-0: Control transfer stage */ 322#define CS_SQER 0x0006 /* Sequence error */ 323#define CS_WRND 0x0005 /* Control write nodata status stage */ 324#define CS_WRSS 0x0004 /* Control write status stage */ 325#define CS_WRDS 0x0003 /* Control write data stage */ 326#define CS_RDSS 0x0002 /* Control read status stage */ 327#define CS_RDDS 0x0001 /* Control read data stage */ 328#define CS_IDST 0x0000 /* Idle or setup stage */ 329 330/* Interrupt Status Register 1 */ 331#define OVRCR 0x8000 /* b15: Over-current interrupt */ 332#define BCHG 0x4000 /* b14: USB bus chenge interrupt */ 333#define DTCH 0x1000 /* b12: Detach sense interrupt */ 334#define ATTCH 0x0800 /* b11: Attach sense interrupt */ 335#define EOFERR 0x0040 /* b6: EOF-error interrupt */ 336#define SIGN 0x0020 /* b5: Setup ignore interrupt */ 337#define SACK 0x0010 /* b4: Setup acknowledge interrupt */ 338 339/* Frame Number Register */ 340#define OVRN 0x8000 /* b15: Overrun error */ 341#define CRCE 0x4000 /* b14: Received data error */ 342#define FRNM 0x07FF /* b10-0: Frame number */ 343 344/* Micro Frame Number Register */ 345#define UFRNM 0x0007 /* b2-0: Micro frame number */ 346 347/* Default Control Pipe Maxpacket Size Register */ 348/* Pipe Maxpacket Size Register */ 349#define DEVSEL 0xF000 /* b15-14: Device address select */ 350#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 351 352/* Default Control Pipe Control Register */ 353#define BSTS 0x8000 /* b15: Buffer status */ 354#define SUREQ 0x4000 /* b14: Send USB request */ 355#define CSCLR 0x2000 /* b13: complete-split status clear */ 356#define CSSTS 0x1000 /* b12: complete-split status */ 357#define SUREQCLR 0x0800 /* b11: stop setup request */ 358#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 359#define SQSET 0x0080 /* b7: Sequence toggle bit set */ 360#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 361#define PBUSY 0x0020 /* b5: pipe busy */ 362#define PINGE 0x0010 /* b4: ping enable */ 363#define CCPL 0x0004 /* b2: Enable control transfer complete */ 364#define PID 0x0003 /* b1-0: Response PID */ 365#define PID_STALL11 0x0003 /* STALL */ 366#define PID_STALL 0x0002 /* STALL */ 367#define PID_BUF 0x0001 /* BUF */ 368#define PID_NAK 0x0000 /* NAK */ 369 370/* Pipe Window Select Register */ 371#define PIPENM 0x0007 /* b2-0: Pipe select */ 372 373/* Pipe Configuration Register */ 374#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ 375#define R8A66597_ISO 0xC000 /* Isochronous */ 376#define R8A66597_INT 0x8000 /* Interrupt */ 377#define R8A66597_BULK 0x4000 /* Bulk */ 378#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ 379#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ 380#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 381#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ 382#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ 383#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ 384 385/* Pipe Buffer Configuration Register */ 386#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 387#define BUFNMB 0x007F /* b6-0: Pipe buffer number */ 388#define PIPE0BUF 256 389#define PIPExBUF 64 390 391/* Pipe Maxpacket Size Register */ 392#define MXPS 0x07FF /* b10-0: Maxpacket size */ 393 394/* Pipe Cycle Configuration Register */ 395#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 396#define IITV 0x0007 /* b2-0: Isochronous interval */ 397 398/* Pipex Control Register */ 399#define BSTS 0x8000 /* b15: Buffer status */ 400#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 401#define CSCLR 0x2000 /* b13: complete-split status clear */ 402#define CSSTS 0x1000 /* b12: complete-split status */ 403#define ATREPM 0x0400 /* b10: Auto repeat mode */ 404#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 405#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 406#define SQSET 0x0080 /* b7: Sequence toggle bit set */ 407#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 408#define PBUSY 0x0020 /* b5: pipe busy */ 409#define PID 0x0003 /* b1-0: Response PID */ 410 411/* PIPExTRE */ 412#define TRENB 0x0200 /* b9: Transaction counter enable */ 413#define TRCLR 0x0100 /* b8: Transaction counter clear */ 414 415/* PIPExTRN */ 416#define TRNCNT 0xFFFF /* b15-0: Transaction counter */ 417 418/* DEVADDx */ 419#define UPPHUB 0x7800 420#define HUBPORT 0x0700 421#define USBSPD 0x00C0 422#define RTPORT 0x0001 423 424/* SUDMAC registers */ 425#define CH0CFG 0x00 426#define CH1CFG 0x04 427#define CH0BA 0x10 428#define CH1BA 0x14 429#define CH0BBC 0x18 430#define CH1BBC 0x1C 431#define CH0CA 0x20 432#define CH1CA 0x24 433#define CH0CBC 0x28 434#define CH1CBC 0x2C 435#define CH0DEN 0x30 436#define CH1DEN 0x34 437#define DSTSCLR 0x38 438#define DBUFCTRL 0x3C 439#define DINTCTRL 0x40 440#define DINTSTS 0x44 441#define DINTSTSCLR 0x48 442#define CH0SHCTRL 0x50 443#define CH1SHCTRL 0x54 444 445/* SUDMAC Configuration Registers */ 446#define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */ 447#define RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */ 448#define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */ 449 450/* DMA Enable Registers */ 451#define DEN 0x0001 /* b1: DMA Transfer Enable */ 452 453/* DMA Status Clear Register */ 454#define CH1STCLR 0x0002 /* b2: Ch1 DMA Status Clear */ 455#define CH0STCLR 0x0001 /* b1: Ch0 DMA Status Clear */ 456 457/* DMA Buffer Control Register */ 458#define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */ 459#define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */ 460#define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */ 461#define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */ 462 463/* DMA Interrupt Control Register */ 464#define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */ 465#define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */ 466#define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */ 467#define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */ 468 469/* DMA Interrupt Status Register */ 470#define CH1ERRS 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */ 471#define CH0ERRS 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */ 472#define CH1ENDS 0x0002 /* b2: Ch1 DMA Transfer End Int Status */ 473#define CH0ENDS 0x0001 /* b1: Ch0 DMA Transfer End Int Status */ 474 475/* DMA Interrupt Status Clear Register */ 476#define CH1ERRC 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */ 477#define CH0ERRC 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */ 478#define CH1ENDC 0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */ 479#define CH0ENDC 0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */ 480 481#endif /* __LINUX_USB_R8A66597_H */ 482