cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra_usb_phy.h (2753B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2010 Google, Inc.
      4 *
      5 * This software is licensed under the terms of the GNU General Public
      6 * License version 2, as published by the Free Software Foundation, and
      7 * may be copied, distributed, and modified under those terms.
      8 *
      9 * This program is distributed in the hope that it will be useful,
     10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12 * GNU General Public License for more details.
     13 *
     14 */
     15
     16#ifndef __TEGRA_USB_PHY_H
     17#define __TEGRA_USB_PHY_H
     18
     19#include <linux/clk.h>
     20#include <linux/gpio.h>
     21#include <linux/regmap.h>
     22#include <linux/reset.h>
     23#include <linux/usb/otg.h>
     24
     25/*
     26 * utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
     27 *     should be set up by clk-tegra, false if by the PHY code
     28 * has_hostpc: true if the USB controller has the HOSTPC extension, which
     29 *     changes the location of the PHCD and PTS fields
     30 * requires_usbmode_setup: true if the USBMODE register needs to be set to
     31 *      enter host mode
     32 * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
     33 *      and hsdiscon_level should be set for adequate signal quality
     34 * requires_pmc_ao_power_up: true if USB AO is powered down by default
     35 */
     36
     37struct tegra_phy_soc_config {
     38	bool utmi_pll_config_in_car_module;
     39	bool has_hostpc;
     40	bool requires_usbmode_setup;
     41	bool requires_extra_tuning_parameters;
     42	bool requires_pmc_ao_power_up;
     43};
     44
     45struct tegra_utmip_config {
     46	u8 hssync_start_delay;
     47	u8 elastic_limit;
     48	u8 idle_wait_delay;
     49	u8 term_range_adj;
     50	bool xcvr_setup_use_fuses;
     51	u8 xcvr_setup;
     52	u8 xcvr_lsfslew;
     53	u8 xcvr_lsrslew;
     54	u8 xcvr_hsslew;
     55	u8 hssquelch_level;
     56	u8 hsdiscon_level;
     57};
     58
     59enum tegra_usb_phy_port_speed {
     60	TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
     61	TEGRA_USB_PHY_PORT_SPEED_LOW,
     62	TEGRA_USB_PHY_PORT_SPEED_HIGH,
     63};
     64
     65struct tegra_xtal_freq;
     66
     67struct tegra_usb_phy {
     68	int irq;
     69	int instance;
     70	const struct tegra_xtal_freq *freq;
     71	void __iomem *regs;
     72	void __iomem *pad_regs;
     73	struct clk *clk;
     74	struct clk *pll_u;
     75	struct clk *pad_clk;
     76	struct regulator *vbus;
     77	struct regmap *pmc_regmap;
     78	enum usb_dr_mode mode;
     79	void *config;
     80	const struct tegra_phy_soc_config *soc_config;
     81	struct usb_phy *ulpi;
     82	struct usb_phy u_phy;
     83	bool is_legacy_phy;
     84	bool is_ulpi_phy;
     85	struct gpio_desc *reset_gpio;
     86	struct reset_control *pad_rst;
     87	bool wakeup_enabled;
     88	bool pad_wakeup;
     89	bool powered_on;
     90};
     91
     92void tegra_usb_phy_preresume(struct usb_phy *phy);
     93
     94void tegra_usb_phy_postresume(struct usb_phy *phy);
     95
     96void tegra_ehci_phy_restore_start(struct usb_phy *phy,
     97				 enum tegra_usb_phy_port_speed port_speed);
     98
     99void tegra_ehci_phy_restore_end(struct usb_phy *phy);
    100
    101#endif /* __TEGRA_USB_PHY_H */