via-core.h (6723B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved. 4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net> 6 * Copyright 2010 Florian Tobias Schandinat <FlorianSchandinat@gmx.de> 7 */ 8 9#ifndef __VIA_CORE_H__ 10#define __VIA_CORE_H__ 11#include <linux/types.h> 12#include <linux/io.h> 13#include <linux/spinlock.h> 14#include <linux/pci.h> 15 16/* 17 * A description of each known serial I2C/GPIO port. 18 */ 19enum via_port_type { 20 VIA_PORT_NONE = 0, 21 VIA_PORT_I2C, 22 VIA_PORT_GPIO, 23}; 24 25enum via_port_mode { 26 VIA_MODE_OFF = 0, 27 VIA_MODE_I2C, /* Used as I2C port */ 28 VIA_MODE_GPIO, /* Two GPIO ports */ 29}; 30 31enum viafb_i2c_adap { 32 VIA_PORT_26 = 0, 33 VIA_PORT_31, 34 VIA_PORT_25, 35 VIA_PORT_2C, 36 VIA_PORT_3D, 37}; 38#define VIAFB_NUM_PORTS 5 39 40struct via_port_cfg { 41 enum via_port_type type; 42 enum via_port_mode mode; 43 u16 io_port; 44 u8 ioport_index; 45}; 46 47/* 48 * Allow subdevs to register suspend/resume hooks. 49 */ 50struct viafb_pm_hooks { 51 struct list_head list; 52 int (*suspend)(void *private); 53 int (*resume)(void *private); 54 void *private; 55}; 56 57void viafb_pm_register(struct viafb_pm_hooks *hooks); 58void viafb_pm_unregister(struct viafb_pm_hooks *hooks); 59 60/* 61 * This is the global viafb "device" containing stuff needed by 62 * all subdevs. 63 */ 64struct viafb_dev { 65 struct pci_dev *pdev; 66 int chip_type; 67 struct via_port_cfg *port_cfg; 68 /* 69 * Spinlock for access to device registers. Not yet 70 * globally used. 71 */ 72 spinlock_t reg_lock; 73 /* 74 * The framebuffer MMIO region. Little, if anything, touches 75 * this memory directly, and certainly nothing outside of the 76 * framebuffer device itself. We *do* have to be able to allocate 77 * chunks of this memory for other devices, though. 78 */ 79 unsigned long fbmem_start; 80 long fbmem_len; 81 void __iomem *fbmem; 82#if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE) 83 long camera_fbmem_offset; 84 long camera_fbmem_size; 85#endif 86 /* 87 * The MMIO region for device registers. 88 */ 89 unsigned long engine_start; 90 unsigned long engine_len; 91 void __iomem *engine_mmio; 92 93}; 94 95/* 96 * Interrupt management. 97 */ 98 99void viafb_irq_enable(u32 mask); 100void viafb_irq_disable(u32 mask); 101 102/* 103 * The global interrupt control register and its bits. 104 */ 105#define VDE_INTERRUPT 0x200 /* Video interrupt flags/masks */ 106#define VDE_I_DVISENSE 0x00000001 /* DVI sense int status */ 107#define VDE_I_VBLANK 0x00000002 /* Vertical blank status */ 108#define VDE_I_MCCFI 0x00000004 /* MCE compl. frame int status */ 109#define VDE_I_VSYNC 0x00000008 /* VGA VSYNC int status */ 110#define VDE_I_DMA0DDONE 0x00000010 /* DMA 0 descr done */ 111#define VDE_I_DMA0TDONE 0x00000020 /* DMA 0 transfer done */ 112#define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */ 113#define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */ 114#define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */ 115#define VDE_I_HQV0 0x00000200 /* First HQV engine */ 116#define VDE_I_HQV1 0x00000400 /* Second HQV engine */ 117#define VDE_I_HQV1EN 0x00000800 /* Second HQV engine enable */ 118#define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */ 119#define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */ 120#define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */ 121#define VDE_I_VSYNC2 0x00008000 /* Sec. Disp. VSYNC */ 122#define VDE_I_DVISNSEN 0x00010000 /* DVI sense enable */ 123#define VDE_I_VSYNC2EN 0x00020000 /* Sec Disp VSYNC enable */ 124#define VDE_I_MCCFIEN 0x00040000 /* MC comp frame int mask enable */ 125#define VDE_I_VSYNCEN 0x00080000 /* VSYNC enable */ 126#define VDE_I_DMA0DDEN 0x00100000 /* DMA 0 descr done enable */ 127#define VDE_I_DMA0TDEN 0x00200000 /* DMA 0 trans done enable */ 128#define VDE_I_DMA1DDEN 0x00400000 /* DMA 1 descr done enable */ 129#define VDE_I_DMA1TDEN 0x00800000 /* DMA 1 trans done enable */ 130#define VDE_I_C1AVEN 0x01000000 /* cap 1 act vid end enable */ 131#define VDE_I_HQV0EN 0x02000000 /* First hqv engine enable */ 132#define VDE_I_C1VBIEN 0x04000000 /* Cap 1 VBI end enable */ 133#define VDE_I_LVDSSI 0x08000000 /* LVDS sense interrupt */ 134#define VDE_I_C0AVEN 0x10000000 /* Cap 0 act vid end enable */ 135#define VDE_I_C0VBIEN 0x20000000 /* Cap 0 VBI end enable */ 136#define VDE_I_LVDSSIEN 0x40000000 /* LVDS Sense enable */ 137#define VDE_I_ENABLE 0x80000000 /* Global interrupt enable */ 138 139#if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE) 140/* 141 * DMA management. 142 */ 143int viafb_request_dma(void); 144void viafb_release_dma(void); 145/* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */ 146int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg); 147 148/* 149 * DMA Controller registers. 150 */ 151#define VDMA_MR0 0xe00 /* Mod reg 0 */ 152#define VDMA_MR_CHAIN 0x01 /* Chaining mode */ 153#define VDMA_MR_TDIE 0x02 /* Transfer done int enable */ 154#define VDMA_CSR0 0xe04 /* Control/status */ 155#define VDMA_C_ENABLE 0x01 /* DMA Enable */ 156#define VDMA_C_START 0x02 /* Start a transfer */ 157#define VDMA_C_ABORT 0x04 /* Abort a transfer */ 158#define VDMA_C_DONE 0x08 /* Transfer is done */ 159#define VDMA_MARL0 0xe20 /* Mem addr low */ 160#define VDMA_MARH0 0xe24 /* Mem addr high */ 161#define VDMA_DAR0 0xe28 /* Device address */ 162#define VDMA_DQWCR0 0xe2c /* Count (16-byte) */ 163#define VDMA_TMR0 0xe30 /* Tile mode reg */ 164#define VDMA_DPRL0 0xe34 /* Not sure */ 165#define VDMA_DPR_IN 0x08 /* Inbound transfer to FB */ 166#define VDMA_DPRH0 0xe38 167#define VDMA_PMR0 (0xe00 + 0x134) /* Pitch mode */ 168 169/* 170 * Useful stuff that probably belongs somewhere global. 171 */ 172#define VGA_WIDTH 640 173#define VGA_HEIGHT 480 174#endif /* CONFIG_VIDEO_VIA_CAMERA */ 175 176/* 177 * Indexed port operations. Note that these are all multi-op 178 * functions; every invocation will be racy if you're not holding 179 * reg_lock. 180 */ 181 182#define VIAStatus 0x3DA /* Non-indexed port */ 183#define VIACR 0x3D4 184#define VIASR 0x3C4 185#define VIAGR 0x3CE 186#define VIAAR 0x3C0 187 188static inline u8 via_read_reg(u16 port, u8 index) 189{ 190 outb(index, port); 191 return inb(port + 1); 192} 193 194static inline void via_write_reg(u16 port, u8 index, u8 data) 195{ 196 outb(index, port); 197 outb(data, port + 1); 198} 199 200static inline void via_write_reg_mask(u16 port, u8 index, u8 data, u8 mask) 201{ 202 u8 old; 203 204 outb(index, port); 205 old = inb(port + 1); 206 outb((data & mask) | (old & ~mask), port + 1); 207} 208 209#define VIA_MISC_REG_READ 0x03CC 210#define VIA_MISC_REG_WRITE 0x03C2 211 212static inline void via_write_misc_reg_mask(u8 data, u8 mask) 213{ 214 u8 old = inb(VIA_MISC_REG_READ); 215 outb((data & mask) | (old & ~mask), VIA_MISC_REG_WRITE); 216} 217 218 219#endif /* __VIA_CORE_H__ */