ocelot_qsys.h (14609B)
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2/* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 8#ifndef _MSCC_OCELOT_QSYS_H_ 9#define _MSCC_OCELOT_QSYS_H_ 10 11#define QSYS_PORT_MODE_RSZ 0x4 12 13#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 14#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0) 15 16#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5) 17#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4) 18#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3) 19#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2) 20#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1) 21#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0) 22 23#define QSYS_EEE_CFG_RSZ 0x4 24 25#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) 26#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8) 27#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) 28#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) 29#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0) 30 31#define QSYS_SW_STATUS_RSZ 0x4 32 33#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) 34#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8) 35#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) 36#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) 37#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0) 38 39#define QSYS_QMAP_GSZ 0x4 40 41#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) 42#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5) 43#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) 44#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) 45#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2) 46#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2) 47#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0)) 48#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0) 49 50#define QSYS_ISDX_SGRP_GSZ 0x4 51 52#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4 53 54#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9)) 55#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9) 56#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9) 57#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8) 58#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7) 59#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0)) 60#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0) 61 62#define QSYS_RED_PROFILE_RSZ 0x4 63 64#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8)) 65#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8) 66#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8) 67#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0)) 68#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0) 69 70#define QSYS_RES_CFG_GSZ 0x8 71 72#define QSYS_RES_STAT_GSZ 0x8 73 74#define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x) ((x) & GENMASK(15, 0)) 75#define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT_M GENMASK(15, 0) 76 77#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2)) 78#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2) 79#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2) 80#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0)) 81#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0) 82 83#define QSYS_QMAXSDU_CFG_0_RSZ 0x4 84 85#define QSYS_QMAXSDU_CFG_1_RSZ 0x4 86 87#define QSYS_QMAXSDU_CFG_2_RSZ 0x4 88 89#define QSYS_QMAXSDU_CFG_3_RSZ 0x4 90 91#define QSYS_QMAXSDU_CFG_4_RSZ 0x4 92 93#define QSYS_QMAXSDU_CFG_5_RSZ 0x4 94 95#define QSYS_QMAXSDU_CFG_6_RSZ 0x4 96 97#define QSYS_QMAXSDU_CFG_7_RSZ 0x4 98 99#define QSYS_PREEMPTION_CFG_RSZ 0x4 100 101#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0)) 102#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0) 103#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8)) 104#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8) 105#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8) 106#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12)) 107#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12) 108#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12) 109#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16)) 110#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16) 111#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16) 112 113#define QSYS_CIR_CFG_GSZ 0x80 114 115#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) 116#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6) 117#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) 118#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) 119#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0) 120 121#define QSYS_EIR_CFG_GSZ 0x80 122 123#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7)) 124#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7) 125#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7) 126#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1)) 127#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1) 128#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1) 129#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0) 130 131#define QSYS_SE_CFG_GSZ 0x80 132 133#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6)) 134#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6) 135#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6) 136#define QSYS_SE_CFG_SE_RR_ENA BIT(5) 137#define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 138#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2)) 139#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2) 140#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 141#define QSYS_SE_CFG_SE_EXC_ENA BIT(1) 142#define QSYS_SE_CFG_SE_EXC_FWD BIT(0) 143 144#define QSYS_SE_DWRR_CFG_GSZ 0x80 145#define QSYS_SE_DWRR_CFG_RSZ 0x4 146 147#define QSYS_SE_CONNECT_GSZ 0x80 148 149#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17)) 150#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17) 151#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17) 152#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9)) 153#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9) 154#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9) 155#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5)) 156#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5) 157#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5) 158#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1)) 159#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1) 160#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1) 161#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0) 162 163#define QSYS_SE_DLB_SENSE_GSZ 0x80 164 165#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11)) 166#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11) 167#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11) 168#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7)) 169#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7) 170#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7) 171#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3)) 172#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3) 173#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3) 174#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2) 175#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1) 176#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 177 178#define QSYS_CIR_STATE_GSZ 0x80 179 180#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4)) 181#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4) 182#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4) 183#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0)) 184#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0) 185 186#define QSYS_EIR_STATE_GSZ 0x80 187 188#define QSYS_SE_STATE_GSZ 0x80 189 190#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1)) 191#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1) 192#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1) 193#define QSYS_SE_STATE_SE_WAS_YEL BIT(0) 194 195#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8) 196#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3)) 197#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3) 198#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3) 199#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2) 200#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1) 201#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0) 202 203#define QSYS_TAG_CONFIG_RSZ 0x4 204 205#define QSYS_TAG_CONFIG_ENABLE BIT(0) 206#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4)) 207#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4) 208#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4) 209#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) 210#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8) 211#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) 212#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16)) 213#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16) 214#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16) 215 216#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0)) 217#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0) 218#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8) 219#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16) 220 221#define QSYS_PORT_MAX_SDU_RSZ 0x4 222 223#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) 224#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) 225#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) 226#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16) 227#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) 228 229#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) 230#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) 231#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) 232#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8) 233#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) 234 235#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) 236#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) 237#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) 238#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16) 239#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) 240 241#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) 242#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) 243#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16)) 244#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16) 245#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16) 246#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24) 247 248#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) 249#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) 250#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) 251#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8) 252#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) 253 254#endif