cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fuse.h (1935B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
      4 */
      5
      6#ifndef __SOC_TEGRA_FUSE_H__
      7#define __SOC_TEGRA_FUSE_H__
      8
      9#include <linux/types.h>
     10
     11#define TEGRA20		0x20
     12#define TEGRA30		0x30
     13#define TEGRA114	0x35
     14#define TEGRA124	0x40
     15#define TEGRA132	0x13
     16#define TEGRA210	0x21
     17#define TEGRA186	0x18
     18#define TEGRA194	0x19
     19#define TEGRA234	0x23
     20
     21#define TEGRA_FUSE_SKU_CALIB_0	0xf0
     22#define TEGRA30_FUSE_SATA_CALIB	0x124
     23#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
     24
     25#ifndef __ASSEMBLY__
     26
     27enum tegra_revision {
     28	TEGRA_REVISION_UNKNOWN = 0,
     29	TEGRA_REVISION_A01,
     30	TEGRA_REVISION_A02,
     31	TEGRA_REVISION_A03,
     32	TEGRA_REVISION_A03p,
     33	TEGRA_REVISION_A04,
     34	TEGRA_REVISION_MAX,
     35};
     36
     37struct tegra_sku_info {
     38	int sku_id;
     39	int cpu_process_id;
     40	int cpu_speedo_id;
     41	int cpu_speedo_value;
     42	int cpu_iddq_value;
     43	int soc_process_id;
     44	int soc_speedo_id;
     45	int soc_speedo_value;
     46	int gpu_process_id;
     47	int gpu_speedo_id;
     48	int gpu_speedo_value;
     49	enum tegra_revision revision;
     50};
     51
     52#ifdef CONFIG_ARCH_TEGRA
     53extern struct tegra_sku_info tegra_sku_info;
     54u32 tegra_read_straps(void);
     55u32 tegra_read_ram_code(void);
     56int tegra_fuse_readl(unsigned long offset, u32 *value);
     57u32 tegra_read_chipid(void);
     58u8 tegra_get_chip_id(void);
     59u8 tegra_get_platform(void);
     60bool tegra_is_silicon(void);
     61#else
     62static struct tegra_sku_info tegra_sku_info __maybe_unused;
     63
     64static inline u32 tegra_read_straps(void)
     65{
     66	return 0;
     67}
     68
     69static inline u32 tegra_read_ram_code(void)
     70{
     71	return 0;
     72}
     73
     74static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
     75{
     76	return -ENODEV;
     77}
     78
     79static inline u32 tegra_read_chipid(void)
     80{
     81	return 0;
     82}
     83
     84static inline u8 tegra_get_chip_id(void)
     85{
     86	return 0;
     87}
     88
     89static inline u8 tegra_get_platform(void)
     90{
     91	return 0;
     92}
     93
     94static inline bool tegra_is_silicon(void)
     95{
     96	return false;
     97}
     98#endif
     99
    100struct device *tegra_soc_device_register(void);
    101
    102#endif /* __ASSEMBLY__ */
    103
    104#endif /* __SOC_TEGRA_FUSE_H__ */