ak4113.h (10461B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2#ifndef __SOUND_AK4113_H 3#define __SOUND_AK4113_H 4 5/* 6 * Routines for Asahi Kasei AK4113 7 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 8 * Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>, 9 */ 10 11/* AK4113 registers */ 12/* power down */ 13#define AK4113_REG_PWRDN 0x00 14/* format control */ 15#define AK4113_REG_FORMAT 0x01 16/* input/output control */ 17#define AK4113_REG_IO0 0x02 18/* input/output control */ 19#define AK4113_REG_IO1 0x03 20/* interrupt0 mask */ 21#define AK4113_REG_INT0_MASK 0x04 22/* interrupt1 mask */ 23#define AK4113_REG_INT1_MASK 0x05 24/* DAT mask & DTS select */ 25#define AK4113_REG_DATDTS 0x06 26/* receiver status 0 */ 27#define AK4113_REG_RCS0 0x07 28/* receiver status 1 */ 29#define AK4113_REG_RCS1 0x08 30/* receiver status 2 */ 31#define AK4113_REG_RCS2 0x09 32/* RX channel status byte 0 */ 33#define AK4113_REG_RXCSB0 0x0a 34/* RX channel status byte 1 */ 35#define AK4113_REG_RXCSB1 0x0b 36/* RX channel status byte 2 */ 37#define AK4113_REG_RXCSB2 0x0c 38/* RX channel status byte 3 */ 39#define AK4113_REG_RXCSB3 0x0d 40/* RX channel status byte 4 */ 41#define AK4113_REG_RXCSB4 0x0e 42/* burst preamble Pc byte 0 */ 43#define AK4113_REG_Pc0 0x0f 44/* burst preamble Pc byte 1 */ 45#define AK4113_REG_Pc1 0x10 46/* burst preamble Pd byte 0 */ 47#define AK4113_REG_Pd0 0x11 48/* burst preamble Pd byte 1 */ 49#define AK4113_REG_Pd1 0x12 50/* Q-subcode address + control */ 51#define AK4113_REG_QSUB_ADDR 0x13 52/* Q-subcode track */ 53#define AK4113_REG_QSUB_TRACK 0x14 54/* Q-subcode index */ 55#define AK4113_REG_QSUB_INDEX 0x15 56/* Q-subcode minute */ 57#define AK4113_REG_QSUB_MINUTE 0x16 58/* Q-subcode second */ 59#define AK4113_REG_QSUB_SECOND 0x17 60/* Q-subcode frame */ 61#define AK4113_REG_QSUB_FRAME 0x18 62/* Q-subcode zero */ 63#define AK4113_REG_QSUB_ZERO 0x19 64/* Q-subcode absolute minute */ 65#define AK4113_REG_QSUB_ABSMIN 0x1a 66/* Q-subcode absolute second */ 67#define AK4113_REG_QSUB_ABSSEC 0x1b 68/* Q-subcode absolute frame */ 69#define AK4113_REG_QSUB_ABSFRM 0x1c 70 71/* sizes */ 72#define AK4113_REG_RXCSB_SIZE ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1) 73#define AK4113_REG_QSUB_SIZE ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\ 74 +1) 75 76#define AK4113_WRITABLE_REGS (AK4113_REG_DATDTS + 1) 77 78/* AK4113_REG_PWRDN bits */ 79/* Channel Status Select */ 80#define AK4113_CS12 (1<<7) 81/* Block Start & C/U Output Mode */ 82#define AK4113_BCU (1<<6) 83/* Master Clock Operation Select */ 84#define AK4113_CM1 (1<<5) 85/* Master Clock Operation Select */ 86#define AK4113_CM0 (1<<4) 87/* Master Clock Frequency Select */ 88#define AK4113_OCKS1 (1<<3) 89/* Master Clock Frequency Select */ 90#define AK4113_OCKS0 (1<<2) 91/* 0 = power down, 1 = normal operation */ 92#define AK4113_PWN (1<<1) 93/* 0 = reset & initialize (except thisregister), 1 = normal operation */ 94#define AK4113_RST (1<<0) 95 96/* AK4113_REQ_FORMAT bits */ 97/* V/TX Output select: 0 = Validity Flag Output, 1 = TX */ 98#define AK4113_VTX (1<<7) 99/* Audio Data Control */ 100#define AK4113_DIF2 (1<<6) 101/* Audio Data Control */ 102#define AK4113_DIF1 (1<<5) 103/* Audio Data Control */ 104#define AK4113_DIF0 (1<<4) 105/* Deemphasis Autodetect Enable (1 = enable) */ 106#define AK4113_DEAU (1<<3) 107/* 32kHz-48kHz Deemphasis Control */ 108#define AK4113_DEM1 (1<<2) 109/* 32kHz-48kHz Deemphasis Control */ 110#define AK4113_DEM0 (1<<1) 111#define AK4113_DEM_OFF (AK4113_DEM0) 112#define AK4113_DEM_44KHZ (0) 113#define AK4113_DEM_48KHZ (AK4113_DEM1) 114#define AK4113_DEM_32KHZ (AK4113_DEM0|AK4113_DEM1) 115/* STDO: 16-bit, right justified */ 116#define AK4113_DIF_16R (0) 117/* STDO: 18-bit, right justified */ 118#define AK4113_DIF_18R (AK4113_DIF0) 119/* STDO: 20-bit, right justified */ 120#define AK4113_DIF_20R (AK4113_DIF1) 121/* STDO: 24-bit, right justified */ 122#define AK4113_DIF_24R (AK4113_DIF1|AK4113_DIF0) 123/* STDO: 24-bit, left justified */ 124#define AK4113_DIF_24L (AK4113_DIF2) 125/* STDO: I2S */ 126#define AK4113_DIF_24I2S (AK4113_DIF2|AK4113_DIF0) 127/* STDO: 24-bit, left justified; LRCLK, BICK = Input */ 128#define AK4113_DIF_I24L (AK4113_DIF2|AK4113_DIF1) 129/* STDO: I2S; LRCLK, BICK = Input */ 130#define AK4113_DIF_I24I2S (AK4113_DIF2|AK4113_DIF1|AK4113_DIF0) 131 132/* AK4113_REG_IO0 */ 133/* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ 134#define AK4113_XTL1 (1<<6) 135/* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ 136#define AK4113_XTL0 (1<<5) 137/* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */ 138#define AK4113_UCE (1<<4) 139/* TX Output Enable (1 = enable) */ 140#define AK4113_TXE (1<<3) 141/* Output Through Data Selector for TX pin */ 142#define AK4113_OPS2 (1<<2) 143/* Output Through Data Selector for TX pin */ 144#define AK4113_OPS1 (1<<1) 145/* Output Through Data Selector for TX pin */ 146#define AK4113_OPS0 (1<<0) 147/* 11.2896 MHz ref. Xtal freq. */ 148#define AK4113_XTL_11_2896M (0) 149/* 12.288 MHz ref. Xtal freq. */ 150#define AK4113_XTL_12_288M (AK4113_XTL0) 151/* 24.576 MHz ref. Xtal freq. */ 152#define AK4113_XTL_24_576M (AK4113_XTL1) 153 154/* AK4113_REG_IO1 */ 155/* Interrupt 0 pin Hold */ 156#define AK4113_EFH1 (1<<7) 157/* Interrupt 0 pin Hold */ 158#define AK4113_EFH0 (1<<6) 159#define AK4113_EFH_512LRCLK (0) 160#define AK4113_EFH_1024LRCLK (AK4113_EFH0) 161#define AK4113_EFH_2048LRCLK (AK4113_EFH1) 162#define AK4113_EFH_4096LRCLK (AK4113_EFH1|AK4113_EFH0) 163/* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */ 164#define AK4113_FAST (1<<5) 165/* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */ 166#define AK4113_XMCK (1<<4) 167/* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5 (req. XMCK = 1) */ 168#define AK4113_DIV (1<<3) 169/* Input Recovery Data Select */ 170#define AK4113_IPS2 (1<<2) 171/* Input Recovery Data Select */ 172#define AK4113_IPS1 (1<<1) 173/* Input Recovery Data Select */ 174#define AK4113_IPS0 (1<<0) 175#define AK4113_IPS(x) ((x)&7) 176 177/* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/ 178/* mask enable for QINT bit */ 179#define AK4113_MQI (1<<7) 180/* mask enable for AUTO bit */ 181#define AK4113_MAUT (1<<6) 182/* mask enable for CINT bit */ 183#define AK4113_MCIT (1<<5) 184/* mask enable for UNLOCK bit */ 185#define AK4113_MULK (1<<4) 186/* mask enable for V bit */ 187#define AK4113_V (1<<3) 188/* mask enable for STC bit */ 189#define AK4113_STC (1<<2) 190/* mask enable for AUDN bit */ 191#define AK4113_MAN (1<<1) 192/* mask enable for PAR bit */ 193#define AK4113_MPR (1<<0) 194 195/* AK4113_REG_DATDTS */ 196/* DAT Start ID Counter */ 197#define AK4113_DCNT (1<<4) 198/* DTS-CD 16-bit Sync Word Detect */ 199#define AK4113_DTS16 (1<<3) 200/* DTS-CD 14-bit Sync Word Detect */ 201#define AK4113_DTS14 (1<<2) 202/* mask enable for DAT bit (if 1, no INT1 effect */ 203#define AK4113_MDAT1 (1<<1) 204/* mask enable for DAT bit (if 1, no INT0 effect */ 205#define AK4113_MDAT0 (1<<0) 206 207/* AK4113_REG_RCS0 */ 208/* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ 209#define AK4113_QINT (1<<7) 210/* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ 211#define AK4113_AUTO (1<<6) 212/* channel status buffer interrupt, 0 = no change, 1 = change */ 213#define AK4113_CINT (1<<5) 214/* PLL lock status, 0 = lock, 1 = unlock */ 215#define AK4113_UNLCK (1<<4) 216/* Validity bit, 0 = valid, 1 = invalid */ 217#define AK4113_V (1<<3) 218/* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ 219#define AK4113_STC (1<<2) 220/* audio bit output, 0 = audio, 1 = non-audio */ 221#define AK4113_AUDION (1<<1) 222/* parity error or biphase error status, 0 = no error, 1 = error */ 223#define AK4113_PAR (1<<0) 224 225/* AK4113_REG_RCS1 */ 226/* sampling frequency detection */ 227#define AK4113_FS3 (1<<7) 228#define AK4113_FS2 (1<<6) 229#define AK4113_FS1 (1<<5) 230#define AK4113_FS0 (1<<4) 231/* Pre-emphasis detect, 0 = OFF, 1 = ON */ 232#define AK4113_PEM (1<<3) 233/* DAT Start ID Detect, 0 = no detect, 1 = detect */ 234#define AK4113_DAT (1<<2) 235/* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ 236#define AK4113_DTSCD (1<<1) 237/* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ 238#define AK4113_NPCM (1<<0) 239#define AK4113_FS_8000HZ (AK4113_FS3|AK4113_FS0) 240#define AK4113_FS_11025HZ (AK4113_FS2|AK4113_FS0) 241#define AK4113_FS_16000HZ (AK4113_FS2|AK4113_FS1|AK4113_FS0) 242#define AK4113_FS_22050HZ (AK4113_FS2) 243#define AK4113_FS_24000HZ (AK4113_FS2|AK4113_FS1) 244#define AK4113_FS_32000HZ (AK4113_FS1|AK4113_FS0) 245#define AK4113_FS_44100HZ (0) 246#define AK4113_FS_48000HZ (AK4113_FS1) 247#define AK4113_FS_64000HZ (AK4113_FS3|AK4113_FS1|AK4113_FS0) 248#define AK4113_FS_88200HZ (AK4113_FS3) 249#define AK4113_FS_96000HZ (AK4113_FS3|AK4113_FS1) 250#define AK4113_FS_176400HZ (AK4113_FS3|AK4113_FS2) 251#define AK4113_FS_192000HZ (AK4113_FS3|AK4113_FS2|AK4113_FS1) 252 253/* AK4113_REG_RCS2 */ 254/* CRC for Q-subcode, 0 = no error, 1 = error */ 255#define AK4113_QCRC (1<<1) 256/* CRC for channel status, 0 = no error, 1 = error */ 257#define AK4113_CCRC (1<<0) 258 259/* flags for snd_ak4113_check_rate_and_errors() */ 260#define AK4113_CHECK_NO_STAT (1<<0) /* no statistics */ 261#define AK4113_CHECK_NO_RATE (1<<1) /* no rate check */ 262 263#define AK4113_CONTROLS 13 264 265typedef void (ak4113_write_t)(void *private_data, unsigned char addr, 266 unsigned char data); 267typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr); 268 269enum { 270 AK4113_PARITY_ERRORS, 271 AK4113_V_BIT_ERRORS, 272 AK4113_QCRC_ERRORS, 273 AK4113_CCRC_ERRORS, 274 AK4113_NUM_ERRORS 275}; 276 277struct ak4113 { 278 struct snd_card *card; 279 ak4113_write_t *write; 280 ak4113_read_t *read; 281 void *private_data; 282 atomic_t wq_processing; 283 struct mutex reinit_mutex; 284 spinlock_t lock; 285 unsigned char regmap[AK4113_WRITABLE_REGS]; 286 struct snd_kcontrol *kctls[AK4113_CONTROLS]; 287 struct snd_pcm_substream *substream; 288 unsigned long errors[AK4113_NUM_ERRORS]; 289 unsigned char rcs0; 290 unsigned char rcs1; 291 unsigned char rcs2; 292 struct delayed_work work; 293 unsigned int check_flags; 294 void *change_callback_private; 295 void (*change_callback)(struct ak4113 *ak4113, unsigned char c0, 296 unsigned char c1); 297}; 298 299int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read, 300 ak4113_write_t *write, 301 const unsigned char *pgm, 302 void *private_data, struct ak4113 **r_ak4113); 303void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg, 304 unsigned char mask, unsigned char val); 305void snd_ak4113_reinit(struct ak4113 *ak4113); 306int snd_ak4113_build(struct ak4113 *ak4113, 307 struct snd_pcm_substream *capture_substream); 308int snd_ak4113_external_rate(struct ak4113 *ak4113); 309int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags); 310 311#ifdef CONFIG_PM 312void snd_ak4113_suspend(struct ak4113 *chip); 313void snd_ak4113_resume(struct ak4113 *chip); 314#else 315static inline void snd_ak4113_suspend(struct ak4113 *chip) {} 316static inline void snd_ak4113_resume(struct ak4113 *chip) {} 317#endif 318 319#endif /* __SOUND_AK4113_H */ 320