cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xtensa.h (1032B)


      1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
      2/*
      3 * This file is provided under a dual BSD/GPLv2 license.  When using or
      4 * redistributing this file, you may do so under either license.
      5 *
      6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
      7 */
      8
      9#ifndef __INCLUDE_SOUND_SOF_XTENSA_H__
     10#define __INCLUDE_SOUND_SOF_XTENSA_H__
     11
     12#include <sound/sof/header.h>
     13
     14/*
     15 * Architecture specific debug
     16 */
     17
     18/* Xtensa Firmware Oops data */
     19struct sof_ipc_dsp_oops_xtensa {
     20	struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
     21	struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
     22	uint32_t exccause;
     23	uint32_t excvaddr;
     24	uint32_t ps;
     25	uint32_t epc1;
     26	uint32_t epc2;
     27	uint32_t epc3;
     28	uint32_t epc4;
     29	uint32_t epc5;
     30	uint32_t epc6;
     31	uint32_t epc7;
     32	uint32_t eps2;
     33	uint32_t eps3;
     34	uint32_t eps4;
     35	uint32_t eps5;
     36	uint32_t eps6;
     37	uint32_t eps7;
     38	uint32_t depc;
     39	uint32_t intenable;
     40	uint32_t interrupt;
     41	uint32_t sar;
     42	uint32_t debugcause;
     43	uint32_t windowbase;
     44	uint32_t windowstart;
     45	uint32_t excsave1;
     46	uint32_t ar[];
     47}  __packed;
     48
     49#endif