cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qxl_drm.h (4131B)


      1/*
      2 * Copyright 2013 Red Hat
      3 * All Rights Reserved.
      4 *
      5 * Permission is hereby granted, free of charge, to any person obtaining a
      6 * copy of this software and associated documentation files (the "Software"),
      7 * to deal in the Software without restriction, including without limitation
      8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9 * and/or sell copies of the Software, and to permit persons to whom the
     10 * Software is furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice (including the next
     13 * paragraph) shall be included in all copies or substantial portions of the
     14 * Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22 * OTHER DEALINGS IN THE SOFTWARE.
     23 */
     24#ifndef QXL_DRM_H
     25#define QXL_DRM_H
     26
     27#include "drm.h"
     28
     29#if defined(__cplusplus)
     30extern "C" {
     31#endif
     32
     33/* Please note that modifications to all structs defined here are
     34 * subject to backwards-compatibility constraints.
     35 *
     36 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
     37 * compatibility Keep fields aligned to their size
     38 */
     39
     40#define QXL_GEM_DOMAIN_CPU 0
     41#define QXL_GEM_DOMAIN_VRAM 1
     42#define QXL_GEM_DOMAIN_SURFACE 2
     43
     44#define DRM_QXL_ALLOC       0x00
     45#define DRM_QXL_MAP         0x01
     46#define DRM_QXL_EXECBUFFER  0x02
     47#define DRM_QXL_UPDATE_AREA 0x03
     48#define DRM_QXL_GETPARAM    0x04
     49#define DRM_QXL_CLIENTCAP   0x05
     50
     51#define DRM_QXL_ALLOC_SURF  0x06
     52
     53struct drm_qxl_alloc {
     54	__u32 size;
     55	__u32 handle; /* 0 is an invalid handle */
     56};
     57
     58struct drm_qxl_map {
     59	__u64 offset; /* use for mmap system call */
     60	__u32 handle;
     61	__u32 pad;
     62};
     63
     64/*
     65 * dest is the bo we are writing the relocation into
     66 * src is bo we are relocating.
     67 * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
     68 * src_offset)
     69 */
     70#define QXL_RELOC_TYPE_BO 1
     71#define QXL_RELOC_TYPE_SURF 2
     72
     73struct drm_qxl_reloc {
     74	__u64 src_offset; /* offset into src_handle or src buffer */
     75	__u64 dst_offset; /* offset in dest handle */
     76	__u32 src_handle; /* dest handle to compute address from */
     77	__u32 dst_handle; /* 0 if to command buffer */
     78	__u32 reloc_type;
     79	__u32 pad;
     80};
     81
     82struct drm_qxl_command {
     83	__u64		command; /* void* */
     84	__u64		relocs; /* struct drm_qxl_reloc* */
     85	__u32		type;
     86	__u32		command_size;
     87	__u32		relocs_num;
     88	__u32                pad;
     89};
     90
     91struct drm_qxl_execbuffer {
     92	__u32		flags;		/* for future use */
     93	__u32		commands_num;
     94	__u64		commands;	/* struct drm_qxl_command* */
     95};
     96
     97struct drm_qxl_update_area {
     98	__u32 handle;
     99	__u32 top;
    100	__u32 left;
    101	__u32 bottom;
    102	__u32 right;
    103	__u32 pad;
    104};
    105
    106#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
    107#define QXL_PARAM_MAX_RELOCS 2
    108struct drm_qxl_getparam {
    109	__u64 param;
    110	__u64 value;
    111};
    112
    113/* these are one bit values */
    114struct drm_qxl_clientcap {
    115	__u32 index;
    116	__u32 pad;
    117};
    118
    119struct drm_qxl_alloc_surf {
    120	__u32 format;
    121	__u32 width;
    122	__u32 height;
    123	__s32 stride;
    124	__u32 handle;
    125	__u32 pad;
    126};
    127
    128#define DRM_IOCTL_QXL_ALLOC \
    129	DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
    130
    131#define DRM_IOCTL_QXL_MAP \
    132	DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
    133
    134#define DRM_IOCTL_QXL_EXECBUFFER \
    135	DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
    136		struct drm_qxl_execbuffer)
    137
    138#define DRM_IOCTL_QXL_UPDATE_AREA \
    139	DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
    140		struct drm_qxl_update_area)
    141
    142#define DRM_IOCTL_QXL_GETPARAM \
    143	DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
    144		struct drm_qxl_getparam)
    145
    146#define DRM_IOCTL_QXL_CLIENTCAP \
    147	DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
    148		struct drm_qxl_clientcap)
    149
    150#define DRM_IOCTL_QXL_ALLOC_SURF \
    151	DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
    152		struct drm_qxl_alloc_surf)
    153
    154#if defined(__cplusplus)
    155}
    156#endif
    157
    158#endif