cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hsi_char.h (1895B)

      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2/*
      3 * Part of the HSI character device driver.
      4 *
      5 * Copyright (C) 2010 Nokia Corporation. All rights reserved.
      6 *
      7 * Contact: Andras Domokos <andras.domokos at nokia.com>
      8 *
      9 * This program is free software; you can redistribute it and/or
     10 * modify it under the terms of the GNU General Public License
     11 * version 2 as published by the Free Software Foundation.
     12 *
     13 * This program is distributed in the hope that it will be useful, but
     14 * WITHOUT ANY WARRANTY; without even the implied warranty of
     15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
     16 * General Public License for more details.
     17 *
     18 * You should have received a copy of the GNU General Public License
     19 * along with this program; if not, write to the Free Software
     20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
     21 * 02110-1301 USA
     22 */
     23
     24#ifndef __HSI_CHAR_H
     25#define __HSI_CHAR_H
     26
     27#include <linux/types.h>
     28
     29#define HSI_CHAR_MAGIC		'k'
     30#define HSC_IOW(num, dtype)	_IOW(HSI_CHAR_MAGIC, num, dtype)
     31#define HSC_IOR(num, dtype)	_IOR(HSI_CHAR_MAGIC, num, dtype)
     32#define HSC_IOWR(num, dtype)	_IOWR(HSI_CHAR_MAGIC, num, dtype)
     33#define HSC_IO(num)		_IO(HSI_CHAR_MAGIC, num)
     34
     35#define HSC_RESET		HSC_IO(16)
     36#define HSC_SET_PM		HSC_IO(17)
     37#define HSC_SEND_BREAK		HSC_IO(18)
     38#define HSC_SET_RX		HSC_IOW(19, struct hsc_rx_config)
     39#define HSC_GET_RX		HSC_IOW(20, struct hsc_rx_config)
     40#define HSC_SET_TX		HSC_IOW(21, struct hsc_tx_config)
     41#define HSC_GET_TX		HSC_IOW(22, struct hsc_tx_config)
     42
     43#define HSC_PM_DISABLE		0
     44#define HSC_PM_ENABLE		1
     45
     46#define HSC_MODE_STREAM		1
     47#define HSC_MODE_FRAME		2
     48#define HSC_FLOW_SYNC		0
     49#define HSC_ARB_RR		0
     50#define HSC_ARB_PRIO		1
     51
     52struct hsc_rx_config {
     53	__u32 mode;
     54	__u32 flow;
     55	__u32 channels;
     56};
     57
     58struct hsc_tx_config {
     59	__u32 mode;
     60	__u32 channels;
     61	__u32 speed;
     62	__u32 arb_mode;
     63};
     64
     65#endif /* __HSI_CHAR_H */