habanalabs.h (51556B)
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2 * 3 * Copyright 2016-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8#ifndef HABANALABS_H_ 9#define HABANALABS_H_ 10 11#include <linux/types.h> 12#include <linux/ioctl.h> 13 14/* 15 * Defines that are asic-specific but constitutes as ABI between kernel driver 16 * and userspace 17 */ 18#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 19#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ 20 21/* 22 * 128 SOBs reserved for collective wait 23 * 16 SOBs reserved for sync stream 24 */ 25#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 27/* 28 * 64 monitors reserved for collective wait 29 * 8 monitors reserved for sync stream 30 */ 31#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 32 33/* Max number of elements in timestamps registration buffers */ 34#define TS_MAX_ELEMENTS_NUM (1 << 20) /* 1MB */ 35 36/* 37 * Goya queue Numbering 38 * 39 * The external queues (PCI DMA channels) MUST be before the internal queues 40 * and each group (PCI DMA channels and internal) must be contiguous inside 41 * itself but there can be a gap between the two groups (although not 42 * recommended) 43 */ 44 45enum goya_queue_id { 46 GOYA_QUEUE_ID_DMA_0 = 0, 47 GOYA_QUEUE_ID_DMA_1 = 1, 48 GOYA_QUEUE_ID_DMA_2 = 2, 49 GOYA_QUEUE_ID_DMA_3 = 3, 50 GOYA_QUEUE_ID_DMA_4 = 4, 51 GOYA_QUEUE_ID_CPU_PQ = 5, 52 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */ 53 GOYA_QUEUE_ID_TPC0 = 7, 54 GOYA_QUEUE_ID_TPC1 = 8, 55 GOYA_QUEUE_ID_TPC2 = 9, 56 GOYA_QUEUE_ID_TPC3 = 10, 57 GOYA_QUEUE_ID_TPC4 = 11, 58 GOYA_QUEUE_ID_TPC5 = 12, 59 GOYA_QUEUE_ID_TPC6 = 13, 60 GOYA_QUEUE_ID_TPC7 = 14, 61 GOYA_QUEUE_ID_SIZE 62}; 63 64/* 65 * Gaudi queue Numbering 66 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. 67 * Except one CPU queue, all the rest are internal queues. 68 */ 69 70enum gaudi_queue_id { 71 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ 72 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ 73 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ 74 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ 75 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ 76 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ 77 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ 78 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ 79 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ 80 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ 81 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ 82 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ 83 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ 84 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ 85 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ 86 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ 87 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ 88 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ 89 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ 90 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ 91 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ 92 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */ 93 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */ 94 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */ 95 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */ 96 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ 97 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ 98 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ 99 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ 100 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ 101 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ 102 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ 103 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ 104 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ 105 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ 106 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ 107 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ 108 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ 109 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ 110 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ 111 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ 112 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ 113 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ 114 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ 115 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ 116 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ 117 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ 118 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ 119 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ 120 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ 121 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ 122 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ 123 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ 124 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ 125 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ 126 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ 127 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ 128 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ 129 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ 130 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ 131 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ 132 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ 133 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ 134 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ 135 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ 136 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ 137 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ 138 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ 139 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ 140 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ 141 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ 142 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ 143 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ 144 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ 145 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ 146 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ 147 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ 148 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ 149 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ 150 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ 151 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ 152 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ 153 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ 154 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ 155 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ 156 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ 157 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ 158 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ 159 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ 160 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ 161 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ 162 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ 163 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ 164 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ 165 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ 166 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ 167 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ 168 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ 169 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ 170 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ 171 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ 172 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ 173 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ 174 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ 175 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ 176 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ 177 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ 178 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ 179 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ 180 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ 181 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ 182 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ 183 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ 184 GAUDI_QUEUE_ID_SIZE 185}; 186 187/* 188 * Engine Numbering 189 * 190 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' 191 */ 192 193enum goya_engine_id { 194 GOYA_ENGINE_ID_DMA_0 = 0, 195 GOYA_ENGINE_ID_DMA_1, 196 GOYA_ENGINE_ID_DMA_2, 197 GOYA_ENGINE_ID_DMA_3, 198 GOYA_ENGINE_ID_DMA_4, 199 GOYA_ENGINE_ID_MME_0, 200 GOYA_ENGINE_ID_TPC_0, 201 GOYA_ENGINE_ID_TPC_1, 202 GOYA_ENGINE_ID_TPC_2, 203 GOYA_ENGINE_ID_TPC_3, 204 GOYA_ENGINE_ID_TPC_4, 205 GOYA_ENGINE_ID_TPC_5, 206 GOYA_ENGINE_ID_TPC_6, 207 GOYA_ENGINE_ID_TPC_7, 208 GOYA_ENGINE_ID_SIZE 209}; 210 211enum gaudi_engine_id { 212 GAUDI_ENGINE_ID_DMA_0 = 0, 213 GAUDI_ENGINE_ID_DMA_1, 214 GAUDI_ENGINE_ID_DMA_2, 215 GAUDI_ENGINE_ID_DMA_3, 216 GAUDI_ENGINE_ID_DMA_4, 217 GAUDI_ENGINE_ID_DMA_5, 218 GAUDI_ENGINE_ID_DMA_6, 219 GAUDI_ENGINE_ID_DMA_7, 220 GAUDI_ENGINE_ID_MME_0, 221 GAUDI_ENGINE_ID_MME_1, 222 GAUDI_ENGINE_ID_MME_2, 223 GAUDI_ENGINE_ID_MME_3, 224 GAUDI_ENGINE_ID_TPC_0, 225 GAUDI_ENGINE_ID_TPC_1, 226 GAUDI_ENGINE_ID_TPC_2, 227 GAUDI_ENGINE_ID_TPC_3, 228 GAUDI_ENGINE_ID_TPC_4, 229 GAUDI_ENGINE_ID_TPC_5, 230 GAUDI_ENGINE_ID_TPC_6, 231 GAUDI_ENGINE_ID_TPC_7, 232 GAUDI_ENGINE_ID_NIC_0, 233 GAUDI_ENGINE_ID_NIC_1, 234 GAUDI_ENGINE_ID_NIC_2, 235 GAUDI_ENGINE_ID_NIC_3, 236 GAUDI_ENGINE_ID_NIC_4, 237 GAUDI_ENGINE_ID_NIC_5, 238 GAUDI_ENGINE_ID_NIC_6, 239 GAUDI_ENGINE_ID_NIC_7, 240 GAUDI_ENGINE_ID_NIC_8, 241 GAUDI_ENGINE_ID_NIC_9, 242 GAUDI_ENGINE_ID_SIZE 243}; 244 245/* 246 * ASIC specific PLL index 247 * 248 * Used to retrieve in frequency info of different IPs via 249 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be 250 * used as an index in struct hl_pll_frequency_info 251 */ 252 253enum hl_goya_pll_index { 254 HL_GOYA_CPU_PLL = 0, 255 HL_GOYA_IC_PLL, 256 HL_GOYA_MC_PLL, 257 HL_GOYA_MME_PLL, 258 HL_GOYA_PCI_PLL, 259 HL_GOYA_EMMC_PLL, 260 HL_GOYA_TPC_PLL, 261 HL_GOYA_PLL_MAX 262}; 263 264enum hl_gaudi_pll_index { 265 HL_GAUDI_CPU_PLL = 0, 266 HL_GAUDI_PCI_PLL, 267 HL_GAUDI_SRAM_PLL, 268 HL_GAUDI_HBM_PLL, 269 HL_GAUDI_NIC_PLL, 270 HL_GAUDI_DMA_PLL, 271 HL_GAUDI_MESH_PLL, 272 HL_GAUDI_MME_PLL, 273 HL_GAUDI_TPC_PLL, 274 HL_GAUDI_IF_PLL, 275 HL_GAUDI_PLL_MAX 276}; 277 278/** 279 * enum hl_device_status - Device status information. 280 * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational. 281 * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset. 282 * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable. 283 * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled. 284 * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in 285 * progress. 286 * @HL_DEVICE_STATUS_LAST: Last status. 287 */ 288enum hl_device_status { 289 HL_DEVICE_STATUS_OPERATIONAL, 290 HL_DEVICE_STATUS_IN_RESET, 291 HL_DEVICE_STATUS_MALFUNCTION, 292 HL_DEVICE_STATUS_NEEDS_RESET, 293 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 294 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION 295}; 296 297enum hl_server_type { 298 HL_SERVER_TYPE_UNKNOWN = 0, 299 HL_SERVER_GAUDI_HLS1 = 1, 300 HL_SERVER_GAUDI_HLS1H = 2, 301 HL_SERVER_GAUDI_TYPE1 = 3, 302 HL_SERVER_GAUDI_TYPE2 = 4 303}; 304 305/* Opcode for management ioctl 306 * 307 * HW_IP_INFO - Receive information about different IP blocks in the 308 * device. 309 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event 310 * occurred since the last hard reset. 311 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the 312 * specific context. This is relevant only for devices 313 * where the dram is managed by the kernel driver 314 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each 315 * internal engine. 316 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't 317 * require an open context. 318 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device 319 * over the last period specified by the user. 320 * The period can be between 100ms to 1s, in 321 * resolution of 100ms. The return value is a 322 * percentage of the utilization rate. 323 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each 324 * event occurred since the driver was loaded. 325 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate 326 * of the device in MHz. The maximum clock rate is 327 * configurable via sysfs parameter 328 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset 329 * operations performed on the device since the last 330 * time the driver was loaded. 331 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time 332 * for synchronization. 333 * HL_INFO_CS_COUNTERS - Retrieve command submission counters 334 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters 335 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 336 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 337 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 338 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 339 * HL_INFO_POWER - Retrieve power information 340 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls 341 * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info 342 * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num 343 * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened 344 * and CS timeout or razwi error occurred. 345 * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number. 346 * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi: 347 * Timestamp of razwi. 348 * The address which accessing it caused the razwi. 349 * Razwi initiator. 350 * Razwi cause, was it a page fault or MMU access error. 351 * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation 352 * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications. 353 * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd 354 * HL_INFO_GET_EVENTS - Retrieve the last occurred events 355 */ 356#define HL_INFO_HW_IP_INFO 0 357#define HL_INFO_HW_EVENTS 1 358#define HL_INFO_DRAM_USAGE 2 359#define HL_INFO_HW_IDLE 3 360#define HL_INFO_DEVICE_STATUS 4 361#define HL_INFO_DEVICE_UTILIZATION 6 362#define HL_INFO_HW_EVENTS_AGGREGATE 7 363#define HL_INFO_CLK_RATE 8 364#define HL_INFO_RESET_COUNT 9 365#define HL_INFO_TIME_SYNC 10 366#define HL_INFO_CS_COUNTERS 11 367#define HL_INFO_PCI_COUNTERS 12 368#define HL_INFO_CLK_THROTTLE_REASON 13 369#define HL_INFO_SYNC_MANAGER 14 370#define HL_INFO_TOTAL_ENERGY 15 371#define HL_INFO_PLL_FREQUENCY 16 372#define HL_INFO_POWER 17 373#define HL_INFO_OPEN_STATS 18 374#define HL_INFO_DRAM_REPLACED_ROWS 21 375#define HL_INFO_DRAM_PENDING_ROWS 22 376#define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 377#define HL_INFO_CS_TIMEOUT_EVENT 24 378#define HL_INFO_RAZWI_EVENT 25 379#define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 380#define HL_INFO_REGISTER_EVENTFD 28 381#define HL_INFO_UNREGISTER_EVENTFD 29 382#define HL_INFO_GET_EVENTS 30 383 384#define HL_INFO_VERSION_MAX_LEN 128 385#define HL_INFO_CARD_NAME_MAX_LEN 16 386 387/** 388 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC 389 * @sram_base_address: The first SRAM physical base address that is free to be 390 * used by the user. 391 * @dram_base_address: The first DRAM virtual or physical base address that is 392 * free to be used by the user. 393 * @dram_size: The DRAM size that is available to the user. 394 * @sram_size: The SRAM size that is available to the user. 395 * @num_of_events: The number of events that can be received from the f/w. This 396 * is needed so the user can what is the size of the h/w events 397 * array he needs to pass to the kernel when he wants to fetch 398 * the event counters. 399 * @device_id: PCI device ID of the ASIC. 400 * @module_id: Module ID of the ASIC for mezzanine cards in servers 401 * (From OCP spec). 402 * @first_available_interrupt_id: The first available interrupt ID for the user 403 * to be used when it works with user interrupts. 404 * @server_type: Server type that the Gaudi ASIC is currently installed in. 405 * The value is according to enum hl_server_type 406 * @cpld_version: CPLD version on the board. 407 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. 408 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. 409 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. 410 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler 411 * in some ASICs. 412 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant 413 * for Goya/Gaudi only. 414 * @dram_enabled: Whether the DRAM is enabled. 415 * @cpucp_version: The CPUCP f/w version. 416 * @card_name: The card name as passed by the f/w. 417 * @dram_page_size: The DRAM physical page size. 418 * @number_of_user_interrupts: The number of interrupts that are available to the userspace 419 * application to use. Relevant for Gaudi2 and later. 420 * @device_mem_alloc_default_page_size: default page size used in device memory allocation. 421 */ 422struct hl_info_hw_ip_info { 423 __u64 sram_base_address; 424 __u64 dram_base_address; 425 __u64 dram_size; 426 __u32 sram_size; 427 __u32 num_of_events; 428 __u32 device_id; 429 __u32 module_id; 430 __u32 reserved; 431 __u16 first_available_interrupt_id; 432 __u16 server_type; 433 __u32 cpld_version; 434 __u32 psoc_pci_pll_nr; 435 __u32 psoc_pci_pll_nf; 436 __u32 psoc_pci_pll_od; 437 __u32 psoc_pci_pll_div_factor; 438 __u8 tpc_enabled_mask; 439 __u8 dram_enabled; 440 __u8 pad[2]; 441 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 442 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 443 __u64 reserved2; 444 __u64 dram_page_size; 445 __u32 reserved3; 446 __u16 number_of_user_interrupts; 447 __u16 pad2; 448 __u64 reserved4; 449 __u64 device_mem_alloc_default_page_size; 450}; 451 452struct hl_info_dram_usage { 453 __u64 dram_free_mem; 454 __u64 ctx_dram_mem; 455}; 456 457#define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 458 459struct hl_info_hw_idle { 460 __u32 is_idle; 461 /* 462 * Bitmask of busy engines. 463 * Bits definition is according to `enum <chip>_enging_id'. 464 */ 465 __u32 busy_engines_mask; 466 467 /* 468 * Extended Bitmask of busy engines. 469 * Bits definition is according to `enum <chip>_enging_id'. 470 */ 471 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 472}; 473 474struct hl_info_device_status { 475 __u32 status; 476 __u32 pad; 477}; 478 479struct hl_info_device_utilization { 480 __u32 utilization; 481 __u32 pad; 482}; 483 484struct hl_info_clk_rate { 485 __u32 cur_clk_rate_mhz; 486 __u32 max_clk_rate_mhz; 487}; 488 489struct hl_info_reset_count { 490 __u32 hard_reset_cnt; 491 __u32 soft_reset_cnt; 492}; 493 494struct hl_info_time_sync { 495 __u64 device_time; 496 __u64 host_time; 497}; 498 499/** 500 * struct hl_info_pci_counters - pci counters 501 * @rx_throughput: PCI rx throughput KBps 502 * @tx_throughput: PCI tx throughput KBps 503 * @replay_cnt: PCI replay counter 504 */ 505struct hl_info_pci_counters { 506 __u64 rx_throughput; 507 __u64 tx_throughput; 508 __u64 replay_cnt; 509}; 510 511enum hl_clk_throttling_type { 512 HL_CLK_THROTTLE_TYPE_POWER, 513 HL_CLK_THROTTLE_TYPE_THERMAL, 514 HL_CLK_THROTTLE_TYPE_MAX 515}; 516 517/* clk_throttling_reason masks */ 518#define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) 519#define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL) 520 521/** 522 * struct hl_info_clk_throttle - clock throttling reason 523 * @clk_throttling_reason: each bit represents a clk throttling reason 524 * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event 525 * @clk_throttling_duration_ns: the clock throttle time in nanosec 526 */ 527struct hl_info_clk_throttle { 528 __u32 clk_throttling_reason; 529 __u32 pad; 530 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX]; 531 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX]; 532}; 533 534/** 535 * struct hl_info_energy - device energy information 536 * @total_energy_consumption: total device energy consumption 537 */ 538struct hl_info_energy { 539 __u64 total_energy_consumption; 540}; 541 542#define HL_PLL_NUM_OUTPUTS 4 543 544struct hl_pll_frequency_info { 545 __u16 output[HL_PLL_NUM_OUTPUTS]; 546}; 547 548/** 549 * struct hl_open_stats_info - device open statistics information 550 * @open_counter: ever growing counter, increased on each successful dev open 551 * @last_open_period_ms: duration (ms) device was open last time 552 * @is_compute_ctx_active: Whether there is an active compute context executing 553 * @compute_ctx_in_release: true if the current compute context is being released 554 */ 555struct hl_open_stats_info { 556 __u64 open_counter; 557 __u64 last_open_period_ms; 558 __u8 is_compute_ctx_active; 559 __u8 compute_ctx_in_release; 560 __u8 pad[6]; 561}; 562 563/** 564 * struct hl_power_info - power information 565 * @power: power consumption 566 */ 567struct hl_power_info { 568 __u64 power; 569}; 570 571/** 572 * struct hl_info_sync_manager - sync manager information 573 * @first_available_sync_object: first available sob 574 * @first_available_monitor: first available monitor 575 * @first_available_cq: first available cq 576 */ 577struct hl_info_sync_manager { 578 __u32 first_available_sync_object; 579 __u32 first_available_monitor; 580 __u32 first_available_cq; 581 __u32 reserved; 582}; 583 584/** 585 * struct hl_info_cs_counters - command submission counters 586 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue 587 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue 588 * @total_parsing_drop_cnt: total dropped due to error in packet parsing 589 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing 590 * @total_queue_full_drop_cnt: total dropped due to queue full 591 * @ctx_queue_full_drop_cnt: context dropped due to queue full 592 * @total_device_in_reset_drop_cnt: total dropped due to device in reset 593 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 594 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 595 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 596 * @total_validation_drop_cnt: total dropped due to validation error 597 * @ctx_validation_drop_cnt: context dropped due to validation error 598 */ 599struct hl_info_cs_counters { 600 __u64 total_out_of_mem_drop_cnt; 601 __u64 ctx_out_of_mem_drop_cnt; 602 __u64 total_parsing_drop_cnt; 603 __u64 ctx_parsing_drop_cnt; 604 __u64 total_queue_full_drop_cnt; 605 __u64 ctx_queue_full_drop_cnt; 606 __u64 total_device_in_reset_drop_cnt; 607 __u64 ctx_device_in_reset_drop_cnt; 608 __u64 total_max_cs_in_flight_drop_cnt; 609 __u64 ctx_max_cs_in_flight_drop_cnt; 610 __u64 total_validation_drop_cnt; 611 __u64 ctx_validation_drop_cnt; 612}; 613 614/** 615 * struct hl_info_last_err_open_dev_time - last error boot information. 616 * @timestamp: timestamp of last time the device was opened and error occurred. 617 */ 618struct hl_info_last_err_open_dev_time { 619 __s64 timestamp; 620}; 621 622/** 623 * struct hl_info_cs_timeout_event - last CS timeout information. 624 * @timestamp: timestamp when last CS timeout event occurred. 625 * @seq: sequence number of last CS timeout event. 626 */ 627struct hl_info_cs_timeout_event { 628 __s64 timestamp; 629 __u64 seq; 630}; 631 632#define HL_RAZWI_PAGE_FAULT 0 633#define HL_RAZWI_MMU_ACCESS_ERROR 1 634 635/** 636 * struct hl_info_razwi_event - razwi information. 637 * @timestamp: timestamp of razwi. 638 * @addr: address which accessing it caused razwi. 639 * @engine_id_1: engine id of the razwi initiator, if it was initiated by engine that does not 640 * have engine id it will be set to U16_MAX. 641 * @engine_id_2: second engine id of razwi initiator. Might happen that razwi have 2 possible 642 * engines which one them caused the razwi. In that case, it will contain the 643 * second possible engine id, otherwise it will be set to U16_MAX. 644 * @no_engine_id: if razwi initiator does not have engine id, this field will be set to 1, 645 * otherwise 0. 646 * @error_type: cause of razwi, page fault or access error, otherwise it will be set to U8_MAX. 647 * @pad: padding to 64 bit. 648 */ 649struct hl_info_razwi_event { 650 __s64 timestamp; 651 __u64 addr; 652 __u16 engine_id_1; 653 __u16 engine_id_2; 654 __u8 no_engine_id; 655 __u8 error_type; 656 __u8 pad[2]; 657}; 658 659/** 660 * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. 661 * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size 662 * (e.g. 0x2100000 means that 1MB and 32MB pages are supported). 663 */ 664struct hl_info_dev_memalloc_page_sizes { 665 __u64 page_order_bitmask; 666}; 667 668enum gaudi_dcores { 669 HL_GAUDI_WS_DCORE, 670 HL_GAUDI_WN_DCORE, 671 HL_GAUDI_EN_DCORE, 672 HL_GAUDI_ES_DCORE 673}; 674 675/** 676 * struct hl_info_args - Main structure to retrieve device related information. 677 * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation 678 * mentioned in @op. 679 * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it 680 * limits how many bytes the kernel can write. For hw_events array, the size should be 681 * hl_info_hw_ip_info.num_of_events * sizeof(__u32). 682 * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details. 683 * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores). 684 * @ctx_id: Context ID of the user. Currently not in use. 685 * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms 686 * resolution. Currently not in use. 687 * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration. 688 * @eventfd: event file descriptor for event notifications. 689 * @pad: Padding to 64 bit. 690 */ 691struct hl_info_args { 692 __u64 return_pointer; 693 __u32 return_size; 694 __u32 op; 695 696 union { 697 __u32 dcore_id; 698 __u32 ctx_id; 699 __u32 period_ms; 700 __u32 pll_index; 701 __u32 eventfd; 702 }; 703 704 __u32 pad; 705}; 706 707/* Opcode to create a new command buffer */ 708#define HL_CB_OP_CREATE 0 709/* Opcode to destroy previously created command buffer */ 710#define HL_CB_OP_DESTROY 1 711/* Opcode to retrieve information about a command buffer */ 712#define HL_CB_OP_INFO 2 713 714/* 2MB minus 32 bytes for 2xMSG_PROT */ 715#define HL_MAX_CB_SIZE (0x200000 - 32) 716 717/* Indicates whether the command buffer should be mapped to the device's MMU */ 718#define HL_CB_FLAGS_MAP 0x1 719 720/* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */ 721#define HL_CB_FLAGS_GET_DEVICE_VA 0x2 722 723struct hl_cb_in { 724 /* Handle of CB or 0 if we want to create one */ 725 __u64 cb_handle; 726 /* HL_CB_OP_* */ 727 __u32 op; 728 729 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that 730 * will be allocated, regardless of this parameter's value, is PAGE_SIZE 731 */ 732 __u32 cb_size; 733 734 /* Context ID - Currently not in use */ 735 __u32 ctx_id; 736 /* HL_CB_FLAGS_* */ 737 __u32 flags; 738}; 739 740struct hl_cb_out { 741 union { 742 /* Handle of CB */ 743 __u64 cb_handle; 744 745 union { 746 /* Information about CB */ 747 struct { 748 /* Usage count of CB */ 749 __u32 usage_cnt; 750 __u32 pad; 751 }; 752 753 /* CB mapped address to device MMU */ 754 __u64 device_va; 755 }; 756 }; 757}; 758 759union hl_cb_args { 760 struct hl_cb_in in; 761 struct hl_cb_out out; 762}; 763 764/* HL_CS_CHUNK_FLAGS_ values 765 * 766 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: 767 * Indicates if the CB was allocated and mapped by userspace. 768 * User allocated CB is a command buffer allocated by the user, via malloc 769 * (or similar). After allocating the CB, the user invokes “memory ioctl” 770 * to map the user memory into a device virtual address. The user provides 771 * this address via the cb_handle field. The interface provides the 772 * ability to create a large CBs, Which aren’t limited to 773 * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues 774 * throughput. This CB allocation method also reduces the use of Linux 775 * DMA-able memory pool. Which are limited and used by other Linux 776 * sub-systems. 777 */ 778#define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 779 780/* 781 * This structure size must always be fixed to 64-bytes for backward 782 * compatibility 783 */ 784struct hl_cs_chunk { 785 union { 786 /* For external queue, this represents a Handle of CB on the 787 * Host. 788 * For internal queue in Goya, this represents an SRAM or 789 * a DRAM address of the internal CB. In Gaudi, this might also 790 * represent a mapped host address of the CB. 791 * 792 * A mapped host address is in the device address space, after 793 * a host address was mapped by the device MMU. 794 */ 795 __u64 cb_handle; 796 797 /* Relevant only when HL_CS_FLAGS_WAIT or 798 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 799 * This holds address of array of u64 values that contain 800 * signal CS sequence numbers. The wait described by 801 * this job will listen on all those signals 802 * (wait event per signal) 803 */ 804 __u64 signal_seq_arr; 805 806 /* 807 * Relevant only when HL_CS_FLAGS_WAIT or 808 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 809 * along with HL_CS_FLAGS_ENCAP_SIGNALS. 810 * This is the CS sequence which has the encapsulated signals. 811 */ 812 __u64 encaps_signal_seq; 813 }; 814 815 /* Index of queue to put the CB on */ 816 __u32 queue_index; 817 818 union { 819 /* 820 * Size of command buffer with valid packets 821 * Can be smaller then actual CB size 822 */ 823 __u32 cb_size; 824 825 /* Relevant only when HL_CS_FLAGS_WAIT or 826 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 827 * Number of entries in signal_seq_arr 828 */ 829 __u32 num_signal_seq_arr; 830 831 /* Relevant only when HL_CS_FLAGS_WAIT or 832 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along 833 * with HL_CS_FLAGS_ENCAP_SIGNALS 834 * This set the signals range that the user want to wait for 835 * out of the whole reserved signals range. 836 * e.g if the signals range is 20, and user don't want 837 * to wait for signal 8, so he set this offset to 7, then 838 * he call the API again with 9 and so on till 20. 839 */ 840 __u32 encaps_signal_offset; 841 }; 842 843 /* HL_CS_CHUNK_FLAGS_* */ 844 __u32 cs_chunk_flags; 845 846 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. 847 * This holds the collective engine ID. The wait described by this job 848 * will sync with this engine and with all NICs before completion. 849 */ 850 __u32 collective_engine_id; 851 852 /* Align structure to 64 bytes */ 853 __u32 pad[10]; 854}; 855 856/* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ 857#define HL_CS_FLAGS_FORCE_RESTORE 0x1 858#define HL_CS_FLAGS_SIGNAL 0x2 859#define HL_CS_FLAGS_WAIT 0x4 860#define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 861#define HL_CS_FLAGS_TIMESTAMP 0x20 862#define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 863#define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 864#define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 865#define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 866#define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 867 868/* 869 * The encapsulated signals CS is merged into the existing CS ioctls. 870 * In order to use this feature need to follow the below procedure: 871 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 872 * the output of this API will be the SOB offset from CFG_BASE. 873 * this address will be used to patch CB cmds to do the signaling for this 874 * SOB by incrementing it's value. 875 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 876 * CS type, note that this might fail if out-of-sync happened to the SOB 877 * value, in case other signaling request to the same SOB occurred between 878 * reserve-unreserve calls. 879 * 2. Use the staged CS to do the encapsulated signaling jobs. 880 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 881 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset 882 * field. This offset allows app to wait on part of the reserved signals. 883 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag 884 * to wait for the encapsulated signals. 885 */ 886#define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 887#define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 888#define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 889 890#define HL_CS_STATUS_SUCCESS 0 891 892#define HL_MAX_JOBS_PER_CS 512 893 894struct hl_cs_in { 895 896 /* this holds address of array of hl_cs_chunk for restore phase */ 897 __u64 chunks_restore; 898 899 /* holds address of array of hl_cs_chunk for execution phase */ 900 __u64 chunks_execute; 901 902 union { 903 /* 904 * Sequence number of a staged submission CS 905 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and 906 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset. 907 */ 908 __u64 seq; 909 910 /* 911 * Encapsulated signals handle id 912 * Valid for two flows: 913 * 1. CS with encapsulated signals: 914 * when HL_CS_FLAGS_STAGED_SUBMISSION and 915 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 916 * and HL_CS_FLAGS_ENCAP_SIGNALS are set. 917 * 2. unreserve signals: 918 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set. 919 */ 920 __u32 encaps_sig_handle_id; 921 922 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 923 struct { 924 /* Encapsulated signals number */ 925 __u32 encaps_signals_count; 926 927 /* Encapsulated signals queue index (stream) */ 928 __u32 encaps_signals_q_idx; 929 }; 930 }; 931 932 /* Number of chunks in restore phase array. Maximum number is 933 * HL_MAX_JOBS_PER_CS 934 */ 935 __u32 num_chunks_restore; 936 937 /* Number of chunks in execution array. Maximum number is 938 * HL_MAX_JOBS_PER_CS 939 */ 940 __u32 num_chunks_execute; 941 942 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT 943 * is set 944 */ 945 __u32 timeout; 946 947 /* HL_CS_FLAGS_* */ 948 __u32 cs_flags; 949 950 /* Context ID - Currently not in use */ 951 __u32 ctx_id; 952}; 953 954struct hl_cs_out { 955 union { 956 /* 957 * seq holds the sequence number of the CS to pass to wait 958 * ioctl. All values are valid except for 0 and ULLONG_MAX 959 */ 960 __u64 seq; 961 962 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 963 struct { 964 /* This is the resereved signal handle id */ 965 __u32 handle_id; 966 967 /* This is the signals count */ 968 __u32 count; 969 }; 970 }; 971 972 /* HL_CS_STATUS */ 973 __u32 status; 974 975 /* 976 * SOB base address offset 977 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set 978 */ 979 __u32 sob_base_addr_offset; 980 981 /* 982 * Count of completed signals in SOB before current signal submission. 983 * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION) 984 * or HL_CS_FLAGS_SIGNAL is set 985 */ 986 __u16 sob_count_before_submission; 987 __u16 pad[3]; 988}; 989 990union hl_cs_args { 991 struct hl_cs_in in; 992 struct hl_cs_out out; 993}; 994 995#define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 996#define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 997#define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 998#define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 999#define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20 1000 1001#define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 1002 1003struct hl_wait_cs_in { 1004 union { 1005 struct { 1006 /* 1007 * In case of wait_cs holds the CS sequence number. 1008 * In case of wait for multi CS hold a user pointer to 1009 * an array of CS sequence numbers 1010 */ 1011 __u64 seq; 1012 /* Absolute timeout to wait for command submission 1013 * in microseconds 1014 */ 1015 __u64 timeout_us; 1016 }; 1017 1018 struct { 1019 union { 1020 /* User address for completion comparison. 1021 * upon interrupt, driver will compare the value pointed 1022 * by this address with the supplied target value. 1023 * in order not to perform any comparison, set address 1024 * to all 1s. 1025 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 1026 */ 1027 __u64 addr; 1028 1029 /* cq_counters_handle to a kernel mapped cb which contains 1030 * cq counters. 1031 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set 1032 */ 1033 __u64 cq_counters_handle; 1034 }; 1035 1036 /* Target value for completion comparison */ 1037 __u64 target; 1038 }; 1039 }; 1040 1041 /* Context ID - Currently not in use */ 1042 __u32 ctx_id; 1043 1044 /* HL_WAIT_CS_FLAGS_* 1045 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include 1046 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order 1047 * not to specify an interrupt id ,set mask to all 1s. 1048 */ 1049 __u32 flags; 1050 1051 union { 1052 struct { 1053 /* Multi CS API info- valid entries in multi-CS array */ 1054 __u8 seq_arr_len; 1055 __u8 pad[7]; 1056 }; 1057 1058 /* Absolute timeout to wait for an interrupt in microseconds. 1059 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 1060 */ 1061 __u64 interrupt_timeout_us; 1062 }; 1063 1064 /* 1065 * cq counter offset inside the counters cb pointed by cq_counters_handle above. 1066 * upon interrupt, driver will compare the value pointed 1067 * by this address (cq_counters_handle + cq_counters_offset) 1068 * with the supplied target value. 1069 * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set 1070 */ 1071 __u64 cq_counters_offset; 1072 1073 /* 1074 * Timestamp_handle timestamps buffer handle. 1075 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set 1076 */ 1077 __u64 timestamp_handle; 1078 1079 /* 1080 * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above. 1081 * upon interrupt, if the cq reached the target value then driver will write 1082 * timestamp to this offset. 1083 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set 1084 */ 1085 __u64 timestamp_offset; 1086}; 1087 1088#define HL_WAIT_CS_STATUS_COMPLETED 0 1089#define HL_WAIT_CS_STATUS_BUSY 1 1090#define HL_WAIT_CS_STATUS_TIMEDOUT 2 1091#define HL_WAIT_CS_STATUS_ABORTED 3 1092 1093#define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 1094#define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 1095 1096struct hl_wait_cs_out { 1097 /* HL_WAIT_CS_STATUS_* */ 1098 __u32 status; 1099 /* HL_WAIT_CS_STATUS_FLAG* */ 1100 __u32 flags; 1101 /* 1102 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set 1103 * for wait_cs: timestamp of CS completion 1104 * for wait_multi_cs: timestamp of FIRST CS completion 1105 */ 1106 __s64 timestamp_nsec; 1107 /* multi CS completion bitmap */ 1108 __u32 cs_completion_map; 1109 __u32 pad; 1110}; 1111 1112union hl_wait_cs_args { 1113 struct hl_wait_cs_in in; 1114 struct hl_wait_cs_out out; 1115}; 1116 1117/* Opcode to allocate device memory */ 1118#define HL_MEM_OP_ALLOC 0 1119/* Opcode to free previously allocated device memory */ 1120#define HL_MEM_OP_FREE 1 1121/* Opcode to map host and device memory */ 1122#define HL_MEM_OP_MAP 2 1123/* Opcode to unmap previously mapped host and device memory */ 1124#define HL_MEM_OP_UNMAP 3 1125/* Opcode to map a hw block */ 1126#define HL_MEM_OP_MAP_BLOCK 4 1127/* Opcode to create DMA-BUF object for an existing device memory allocation 1128 * and to export an FD of that DMA-BUF back to the caller 1129 */ 1130#define HL_MEM_OP_EXPORT_DMABUF_FD 5 1131 1132/* Opcode to create timestamps pool for user interrupts registration support 1133 * The memory will be allocated by the kernel driver, A timestamp buffer which the user 1134 * will get handle to it for mmap, and another internal buffer used by the 1135 * driver for registration management 1136 * The memory will be freed when the user closes the file descriptor(ctx close) 1137 */ 1138#define HL_MEM_OP_TS_ALLOC 6 1139 1140/* Memory flags */ 1141#define HL_MEM_CONTIGUOUS 0x1 1142#define HL_MEM_SHARED 0x2 1143#define HL_MEM_USERPTR 0x4 1144#define HL_MEM_FORCE_HINT 0x8 1145#define HL_MEM_PREFETCH 0x40 1146 1147/** 1148 * structure hl_mem_in - structure that handle input args for memory IOCTL 1149 * @union arg: union of structures to be used based on the input operation 1150 * @op: specify the requested memory operation (one of the HL_MEM_OP_* definitions). 1151 * @flags: flags for the memory operation (one of the HL_MEM_* definitions). 1152 * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the DMA-BUF file/FD flags. 1153 * @ctx_id: context ID - currently not in use. 1154 * @num_of_elements: number of timestamp elements used only with HL_MEM_OP_TS_ALLOC opcode. 1155 */ 1156struct hl_mem_in { 1157 union { 1158 /** 1159 * structure for device memory allocation (used with the HL_MEM_OP_ALLOC op) 1160 * @mem_size: memory size to allocate 1161 * @page_size: page size to use on allocation. when the value is 0 the default page 1162 * size will be taken. 1163 */ 1164 struct { 1165 __u64 mem_size; 1166 __u64 page_size; 1167 } alloc; 1168 1169 /** 1170 * structure for free-ing device memory (used with the HL_MEM_OP_FREE op) 1171 * @handle: handle returned from HL_MEM_OP_ALLOC 1172 */ 1173 struct { 1174 __u64 handle; 1175 } free; 1176 1177 /** 1178 * structure for mapping device memory (used with the HL_MEM_OP_MAP op) 1179 * @hint_addr: requested virtual address of mapped memory. 1180 * the driver will try to map the requested region to this hint 1181 * address, as long as the address is valid and not already mapped. 1182 * the user should check the returned address of the IOCTL to make 1183 * sure he got the hint address. 1184 * passing 0 here means that the driver will choose the address itself. 1185 * @handle: handle returned from HL_MEM_OP_ALLOC. 1186 */ 1187 struct { 1188 __u64 hint_addr; 1189 __u64 handle; 1190 } map_device; 1191 1192 /** 1193 * structure for mapping host memory (used with the HL_MEM_OP_MAP op) 1194 * @host_virt_addr: address of allocated host memory. 1195 * @hint_addr: requested virtual address of mapped memory. 1196 * the driver will try to map the requested region to this hint 1197 * address, as long as the address is valid and not already mapped. 1198 * the user should check the returned address of the IOCTL to make 1199 * sure he got the hint address. 1200 * passing 0 here means that the driver will choose the address itself. 1201 * @size: size of allocated host memory. 1202 */ 1203 struct { 1204 __u64 host_virt_addr; 1205 __u64 hint_addr; 1206 __u64 mem_size; 1207 } map_host; 1208 1209 /** 1210 * structure for mapping hw block (used with the HL_MEM_OP_MAP_BLOCK op) 1211 * @block_addr:HW block address to map, a handle and size will be returned 1212 * to the user and will be used to mmap the relevant block. 1213 * only addresses from configuration space are allowed. 1214 */ 1215 struct { 1216 __u64 block_addr; 1217 } map_block; 1218 1219 /** 1220 * structure for unmapping host memory (used with the HL_MEM_OP_UNMAP op) 1221 * @device_virt_addr: virtual address returned from HL_MEM_OP_MAP 1222 */ 1223 struct { 1224 __u64 device_virt_addr; 1225 } unmap; 1226 1227 /** 1228 * structure for exporting DMABUF object (used with 1229 * the HL_MEM_OP_EXPORT_DMABUF_FD op) 1230 * @handle: handle returned from HL_MEM_OP_ALLOC. 1231 * in Gaudi, where we don't have MMU for the device memory, the 1232 * driver expects a physical address (instead of a handle) in the 1233 * device memory space. 1234 * @mem_size: size of memory allocation. Relevant only for GAUDI 1235 */ 1236 struct { 1237 __u64 handle; 1238 __u64 mem_size; 1239 } export_dmabuf_fd; 1240 }; 1241 1242 __u32 op; 1243 __u32 flags; 1244 __u32 ctx_id; 1245 __u32 num_of_elements; 1246}; 1247 1248struct hl_mem_out { 1249 union { 1250 /* 1251 * Used for HL_MEM_OP_MAP as the virtual address that was 1252 * assigned in the device VA space. 1253 * A value of 0 means the requested operation failed. 1254 */ 1255 __u64 device_virt_addr; 1256 1257 /* 1258 * Used in HL_MEM_OP_ALLOC 1259 * This is the assigned handle for the allocated memory 1260 */ 1261 __u64 handle; 1262 1263 struct { 1264 /* 1265 * Used in HL_MEM_OP_MAP_BLOCK. 1266 * This is the assigned handle for the mapped block 1267 */ 1268 __u64 block_handle; 1269 1270 /* 1271 * Used in HL_MEM_OP_MAP_BLOCK 1272 * This is the size of the mapped block 1273 */ 1274 __u32 block_size; 1275 1276 __u32 pad; 1277 }; 1278 1279 /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the 1280 * DMA-BUF object that was created to describe a memory 1281 * allocation on the device's memory space. The FD should be 1282 * passed to the importer driver 1283 */ 1284 __s32 fd; 1285 }; 1286}; 1287 1288union hl_mem_args { 1289 struct hl_mem_in in; 1290 struct hl_mem_out out; 1291}; 1292 1293#define HL_DEBUG_MAX_AUX_VALUES 10 1294 1295struct hl_debug_params_etr { 1296 /* Address in memory to allocate buffer */ 1297 __u64 buffer_address; 1298 1299 /* Size of buffer to allocate */ 1300 __u64 buffer_size; 1301 1302 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1303 __u32 sink_mode; 1304 __u32 pad; 1305}; 1306 1307struct hl_debug_params_etf { 1308 /* Address in memory to allocate buffer */ 1309 __u64 buffer_address; 1310 1311 /* Size of buffer to allocate */ 1312 __u64 buffer_size; 1313 1314 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1315 __u32 sink_mode; 1316 __u32 pad; 1317}; 1318 1319struct hl_debug_params_stm { 1320 /* Two bit masks for HW event and Stimulus Port */ 1321 __u64 he_mask; 1322 __u64 sp_mask; 1323 1324 /* Trace source ID */ 1325 __u32 id; 1326 1327 /* Frequency for the timestamp register */ 1328 __u32 frequency; 1329}; 1330 1331struct hl_debug_params_bmon { 1332 /* Two address ranges that the user can request to filter */ 1333 __u64 start_addr0; 1334 __u64 addr_mask0; 1335 1336 __u64 start_addr1; 1337 __u64 addr_mask1; 1338 1339 /* Capture window configuration */ 1340 __u32 bw_win; 1341 __u32 win_capture; 1342 1343 /* Trace source ID */ 1344 __u32 id; 1345 __u32 pad; 1346}; 1347 1348struct hl_debug_params_spmu { 1349 /* Event types selection */ 1350 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 1351 1352 /* Number of event types selection */ 1353 __u32 event_types_num; 1354 __u32 pad; 1355}; 1356 1357/* Opcode for ETR component */ 1358#define HL_DEBUG_OP_ETR 0 1359/* Opcode for ETF component */ 1360#define HL_DEBUG_OP_ETF 1 1361/* Opcode for STM component */ 1362#define HL_DEBUG_OP_STM 2 1363/* Opcode for FUNNEL component */ 1364#define HL_DEBUG_OP_FUNNEL 3 1365/* Opcode for BMON component */ 1366#define HL_DEBUG_OP_BMON 4 1367/* Opcode for SPMU component */ 1368#define HL_DEBUG_OP_SPMU 5 1369/* Opcode for timestamp (deprecated) */ 1370#define HL_DEBUG_OP_TIMESTAMP 6 1371/* Opcode for setting the device into or out of debug mode. The enable 1372 * variable should be 1 for enabling debug mode and 0 for disabling it 1373 */ 1374#define HL_DEBUG_OP_SET_MODE 7 1375 1376struct hl_debug_args { 1377 /* 1378 * Pointer to user input structure. 1379 * This field is relevant to specific opcodes. 1380 */ 1381 __u64 input_ptr; 1382 /* Pointer to user output structure */ 1383 __u64 output_ptr; 1384 /* Size of user input structure */ 1385 __u32 input_size; 1386 /* Size of user output structure */ 1387 __u32 output_size; 1388 /* HL_DEBUG_OP_* */ 1389 __u32 op; 1390 /* 1391 * Register index in the component, taken from the debug_regs_index enum 1392 * in the various ASIC header files 1393 */ 1394 __u32 reg_idx; 1395 /* Enable/disable */ 1396 __u32 enable; 1397 /* Context ID - Currently not in use */ 1398 __u32 ctx_id; 1399}; 1400 1401/* 1402 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command 1403 * 1404 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event 1405 */ 1406#define HL_NOTIFIER_EVENT_TPC_ASSERT (1 << 0) 1407 1408/* 1409 * Various information operations such as: 1410 * - H/W IP information 1411 * - Current dram usage 1412 * 1413 * The user calls this IOCTL with an opcode that describes the required 1414 * information. The user should supply a pointer to a user-allocated memory 1415 * chunk, which will be filled by the driver with the requested information. 1416 * 1417 * The user supplies the maximum amount of size to copy into the user's memory, 1418 * in order to prevent data corruption in case of differences between the 1419 * definitions of structures in kernel and userspace, e.g. in case of old 1420 * userspace and new kernel driver 1421 */ 1422#define HL_IOCTL_INFO \ 1423 _IOWR('H', 0x01, struct hl_info_args) 1424 1425/* 1426 * Command Buffer 1427 * - Request a Command Buffer 1428 * - Destroy a Command Buffer 1429 * 1430 * The command buffers are memory blocks that reside in DMA-able address 1431 * space and are physically contiguous so they can be accessed by the device 1432 * directly. They are allocated using the coherent DMA API. 1433 * 1434 * When creating a new CB, the IOCTL returns a handle of it, and the user-space 1435 * process needs to use that handle to mmap the buffer so it can access them. 1436 * 1437 * In some instances, the device must access the command buffer through the 1438 * device's MMU, and thus its memory should be mapped. In these cases, user can 1439 * indicate the driver that such a mapping is required. 1440 * The resulting device virtual address will be used internally by the driver, 1441 * and won't be returned to user. 1442 * 1443 */ 1444#define HL_IOCTL_CB \ 1445 _IOWR('H', 0x02, union hl_cb_args) 1446 1447/* 1448 * Command Submission 1449 * 1450 * To submit work to the device, the user need to call this IOCTL with a set 1451 * of JOBS. That set of JOBS constitutes a CS object. 1452 * Each JOB will be enqueued on a specific queue, according to the user's input. 1453 * There can be more then one JOB per queue. 1454 * 1455 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase 1456 * and a second set is for "execution" phase. 1457 * The JOBS on the "restore" phase are enqueued only after context-switch 1458 * (or if its the first CS for this context). The user can also order the 1459 * driver to run the "restore" phase explicitly 1460 * 1461 * There are two types of queues - external and internal. External queues 1462 * are DMA queues which transfer data from/to the Host. All other queues are 1463 * internal. The driver will get completion notifications from the device only 1464 * on JOBS which are enqueued in the external queues. 1465 * 1466 * For jobs on external queues, the user needs to create command buffers 1467 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on 1468 * internal queues, the user needs to prepare a "command buffer" with packets 1469 * on either the device SRAM/DRAM or the host, and give the device address of 1470 * that buffer to the CS ioctl. 1471 * 1472 * This IOCTL is asynchronous in regard to the actual execution of the CS. This 1473 * means it returns immediately after ALL the JOBS were enqueued on their 1474 * relevant queues. Therefore, the user mustn't assume the CS has been completed 1475 * or has even started to execute. 1476 * 1477 * Upon successful enqueue, the IOCTL returns a sequence number which the user 1478 * can use with the "Wait for CS" IOCTL to check whether the handle's CS 1479 * external JOBS have been completed. Note that if the CS has internal JOBS 1480 * which can execute AFTER the external JOBS have finished, the driver might 1481 * report that the CS has finished executing BEFORE the internal JOBS have 1482 * actually finished executing. 1483 * 1484 * Even though the sequence number increments per CS, the user can NOT 1485 * automatically assume that if CS with sequence number N finished, then CS 1486 * with sequence number N-1 also finished. The user can make this assumption if 1487 * and only if CS N and CS N-1 are exactly the same (same CBs for the same 1488 * queues). 1489 */ 1490#define HL_IOCTL_CS \ 1491 _IOWR('H', 0x03, union hl_cs_args) 1492 1493/* 1494 * Wait for Command Submission 1495 * 1496 * The user can call this IOCTL with a handle it received from the CS IOCTL 1497 * to wait until the handle's CS has finished executing. The user will wait 1498 * inside the kernel until the CS has finished or until the user-requested 1499 * timeout has expired. 1500 * 1501 * If the timeout value is 0, the driver won't sleep at all. It will check 1502 * the status of the CS and return immediately 1503 * 1504 * The return value of the IOCTL is a standard Linux error code. The possible 1505 * values are: 1506 * 1507 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal 1508 * that the user process received 1509 * ETIMEDOUT - The CS has caused a timeout on the device 1510 * EIO - The CS was aborted (usually because the device was reset) 1511 * ENODEV - The device wants to do hard-reset (so user need to close FD) 1512 * 1513 * The driver also returns a custom define in case the IOCTL call returned 0. 1514 * The define can be one of the following: 1515 * 1516 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0) 1517 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0) 1518 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device 1519 * (ETIMEDOUT) 1520 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the 1521 * device was reset (EIO) 1522 */ 1523 1524#define HL_IOCTL_WAIT_CS \ 1525 _IOWR('H', 0x04, union hl_wait_cs_args) 1526 1527/* 1528 * Memory 1529 * - Map host memory to device MMU 1530 * - Unmap host memory from device MMU 1531 * 1532 * This IOCTL allows the user to map host memory to the device MMU 1533 * 1534 * For host memory, the IOCTL doesn't allocate memory. The user is supposed 1535 * to allocate the memory in user-space (malloc/new). The driver pins the 1536 * physical pages (up to the allowed limit by the OS), assigns a virtual 1537 * address in the device VA space and initializes the device MMU. 1538 * 1539 * There is an option for the user to specify the requested virtual address. 1540 * 1541 */ 1542#define HL_IOCTL_MEMORY \ 1543 _IOWR('H', 0x05, union hl_mem_args) 1544 1545/* 1546 * Debug 1547 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces 1548 * 1549 * This IOCTL allows the user to get debug traces from the chip. 1550 * 1551 * Before the user can send configuration requests of the various 1552 * debug/profile engines, it needs to set the device into debug mode. 1553 * This is because the debug/profile infrastructure is shared component in the 1554 * device and we can't allow multiple users to access it at the same time. 1555 * 1556 * Once a user set the device into debug mode, the driver won't allow other 1557 * users to "work" with the device, i.e. open a FD. If there are multiple users 1558 * opened on the device, the driver won't allow any user to debug the device. 1559 * 1560 * For each configuration request, the user needs to provide the register index 1561 * and essential data such as buffer address and size. 1562 * 1563 * Once the user has finished using the debug/profile engines, he should 1564 * set the device into non-debug mode, i.e. disable debug mode. 1565 * 1566 * The driver can decide to "kick out" the user if he abuses this interface. 1567 * 1568 */ 1569#define HL_IOCTL_DEBUG \ 1570 _IOWR('H', 0x06, struct hl_debug_args) 1571 1572#define HL_COMMAND_START 0x01 1573#define HL_COMMAND_END 0x07 1574 1575#endif /* HABANALABS_H_ */