cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cxgb4-abi.h (3122B)

      1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
      2/*
      3 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
      4 *
      5 * This software is available to you under a choice of one of two
      6 * licenses.  You may choose to be licensed under the terms of the GNU
      7 * General Public License (GPL) Version 2, available from the file
      8 * COPYING in the main directory of this source tree, or the
      9 * OpenIB.org BSD license below:
     10 *
     11 *     Redistribution and use in source and binary forms, with or
     12 *     without modification, are permitted provided that the following
     13 *     conditions are met:
     14 *
     15 *      - Redistributions of source code must retain the above
     16 *        copyright notice, this list of conditions and the following
     17 *        disclaimer.
     18 *
     19 *      - Redistributions in binary form must reproduce the above
     20 *        copyright notice, this list of conditions and the following
     21 *        disclaimer in the documentation and/or other materials
     22 *        provided with the distribution.
     23 *
     24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     31 * SOFTWARE.
     32 */
     33#ifndef CXGB4_ABI_USER_H
     34#define CXGB4_ABI_USER_H
     35
     36#include <linux/types.h>
     37
     38#define C4IW_UVERBS_ABI_VERSION	3
     39
     40/*
     41 * Make sure that all structs defined in this file remain laid out so
     42 * that they pack the same way on 32-bit and 64-bit architectures (to
     43 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
     44 * In particular do not use pointer types -- pass pointers in __aligned_u64
     45 * instead.
     46 */
     47
     48enum {
     49	C4IW_64B_CQE = (1 << 0)
     50};
     51
     52struct c4iw_create_cq {
     53	__u32 flags;
     54	__u32 reserved;
     55};
     56
     57struct c4iw_create_cq_resp {
     58	__aligned_u64 key;
     59	__aligned_u64 gts_key;
     60	__aligned_u64 memsize;
     61	__u32 cqid;
     62	__u32 size;
     63	__u32 qid_mask;
     64	__u32 flags;
     65};
     66
     67enum {
     68	C4IW_QPF_ONCHIP	= (1 << 0),
     69	C4IW_QPF_WRITE_W_IMM = (1 << 1)
     70};
     71
     72struct c4iw_create_qp_resp {
     73	__aligned_u64 ma_sync_key;
     74	__aligned_u64 sq_key;
     75	__aligned_u64 rq_key;
     76	__aligned_u64 sq_db_gts_key;
     77	__aligned_u64 rq_db_gts_key;
     78	__aligned_u64 sq_memsize;
     79	__aligned_u64 rq_memsize;
     80	__u32 sqid;
     81	__u32 rqid;
     82	__u32 sq_size;
     83	__u32 rq_size;
     84	__u32 qid_mask;
     85	__u32 flags;
     86};
     87
     88struct c4iw_create_srq_resp {
     89	__aligned_u64 srq_key;
     90	__aligned_u64 srq_db_gts_key;
     91	__aligned_u64 srq_memsize;
     92	__u32 srqid;
     93	__u32 srq_size;
     94	__u32 rqt_abs_idx;
     95	__u32 qid_mask;
     96	__u32 flags;
     97	__u32 reserved; /* explicit padding */
     98};
     99
    100enum {
    101	/* HW supports SRQ_LIMIT_REACHED event */
    102	T4_SRQ_LIMIT_SUPPORT = 1 << 0,
    103};
    104
    105struct c4iw_alloc_ucontext_resp {
    106	__aligned_u64 status_page_key;
    107	__u32 status_page_size;
    108	__u32 reserved; /* explicit padding (optional for i386) */
    109};
    110
    111struct c4iw_alloc_pd_resp {
    112	__u32 pdid;
    113};
    114
    115#endif /* CXGB4_ABI_USER_H */