cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mlx5_user_ioctl_verbs.h (3531B)


      1/*
      2 * Copyright (c) 2018, Mellanox Technologies inc.  All rights reserved.
      3 *
      4 * This software is available to you under a choice of one of two
      5 * licenses.  You may choose to be licensed under the terms of the GNU
      6 * General Public License (GPL) Version 2, available from the file
      7 * COPYING in the main directory of this source tree, or the
      8 * OpenIB.org BSD license below:
      9 *
     10 *     Redistribution and use in source and binary forms, with or
     11 *     without modification, are permitted provided that the following
     12 *     conditions are met:
     13 *
     14 *      - Redistributions of source code must retain the above
     15 *        copyright notice, this list of conditions and the following
     16 *        disclaimer.
     17 *
     18 *      - Redistributions in binary form must reproduce the above
     19 *        copyright notice, this list of conditions and the following
     20 *        disclaimer in the documentation and/or other materials
     21 *        provided with the distribution.
     22 *
     23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     30 * SOFTWARE.
     31 */
     32
     33#ifndef MLX5_USER_IOCTL_VERBS_H
     34#define MLX5_USER_IOCTL_VERBS_H
     35
     36#include <linux/types.h>
     37
     38enum mlx5_ib_uapi_flow_action_flags {
     39	MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA	= 1 << 0,
     40};
     41
     42enum mlx5_ib_uapi_flow_table_type {
     43	MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX     = 0x0,
     44	MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX	= 0x1,
     45	MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB	= 0x2,
     46	MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX	= 0x3,
     47	MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX	= 0x4,
     48};
     49
     50enum mlx5_ib_uapi_flow_action_packet_reformat_type {
     51	MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 = 0x0,
     52	MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x1,
     53	MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x2,
     54	MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x3,
     55};
     56
     57struct mlx5_ib_uapi_devx_async_cmd_hdr {
     58	__aligned_u64	wr_id;
     59	__u8		out_data[];
     60};
     61
     62enum mlx5_ib_uapi_dm_type {
     63	MLX5_IB_UAPI_DM_TYPE_MEMIC,
     64	MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM,
     65	MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM,
     66};
     67
     68enum mlx5_ib_uapi_devx_create_event_channel_flags {
     69	MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0,
     70};
     71
     72struct mlx5_ib_uapi_devx_async_event_hdr {
     73	__aligned_u64	cookie;
     74	__u8		out_data[];
     75};
     76
     77enum mlx5_ib_uapi_pp_alloc_flags {
     78	MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX = 1 << 0,
     79};
     80
     81enum mlx5_ib_uapi_uar_alloc_type {
     82	MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF = 0x0,
     83	MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC = 0x1,
     84};
     85
     86enum mlx5_ib_uapi_query_port_flags {
     87	MLX5_IB_UAPI_QUERY_PORT_VPORT			= 1 << 0,
     88	MLX5_IB_UAPI_QUERY_PORT_VPORT_VHCA_ID		= 1 << 1,
     89	MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_RX	= 1 << 2,
     90	MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_TX	= 1 << 3,
     91	MLX5_IB_UAPI_QUERY_PORT_VPORT_REG_C0		= 1 << 4,
     92	MLX5_IB_UAPI_QUERY_PORT_ESW_OWNER_VHCA_ID	= 1 << 5,
     93};
     94
     95struct mlx5_ib_uapi_reg {
     96	__u32 value;
     97	__u32 mask;
     98};
     99
    100struct mlx5_ib_uapi_query_port {
    101	__aligned_u64 flags;
    102	__u16 vport;
    103	__u16 vport_vhca_id;
    104	__u16 esw_owner_vhca_id;
    105	__u16 rsvd0;
    106	__aligned_u64 vport_steering_icm_rx;
    107	__aligned_u64 vport_steering_icm_tx;
    108	struct mlx5_ib_uapi_reg reg_c0;
    109};
    110
    111#endif
    112