emu10k1.h (17381B)
1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2/* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 * Creative Labs, Inc. 5 * Definitions for EMU10K1 (SB Live!) chips 6 * 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23#ifndef _UAPI__SOUND_EMU10K1_H 24#define _UAPI__SOUND_EMU10K1_H 25 26#ifdef __linux__ 27#include <linux/types.h> 28#endif 29 30/* 31 * ---- FX8010 ---- 32 */ 33 34#define EMU10K1_CARD_CREATIVE 0x00000000 35#define EMU10K1_CARD_EMUAPS 0x00000001 36 37#define EMU10K1_FX8010_PCM_COUNT 8 38 39/* 40 * Following definition is copied from linux/types.h to support compiling 41 * this header file in userspace since they are not generally available for 42 * uapi headers. 43 */ 44#define __EMU10K1_DECLARE_BITMAP(name,bits) \ 45 unsigned long name[(bits) / (sizeof(unsigned long) * 8)] 46 47/* instruction set */ 48#define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ 49#define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ 50#define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ 51#define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ 52#define iMACINT0 0x04 /* R = A + X * Y ; saturation */ 53#define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ 54#define iACC3 0x06 /* R = A + X + Y ; saturation */ 55#define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ 56#define iANDXOR 0x08 /* R = (A & X) ^ Y */ 57#define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ 58#define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ 59#define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ 60#define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ 61#define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ 62#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ 63#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ 64 65/* GPRs */ 66#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ 67#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ 68#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ 69#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ 70 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ 71 72#define C_00000000 0x40 73#define C_00000001 0x41 74#define C_00000002 0x42 75#define C_00000003 0x43 76#define C_00000004 0x44 77#define C_00000008 0x45 78#define C_00000010 0x46 79#define C_00000020 0x47 80#define C_00000100 0x48 81#define C_00010000 0x49 82#define C_00080000 0x4a 83#define C_10000000 0x4b 84#define C_20000000 0x4c 85#define C_40000000 0x4d 86#define C_80000000 0x4e 87#define C_7fffffff 0x4f 88#define C_ffffffff 0x50 89#define C_fffffffe 0x51 90#define C_c0000000 0x52 91#define C_4f1bbcdc 0x53 92#define C_5a7ef9db 0x54 93#define C_00100000 0x55 /* ?? */ 94#define GPR_ACCU 0x56 /* ACCUM, accumulator */ 95#define GPR_COND 0x57 /* CCR, condition register */ 96#define GPR_NOISE0 0x58 /* noise source */ 97#define GPR_NOISE1 0x59 /* noise source */ 98#define GPR_IRQ 0x5a /* IRQ register */ 99#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ 100#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ 101#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 102#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 103#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 104#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 105 106#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 107#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 108#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 109#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 110#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 111#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 112 113#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ 114#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ 115#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ 116#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ 117#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ 118#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ 119#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ 120#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */ 121#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */ 122#define A_GPR(x) (A_FXGPREGBASE + (x)) 123 124/* cc_reg constants */ 125#define CC_REG_NORMALIZED C_00000001 126#define CC_REG_BORROW C_00000002 127#define CC_REG_MINUS C_00000004 128#define CC_REG_ZERO C_00000008 129#define CC_REG_SATURATE C_00000010 130#define CC_REG_NONZERO C_00000100 131 132/* FX buses */ 133#define FXBUS_PCM_LEFT 0x00 134#define FXBUS_PCM_RIGHT 0x01 135#define FXBUS_PCM_LEFT_REAR 0x02 136#define FXBUS_PCM_RIGHT_REAR 0x03 137#define FXBUS_MIDI_LEFT 0x04 138#define FXBUS_MIDI_RIGHT 0x05 139#define FXBUS_PCM_CENTER 0x06 140#define FXBUS_PCM_LFE 0x07 141#define FXBUS_PCM_LEFT_FRONT 0x08 142#define FXBUS_PCM_RIGHT_FRONT 0x09 143#define FXBUS_MIDI_REVERB 0x0c 144#define FXBUS_MIDI_CHORUS 0x0d 145#define FXBUS_PCM_LEFT_SIDE 0x0e 146#define FXBUS_PCM_RIGHT_SIDE 0x0f 147#define FXBUS_PT_LEFT 0x14 148#define FXBUS_PT_RIGHT 0x15 149 150/* Inputs */ 151#define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 152#define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 153#define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ 154#define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ 155#define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ 156#define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ 157#define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ 158#define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ 159#define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ 160#define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ 161#define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ 162#define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ 163#define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ 164#define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ 165 166/* Outputs */ 167#define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ 168#define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ 169#define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ 170#define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ 171#define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ 172#define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ 173#define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ 174#define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ 175#define EXTOUT_REAR_L 0x08 /* Rear channel - left */ 176#define EXTOUT_REAR_R 0x09 /* Rear channel - right */ 177#define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ 178#define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ 179#define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ 180#define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ 181#define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ 182#define EXTOUT_ACENTER 0x11 /* Analog Center */ 183#define EXTOUT_ALFE 0x12 /* Analog LFE */ 184 185/* Audigy Inputs */ 186#define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 187#define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 188#define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ 189#define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ 190#define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ 191#define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 192#define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ 193#define A_EXTIN_LINE2_R 0x09 /* right */ 194#define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ 195#define A_EXTIN_ADC_R 0x0b /* right */ 196#define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ 197#define A_EXTIN_AUX2_R 0x0d /* - right */ 198 199/* Audigiy Outputs */ 200#define A_EXTOUT_FRONT_L 0x00 /* digital front left */ 201#define A_EXTOUT_FRONT_R 0x01 /* right */ 202#define A_EXTOUT_CENTER 0x02 /* digital front center */ 203#define A_EXTOUT_LFE 0x03 /* digital front lfe */ 204#define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ 205#define A_EXTOUT_HEADPHONE_R 0x05 /* right */ 206#define A_EXTOUT_REAR_L 0x06 /* digital rear left */ 207#define A_EXTOUT_REAR_R 0x07 /* right */ 208#define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ 209#define A_EXTOUT_AFRONT_R 0x09 /* right */ 210#define A_EXTOUT_ACENTER 0x0a /* analog center */ 211#define A_EXTOUT_ALFE 0x0b /* analog LFE */ 212#define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ 213#define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ 214#define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ 215#define A_EXTOUT_AREAR_R 0x0f /* right */ 216#define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ 217#define A_EXTOUT_AC97_R 0x11 /* right */ 218#define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ 219#define A_EXTOUT_ADC_CAP_R 0x17 /* right */ 220#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ 221 222/* Audigy constants */ 223#define A_C_00000000 0xc0 224#define A_C_00000001 0xc1 225#define A_C_00000002 0xc2 226#define A_C_00000003 0xc3 227#define A_C_00000004 0xc4 228#define A_C_00000008 0xc5 229#define A_C_00000010 0xc6 230#define A_C_00000020 0xc7 231#define A_C_00000100 0xc8 232#define A_C_00010000 0xc9 233#define A_C_00000800 0xca 234#define A_C_10000000 0xcb 235#define A_C_20000000 0xcc 236#define A_C_40000000 0xcd 237#define A_C_80000000 0xce 238#define A_C_7fffffff 0xcf 239#define A_C_ffffffff 0xd0 240#define A_C_fffffffe 0xd1 241#define A_C_c0000000 0xd2 242#define A_C_4f1bbcdc 0xd3 243#define A_C_5a7ef9db 0xd4 244#define A_C_00100000 0xd5 245#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ 246#define A_GPR_COND 0xd7 /* CCR, condition register */ 247#define A_GPR_NOISE0 0xd8 /* noise source */ 248#define A_GPR_NOISE1 0xd9 /* noise source */ 249#define A_GPR_IRQ 0xda /* IRQ register */ 250#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ 251#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ 252 253/* definitions for debug register */ 254#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ 255#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ 256#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ 257#define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ 258#define EMU10K1_DBG_STEP 0x00004000 /* start single step */ 259#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ 260#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ 261 262/* tank memory address line */ 263#ifndef __KERNEL__ 264#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 265#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 266#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 267#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 268#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 269#endif 270 271struct snd_emu10k1_fx8010_info { 272 unsigned int internal_tram_size; /* in samples */ 273 unsigned int external_tram_size; /* in samples */ 274 char fxbus_names[16][32]; /* names of FXBUSes */ 275 char extin_names[16][32]; /* names of external inputs */ 276 char extout_names[32][32]; /* names of external outputs */ 277 unsigned int gpr_controls; /* count of GPR controls */ 278}; 279 280#define EMU10K1_GPR_TRANSLATION_NONE 0 281#define EMU10K1_GPR_TRANSLATION_TABLE100 1 282#define EMU10K1_GPR_TRANSLATION_BASS 2 283#define EMU10K1_GPR_TRANSLATION_TREBLE 3 284#define EMU10K1_GPR_TRANSLATION_ONOFF 4 285 286enum emu10k1_ctl_elem_iface { 287 EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */ 288 EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */ 289}; 290 291struct emu10k1_ctl_elem_id { 292 unsigned int pad; /* don't use */ 293 int iface; /* interface identifier */ 294 unsigned int device; /* device/client number */ 295 unsigned int subdevice; /* subdevice (substream) number */ 296 unsigned char name[44]; /* ASCII name of item */ 297 unsigned int index; /* index of item */ 298}; 299 300struct snd_emu10k1_fx8010_control_gpr { 301 struct emu10k1_ctl_elem_id id; /* full control ID definition */ 302 unsigned int vcount; /* visible count */ 303 unsigned int count; /* count of GPR (1..16) */ 304 unsigned short gpr[32]; /* GPR number(s) */ 305 unsigned int value[32]; /* initial values */ 306 unsigned int min; /* minimum range */ 307 unsigned int max; /* maximum range */ 308 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 309 const unsigned int *tlv; 310}; 311 312/* old ABI without TLV support */ 313struct snd_emu10k1_fx8010_control_old_gpr { 314 struct emu10k1_ctl_elem_id id; 315 unsigned int vcount; 316 unsigned int count; 317 unsigned short gpr[32]; 318 unsigned int value[32]; 319 unsigned int min; 320 unsigned int max; 321 unsigned int translation; 322}; 323 324struct snd_emu10k1_fx8010_code { 325 char name[128]; 326 327 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ 328 __u32 *gpr_map; /* initializers */ 329 330 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ 331 struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */ 332 333 unsigned int gpr_del_control_count; /* count of GPR controls to remove */ 334 struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */ 335 336 unsigned int gpr_list_control_count; /* count of GPR controls to list */ 337 unsigned int gpr_list_control_total; /* total count of GPR controls */ 338 struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */ 339 340 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ 341 __u32 *tram_data_map; /* data initializers */ 342 __u32 *tram_addr_map; /* map initializers */ 343 344 __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ 345 __u32 *code; /* one instruction - 64 bits */ 346}; 347 348struct snd_emu10k1_fx8010_tram { 349 unsigned int address; /* 31.bit == 1 -> external TRAM */ 350 unsigned int size; /* size in samples (4 bytes) */ 351 unsigned int *samples; /* pointer to samples (20-bit) */ 352 /* NULL->clear memory */ 353}; 354 355struct snd_emu10k1_fx8010_pcm_rec { 356 unsigned int substream; /* substream number */ 357 unsigned int res1; /* reserved */ 358 unsigned int channels; /* 16-bit channels count, zero = remove this substream */ 359 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ 360 unsigned int buffer_size; /* count of buffered samples */ 361 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ 362 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 363 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 364 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 365 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 366 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 367 unsigned char pad; /* reserved */ 368 unsigned char etram[32]; /* external TRAM address & data (one per channel) */ 369 unsigned int res2; /* reserved */ 370}; 371 372#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) 373 374#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) 375#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) 376#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 377#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 378#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) 379#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 380#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 381#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 382#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) 383#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 384#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) 385#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) 386#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) 387#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 388 389#endif /* _UAPI__SOUND_EMU10K1_H */