ufshci.h (14149B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11#ifndef _UFSHCI_H 12#define _UFSHCI_H 13 14#include <scsi/scsi_host.h> 15 16enum { 17 TASK_REQ_UPIU_SIZE_DWORDS = 8, 18 TASK_RSP_UPIU_SIZE_DWORDS = 8, 19 ALIGNED_UPIU_SIZE = 512, 20}; 21 22/* UFSHCI Registers */ 23enum { 24 REG_CONTROLLER_CAPABILITIES = 0x00, 25 REG_UFS_VERSION = 0x08, 26 REG_CONTROLLER_DEV_ID = 0x10, 27 REG_CONTROLLER_PROD_ID = 0x14, 28 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 29 REG_INTERRUPT_STATUS = 0x20, 30 REG_INTERRUPT_ENABLE = 0x24, 31 REG_CONTROLLER_STATUS = 0x30, 32 REG_CONTROLLER_ENABLE = 0x34, 33 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 34 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 35 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 36 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 37 REG_UIC_ERROR_CODE_DME = 0x48, 38 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 39 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 40 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 41 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 42 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 43 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 44 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 45 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 46 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 47 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 48 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 49 REG_UIC_COMMAND = 0x90, 50 REG_UIC_COMMAND_ARG_1 = 0x94, 51 REG_UIC_COMMAND_ARG_2 = 0x98, 52 REG_UIC_COMMAND_ARG_3 = 0x9C, 53 54 UFSHCI_REG_SPACE_SIZE = 0xA0, 55 56 REG_UFS_CCAP = 0x100, 57 REG_UFS_CRYPTOCAP = 0x104, 58 59 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 60}; 61 62/* Controller capability masks */ 63enum { 64 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, 65 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 66 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 67 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 68 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 69 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 70 MASK_CRYPTO_SUPPORT = 0x10000000, 71}; 72 73#define UFS_MASK(mask, offset) ((mask) << (offset)) 74 75/* UFS Version 08h */ 76#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 77#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 78 79/* 80 * Controller UFSHCI version 81 * - 2.x and newer use the following scheme: 82 * major << 8 + minor << 4 83 * - 1.x has been converted to match this in 84 * ufshcd_get_ufs_version() 85 */ 86static inline u32 ufshci_version(u32 major, u32 minor) 87{ 88 return (major << 8) + (minor << 4); 89} 90 91/* 92 * HCDDID - Host Controller Identification Descriptor 93 * - Device ID and Device Class 10h 94 */ 95#define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 96#define DEVICE_ID UFS_MASK(0xFF, 24) 97 98/* 99 * HCPMID - Host Controller Identification Descriptor 100 * - Product/Manufacturer ID 14h 101 */ 102#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 103#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 104 105/* AHIT - Auto-Hibernate Idle Timer */ 106#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 107#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 108#define UFSHCI_AHIBERN8_SCALE_FACTOR 10 109#define UFSHCI_AHIBERN8_MAX (1023 * 100000) 110 111/* 112 * IS - Interrupt Status - 20h 113 */ 114#define UTP_TRANSFER_REQ_COMPL 0x1 115#define UIC_DME_END_PT_RESET 0x2 116#define UIC_ERROR 0x4 117#define UIC_TEST_MODE 0x8 118#define UIC_POWER_MODE 0x10 119#define UIC_HIBERNATE_EXIT 0x20 120#define UIC_HIBERNATE_ENTER 0x40 121#define UIC_LINK_LOST 0x80 122#define UIC_LINK_STARTUP 0x100 123#define UTP_TASK_REQ_COMPL 0x200 124#define UIC_COMMAND_COMPL 0x400 125#define DEVICE_FATAL_ERROR 0x800 126#define CONTROLLER_FATAL_ERROR 0x10000 127#define SYSTEM_BUS_FATAL_ERROR 0x20000 128#define CRYPTO_ENGINE_FATAL_ERROR 0x40000 129 130#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 131 UIC_HIBERNATE_EXIT) 132 133#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 134 UIC_POWER_MODE) 135 136#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 137 138#define UFSHCD_ERROR_MASK (UIC_ERROR |\ 139 DEVICE_FATAL_ERROR |\ 140 CONTROLLER_FATAL_ERROR |\ 141 SYSTEM_BUS_FATAL_ERROR |\ 142 CRYPTO_ENGINE_FATAL_ERROR) 143 144#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 145 CONTROLLER_FATAL_ERROR |\ 146 SYSTEM_BUS_FATAL_ERROR |\ 147 CRYPTO_ENGINE_FATAL_ERROR |\ 148 UIC_LINK_LOST) 149 150/* HCS - Host Controller Status 30h */ 151#define DEVICE_PRESENT 0x1 152#define UTP_TRANSFER_REQ_LIST_READY 0x2 153#define UTP_TASK_REQ_LIST_READY 0x4 154#define UIC_COMMAND_READY 0x8 155#define HOST_ERROR_INDICATOR 0x10 156#define DEVICE_ERROR_INDICATOR 0x20 157#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 158 159#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 160 UTP_TASK_REQ_LIST_READY |\ 161 UIC_COMMAND_READY) 162 163enum { 164 PWR_OK = 0x0, 165 PWR_LOCAL = 0x01, 166 PWR_REMOTE = 0x02, 167 PWR_BUSY = 0x03, 168 PWR_ERROR_CAP = 0x04, 169 PWR_FATAL_ERROR = 0x05, 170}; 171 172/* HCE - Host Controller Enable 34h */ 173#define CONTROLLER_ENABLE 0x1 174#define CONTROLLER_DISABLE 0x0 175#define CRYPTO_GENERAL_ENABLE 0x2 176 177/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 178#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 179#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 180#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 181#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 182 183/* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 184#define UIC_DATA_LINK_LAYER_ERROR 0x80000000 185#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF 186#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 187#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 188#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 189#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 190#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 191#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 192#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 193 194/* UECN - Host UIC Error Code Network Layer 40h */ 195#define UIC_NETWORK_LAYER_ERROR 0x80000000 196#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 197#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 198#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 199#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 200 201/* UECT - Host UIC Error Code Transport Layer 44h */ 202#define UIC_TRANSPORT_LAYER_ERROR 0x80000000 203#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 204#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 205#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 206#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 207#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 208#define UIC_TRANSPORT_BAD_TC 0x10 209#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 210#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 211 212/* UECDME - Host UIC Error Code DME 48h */ 213#define UIC_DME_ERROR 0x80000000 214#define UIC_DME_ERROR_CODE_MASK 0x1 215 216/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 217#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 218#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 219#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 220#define INT_AGGR_STATUS_BIT 0x100000 221#define INT_AGGR_PARAM_WRITE 0x1000000 222#define INT_AGGR_ENABLE 0x80000000 223 224/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 225#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 226 227/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 228#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 229 230/* UICCMD - UIC Command */ 231#define COMMAND_OPCODE_MASK 0xFF 232#define GEN_SELECTOR_INDEX_MASK 0xFFFF 233 234#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 235#define RESET_LEVEL 0xFF 236 237#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 238#define CONFIG_RESULT_CODE_MASK 0xFF 239#define GENERIC_ERROR_CODE_MASK 0xFF 240 241/* GenSelectorIndex calculation macros for M-PHY attributes */ 242#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 243#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 244 245#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 246 ((sel) & 0xFFFF)) 247#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 248#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 249#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 250 251/* Link Status*/ 252enum link_status { 253 UFSHCD_LINK_IS_DOWN = 1, 254 UFSHCD_LINK_IS_UP = 2, 255}; 256 257/* UIC Commands */ 258enum uic_cmd_dme { 259 UIC_CMD_DME_GET = 0x01, 260 UIC_CMD_DME_SET = 0x02, 261 UIC_CMD_DME_PEER_GET = 0x03, 262 UIC_CMD_DME_PEER_SET = 0x04, 263 UIC_CMD_DME_POWERON = 0x10, 264 UIC_CMD_DME_POWEROFF = 0x11, 265 UIC_CMD_DME_ENABLE = 0x12, 266 UIC_CMD_DME_RESET = 0x14, 267 UIC_CMD_DME_END_PT_RST = 0x15, 268 UIC_CMD_DME_LINK_STARTUP = 0x16, 269 UIC_CMD_DME_HIBER_ENTER = 0x17, 270 UIC_CMD_DME_HIBER_EXIT = 0x18, 271 UIC_CMD_DME_TEST_MODE = 0x1A, 272}; 273 274/* UIC Config result code / Generic error code */ 275enum { 276 UIC_CMD_RESULT_SUCCESS = 0x00, 277 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 278 UIC_CMD_RESULT_FAILURE = 0x01, 279 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 280 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 281 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 282 UIC_CMD_RESULT_BAD_INDEX = 0x05, 283 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 284 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 285 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 286 UIC_CMD_RESULT_BUSY = 0x09, 287 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 288}; 289 290#define MASK_UIC_COMMAND_RESULT 0xFF 291 292#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 293#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 294 295/* Interrupt disable masks */ 296enum { 297 /* Interrupt disable mask for UFSHCI v1.0 */ 298 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, 299 INTERRUPT_MASK_RW_VER_10 = 0x30000, 300 301 /* Interrupt disable mask for UFSHCI v1.1 */ 302 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 303 304 /* Interrupt disable mask for UFSHCI v2.1 */ 305 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 306}; 307 308/* CCAP - Crypto Capability 100h */ 309union ufs_crypto_capabilities { 310 __le32 reg_val; 311 struct { 312 u8 num_crypto_cap; 313 u8 config_count; 314 u8 reserved; 315 u8 config_array_ptr; 316 }; 317}; 318 319enum ufs_crypto_key_size { 320 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 321 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 322 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 323 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 324 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 325}; 326 327enum ufs_crypto_alg { 328 UFS_CRYPTO_ALG_AES_XTS = 0x0, 329 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 330 UFS_CRYPTO_ALG_AES_ECB = 0x2, 331 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 332}; 333 334/* x-CRYPTOCAP - Crypto Capability X */ 335union ufs_crypto_cap_entry { 336 __le32 reg_val; 337 struct { 338 u8 algorithm_id; 339 u8 sdus_mask; /* Supported data unit size mask */ 340 u8 key_size; 341 u8 reserved; 342 }; 343}; 344 345#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 346#define UFS_CRYPTO_KEY_MAX_SIZE 64 347/* x-CRYPTOCFG - Crypto Configuration X */ 348union ufs_crypto_cfg_entry { 349 __le32 reg_val[32]; 350 struct { 351 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 352 u8 data_unit_size; 353 u8 crypto_cap_idx; 354 u8 reserved_1; 355 u8 config_enable; 356 u8 reserved_multi_host; 357 u8 reserved_2; 358 u8 vsb[2]; 359 u8 reserved_3[56]; 360 }; 361}; 362 363/* 364 * Request Descriptor Definitions 365 */ 366 367/* Transfer request command type */ 368enum { 369 UTP_CMD_TYPE_SCSI = 0x0, 370 UTP_CMD_TYPE_UFS = 0x1, 371 UTP_CMD_TYPE_DEV_MANAGE = 0x2, 372}; 373 374/* To accommodate UFS2.0 required Command type */ 375enum { 376 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 377}; 378 379enum { 380 UTP_SCSI_COMMAND = 0x00000000, 381 UTP_NATIVE_UFS_COMMAND = 0x10000000, 382 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 383 UTP_REQ_DESC_INT_CMD = 0x01000000, 384 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000, 385}; 386 387/* UTP Transfer Request Data Direction (DD) */ 388enum { 389 UTP_NO_DATA_TRANSFER = 0x00000000, 390 UTP_HOST_TO_DEVICE = 0x02000000, 391 UTP_DEVICE_TO_HOST = 0x04000000, 392}; 393 394/* Overall command status values */ 395enum utp_ocs { 396 OCS_SUCCESS = 0x0, 397 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 398 OCS_INVALID_PRDT_ATTR = 0x2, 399 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 400 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 401 OCS_PEER_COMM_FAILURE = 0x5, 402 OCS_ABORTED = 0x6, 403 OCS_FATAL_ERROR = 0x7, 404 OCS_DEVICE_FATAL_ERROR = 0x8, 405 OCS_INVALID_CRYPTO_CONFIG = 0x9, 406 OCS_GENERAL_CRYPTO_ERROR = 0xA, 407 OCS_INVALID_COMMAND_STATUS = 0x0F, 408}; 409 410enum { 411 MASK_OCS = 0x0F, 412}; 413 414/* The maximum length of the data byte count field in the PRDT is 256KB */ 415#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) 416/* The granularity of the data byte count field in the PRDT is 32-bit */ 417#define PRDT_DATA_BYTE_COUNT_PAD 4 418 419/** 420 * struct ufshcd_sg_entry - UFSHCI PRD Entry 421 * @addr: Physical address; DW-0 and DW-1. 422 * @reserved: Reserved for future use DW-2 423 * @size: size of physical segment DW-3 424 */ 425struct ufshcd_sg_entry { 426 __le64 addr; 427 __le32 reserved; 428 __le32 size; 429}; 430 431/** 432 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) 433 * @command_upiu: Command UPIU Frame address 434 * @response_upiu: Response UPIU Frame address 435 * @prd_table: Physical Region Descriptor 436 */ 437struct utp_transfer_cmd_desc { 438 u8 command_upiu[ALIGNED_UPIU_SIZE]; 439 u8 response_upiu[ALIGNED_UPIU_SIZE]; 440 struct ufshcd_sg_entry prd_table[SG_ALL]; 441}; 442 443/** 444 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 445 * @dword0: Descriptor Header DW0 446 * @dword1: Descriptor Header DW1 447 * @dword2: Descriptor Header DW2 448 * @dword3: Descriptor Header DW3 449 */ 450struct request_desc_header { 451 __le32 dword_0; 452 __le32 dword_1; 453 __le32 dword_2; 454 __le32 dword_3; 455}; 456 457/** 458 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) 459 * @header: UTRD header DW-0 to DW-3 460 * @command_desc_base_addr_lo: UCD base address low DW-4 461 * @command_desc_base_addr_hi: UCD base address high DW-5 462 * @response_upiu_length: response UPIU length DW-6 463 * @response_upiu_offset: response UPIU offset DW-6 464 * @prd_table_length: Physical region descriptor length DW-7 465 * @prd_table_offset: Physical region descriptor offset DW-7 466 */ 467struct utp_transfer_req_desc { 468 469 /* DW 0-3 */ 470 struct request_desc_header header; 471 472 /* DW 4-5*/ 473 __le32 command_desc_base_addr_lo; 474 __le32 command_desc_base_addr_hi; 475 476 /* DW 6 */ 477 __le16 response_upiu_length; 478 __le16 response_upiu_offset; 479 480 /* DW 7 */ 481 __le16 prd_table_length; 482 __le16 prd_table_offset; 483}; 484 485/* 486 * UTMRD structure. 487 */ 488struct utp_task_req_desc { 489 /* DW 0-3 */ 490 struct request_desc_header header; 491 492 /* DW 4-11 - Task request UPIU structure */ 493 struct { 494 struct utp_upiu_header req_header; 495 __be32 input_param1; 496 __be32 input_param2; 497 __be32 input_param3; 498 __be32 __reserved1[2]; 499 } upiu_req; 500 501 /* DW 12-19 - Task Management Response UPIU structure */ 502 struct { 503 struct utp_upiu_header rsp_header; 504 __be32 output_param1; 505 __be32 output_param2; 506 __be32 __reserved2[3]; 507 } upiu_rsp; 508}; 509 510#endif /* End of Header */