cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mipi_display.h (5074B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Defines for Mobile Industry Processor Interface (MIPI(R))
      4 * Display Working Group standards: DSI, DCS, DBI, DPI
      5 *
      6 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
      7 * Copyright (C) 2006 Nokia Corporation
      8 * Author: Imre Deak <imre.deak@nokia.com>
      9 */
     10#ifndef MIPI_DISPLAY_H
     11#define MIPI_DISPLAY_H
     12
     13/* MIPI DSI Processor-to-Peripheral transaction types */
     14enum {
     15	MIPI_DSI_V_SYNC_START				= 0x01,
     16	MIPI_DSI_V_SYNC_END				= 0x11,
     17	MIPI_DSI_H_SYNC_START				= 0x21,
     18	MIPI_DSI_H_SYNC_END				= 0x31,
     19
     20	MIPI_DSI_COMPRESSION_MODE			= 0x07,
     21	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
     22
     23	MIPI_DSI_COLOR_MODE_OFF				= 0x02,
     24	MIPI_DSI_COLOR_MODE_ON				= 0x12,
     25	MIPI_DSI_SHUTDOWN_PERIPHERAL			= 0x22,
     26	MIPI_DSI_TURN_ON_PERIPHERAL			= 0x32,
     27
     28	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM		= 0x03,
     29	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM		= 0x13,
     30	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM		= 0x23,
     31
     32	MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM		= 0x04,
     33	MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM		= 0x14,
     34	MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM		= 0x24,
     35
     36	MIPI_DSI_DCS_SHORT_WRITE			= 0x05,
     37	MIPI_DSI_DCS_SHORT_WRITE_PARAM			= 0x15,
     38
     39	MIPI_DSI_DCS_READ				= 0x06,
     40	MIPI_DSI_EXECUTE_QUEUE				= 0x16,
     41
     42	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
     43
     44	MIPI_DSI_NULL_PACKET				= 0x09,
     45	MIPI_DSI_BLANKING_PACKET			= 0x19,
     46	MIPI_DSI_GENERIC_LONG_WRITE			= 0x29,
     47	MIPI_DSI_DCS_LONG_WRITE				= 0x39,
     48
     49	MIPI_DSI_PICTURE_PARAMETER_SET			= 0x0a,
     50	MIPI_DSI_COMPRESSED_PIXEL_STREAM		= 0x0b,
     51
     52	MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20	= 0x0c,
     53	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24		= 0x1c,
     54	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16		= 0x2c,
     55
     56	MIPI_DSI_PACKED_PIXEL_STREAM_30			= 0x0d,
     57	MIPI_DSI_PACKED_PIXEL_STREAM_36			= 0x1d,
     58	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12		= 0x3d,
     59
     60	MIPI_DSI_PACKED_PIXEL_STREAM_16			= 0x0e,
     61	MIPI_DSI_PACKED_PIXEL_STREAM_18			= 0x1e,
     62	MIPI_DSI_PIXEL_STREAM_3BYTE_18			= 0x2e,
     63	MIPI_DSI_PACKED_PIXEL_STREAM_24			= 0x3e,
     64};
     65
     66/* MIPI DSI Peripheral-to-Processor transaction types */
     67enum {
     68	MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT	= 0x02,
     69	MIPI_DSI_RX_END_OF_TRANSMISSION			= 0x08,
     70	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE	= 0x11,
     71	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE	= 0x12,
     72	MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE		= 0x1a,
     73	MIPI_DSI_RX_DCS_LONG_READ_RESPONSE		= 0x1c,
     74	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE	= 0x21,
     75	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE	= 0x22,
     76};
     77
     78/* MIPI DCS commands */
     79enum {
     80	MIPI_DCS_NOP			= 0x00,
     81	MIPI_DCS_SOFT_RESET		= 0x01,
     82	MIPI_DCS_GET_COMPRESSION_MODE	= 0x03,
     83	MIPI_DCS_GET_DISPLAY_ID		= 0x04,
     84	MIPI_DCS_GET_ERROR_COUNT_ON_DSI	= 0x05,
     85	MIPI_DCS_GET_RED_CHANNEL	= 0x06,
     86	MIPI_DCS_GET_GREEN_CHANNEL	= 0x07,
     87	MIPI_DCS_GET_BLUE_CHANNEL	= 0x08,
     88	MIPI_DCS_GET_DISPLAY_STATUS	= 0x09,
     89	MIPI_DCS_GET_POWER_MODE		= 0x0A,
     90	MIPI_DCS_GET_ADDRESS_MODE	= 0x0B,
     91	MIPI_DCS_GET_PIXEL_FORMAT	= 0x0C,
     92	MIPI_DCS_GET_DISPLAY_MODE	= 0x0D,
     93	MIPI_DCS_GET_SIGNAL_MODE	= 0x0E,
     94	MIPI_DCS_GET_DIAGNOSTIC_RESULT	= 0x0F,
     95	MIPI_DCS_ENTER_SLEEP_MODE	= 0x10,
     96	MIPI_DCS_EXIT_SLEEP_MODE	= 0x11,
     97	MIPI_DCS_ENTER_PARTIAL_MODE	= 0x12,
     98	MIPI_DCS_ENTER_NORMAL_MODE	= 0x13,
     99	MIPI_DCS_GET_IMAGE_CHECKSUM_RGB	= 0x14,
    100	MIPI_DCS_GET_IMAGE_CHECKSUM_CT	= 0x15,
    101	MIPI_DCS_EXIT_INVERT_MODE	= 0x20,
    102	MIPI_DCS_ENTER_INVERT_MODE	= 0x21,
    103	MIPI_DCS_SET_GAMMA_CURVE	= 0x26,
    104	MIPI_DCS_SET_DISPLAY_OFF	= 0x28,
    105	MIPI_DCS_SET_DISPLAY_ON		= 0x29,
    106	MIPI_DCS_SET_COLUMN_ADDRESS	= 0x2A,
    107	MIPI_DCS_SET_PAGE_ADDRESS	= 0x2B,
    108	MIPI_DCS_WRITE_MEMORY_START	= 0x2C,
    109	MIPI_DCS_WRITE_LUT		= 0x2D,
    110	MIPI_DCS_READ_MEMORY_START	= 0x2E,
    111	MIPI_DCS_SET_PARTIAL_ROWS	= 0x30,		/* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
    112	MIPI_DCS_SET_PARTIAL_COLUMNS	= 0x31,
    113	MIPI_DCS_SET_SCROLL_AREA	= 0x33,
    114	MIPI_DCS_SET_TEAR_OFF		= 0x34,
    115	MIPI_DCS_SET_TEAR_ON		= 0x35,
    116	MIPI_DCS_SET_ADDRESS_MODE	= 0x36,
    117	MIPI_DCS_SET_SCROLL_START	= 0x37,
    118	MIPI_DCS_EXIT_IDLE_MODE		= 0x38,
    119	MIPI_DCS_ENTER_IDLE_MODE	= 0x39,
    120	MIPI_DCS_SET_PIXEL_FORMAT	= 0x3A,
    121	MIPI_DCS_WRITE_MEMORY_CONTINUE	= 0x3C,
    122	MIPI_DCS_SET_3D_CONTROL		= 0x3D,
    123	MIPI_DCS_READ_MEMORY_CONTINUE	= 0x3E,
    124	MIPI_DCS_GET_3D_CONTROL		= 0x3F,
    125	MIPI_DCS_SET_VSYNC_TIMING	= 0x40,
    126	MIPI_DCS_SET_TEAR_SCANLINE	= 0x44,
    127	MIPI_DCS_GET_SCANLINE		= 0x45,
    128	MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51,		/* MIPI DCS 1.3 */
    129	MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52,		/* MIPI DCS 1.3 */
    130	MIPI_DCS_WRITE_CONTROL_DISPLAY  = 0x53,		/* MIPI DCS 1.3 */
    131	MIPI_DCS_GET_CONTROL_DISPLAY	= 0x54,		/* MIPI DCS 1.3 */
    132	MIPI_DCS_WRITE_POWER_SAVE	= 0x55,		/* MIPI DCS 1.3 */
    133	MIPI_DCS_GET_POWER_SAVE		= 0x56,		/* MIPI DCS 1.3 */
    134	MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,	/* MIPI DCS 1.3 */
    135	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,	/* MIPI DCS 1.3 */
    136	MIPI_DCS_READ_DDB_START		= 0xA1,
    137	MIPI_DCS_READ_PPS_START		= 0xA2,
    138	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
    139	MIPI_DCS_READ_PPS_CONTINUE	= 0xA9,
    140};
    141
    142/* MIPI DCS pixel formats */
    143#define MIPI_DCS_PIXEL_FMT_24BIT	7
    144#define MIPI_DCS_PIXEL_FMT_18BIT	6
    145#define MIPI_DCS_PIXEL_FMT_16BIT	5
    146#define MIPI_DCS_PIXEL_FMT_12BIT	3
    147#define MIPI_DCS_PIXEL_FMT_8BIT		2
    148#define MIPI_DCS_PIXEL_FMT_3BIT		1
    149
    150#endif