cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

altivec.uc (3425B)

      1/* -*- linux-c -*- ------------------------------------------------------- *
      2 *
      3 *   Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
      4 *
      5 *   This program is free software; you can redistribute it and/or modify
      6 *   it under the terms of the GNU General Public License as published by
      7 *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
      8 *   Boston MA 02111-1307, USA; either version 2 of the License, or
      9 *   (at your option) any later version; incorporated herein by reference.
     10 *
     11 * ----------------------------------------------------------------------- */
     12
     13/*
     14 * raid6altivec$#.c
     15 *
     16 * $#-way unrolled portable integer math RAID-6 instruction set
     17 *
     18 * This file is postprocessed using unroll.awk
     19 *
     20 * <benh> hpa: in process,
     21 * you can just "steal" the vec unit with enable_kernel_altivec() (but
     22 * bracked this with preempt_disable/enable or in a lock)
     23 */
     24
     25#include <linux/raid/pq.h>
     26
     27#ifdef CONFIG_ALTIVEC
     28
     29#include <altivec.h>
     30#ifdef __KERNEL__
     31# include <asm/cputable.h>
     32# include <asm/switch_to.h>
     33#endif /* __KERNEL__ */
     34
     35/*
     36 * This is the C data type to use.  We use a vector of
     37 * signed char so vec_cmpgt() will generate the right
     38 * instruction.
     39 */
     40
     41typedef vector signed char unative_t;
     42
     43#define NBYTES(x) ((vector signed char) {x,x,x,x, x,x,x,x, x,x,x,x, x,x,x,x})
     44#define NSIZE	sizeof(unative_t)
     45
     46/*
     47 * The SHLBYTE() operation shifts each byte left by 1, *not*
     48 * rolling over into the next byte
     49 */
     50static inline __attribute_const__ unative_t SHLBYTE(unative_t v)
     51{
     52	return vec_add(v,v);
     53}
     54
     55/*
     56 * The MASK() operation returns 0xFF in any byte for which the high
     57 * bit is 1, 0x00 for any byte for which the high bit is 0.
     58 */
     59static inline __attribute_const__ unative_t MASK(unative_t v)
     60{
     61	unative_t zv = NBYTES(0);
     62
     63	/* vec_cmpgt returns a vector bool char; thus the need for the cast */
     64	return (unative_t)vec_cmpgt(zv, v);
     65}
     66
     67
     68/* This is noinline to make damned sure that gcc doesn't move any of the
     69   Altivec code around the enable/disable code */
     70static void noinline
     71raid6_altivec$#_gen_syndrome_real(int disks, size_t bytes, void **ptrs)
     72{
     73	u8 **dptr = (u8 **)ptrs;
     74	u8 *p, *q;
     75	int d, z, z0;
     76
     77	unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
     78	unative_t x1d = NBYTES(0x1d);
     79
     80	z0 = disks - 3;		/* Highest data disk */
     81	p = dptr[z0+1];		/* XOR parity */
     82	q = dptr[z0+2];		/* RS syndrome */
     83
     84	for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
     85		wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
     86		for ( z = z0-1 ; z >= 0 ; z-- ) {
     87			wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
     88			wp$$ = vec_xor(wp$$, wd$$);
     89			w2$$ = MASK(wq$$);
     90			w1$$ = SHLBYTE(wq$$);
     91			w2$$ = vec_and(w2$$, x1d);
     92			w1$$ = vec_xor(w1$$, w2$$);
     93			wq$$ = vec_xor(w1$$, wd$$);
     94		}
     95		*(unative_t *)&p[d+NSIZE*$$] = wp$$;
     96		*(unative_t *)&q[d+NSIZE*$$] = wq$$;
     97	}
     98}
     99
    100static void raid6_altivec$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
    101{
    102	preempt_disable();
    103	enable_kernel_altivec();
    104
    105	raid6_altivec$#_gen_syndrome_real(disks, bytes, ptrs);
    106
    107	disable_kernel_altivec();
    108	preempt_enable();
    109}
    110
    111int raid6_have_altivec(void);
    112#if $# == 1
    113int raid6_have_altivec(void)
    114{
    115	/* This assumes either all CPUs have Altivec or none does */
    116# ifdef __KERNEL__
    117	return cpu_has_feature(CPU_FTR_ALTIVEC);
    118# else
    119	return 1;
    120# endif
    121}
    122#endif
    123
    124const struct raid6_calls raid6_altivec$# = {
    125	raid6_altivec$#_gen_syndrome,
    126	NULL,			/* XOR not yet implemented */
    127	raid6_have_altivec,
    128	"altivecx$#",
    129	0
    130};
    131
    132#endif /* CONFIG_ALTIVEC */