cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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x86.h (2166B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/* ----------------------------------------------------------------------- *
      3 *
      4 *   Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
      5 *
      6 * ----------------------------------------------------------------------- */
      7
      8/*
      9 * raid6/x86.h
     10 *
     11 * Definitions common to x86 and x86-64 RAID-6 code only
     12 */
     13
     14#ifndef LINUX_RAID_RAID6X86_H
     15#define LINUX_RAID_RAID6X86_H
     16
     17#if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__)
     18
     19#ifdef __KERNEL__ /* Real code */
     20
     21#include <asm/fpu/api.h>
     22
     23#else /* Dummy code for user space testing */
     24
     25static inline void kernel_fpu_begin(void)
     26{
     27}
     28
     29static inline void kernel_fpu_end(void)
     30{
     31}
     32
     33#define __aligned(x) __attribute__((aligned(x)))
     34
     35#define X86_FEATURE_MMX		(0*32+23) /* Multimedia Extensions */
     36#define X86_FEATURE_FXSR	(0*32+24) /* FXSAVE and FXRSTOR instructions
     37					   * (fast save and restore) */
     38#define X86_FEATURE_XMM		(0*32+25) /* Streaming SIMD Extensions */
     39#define X86_FEATURE_XMM2	(0*32+26) /* Streaming SIMD Extensions-2 */
     40#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
     41#define X86_FEATURE_SSSE3	(4*32+ 9) /* Supplemental SSE-3 */
     42#define X86_FEATURE_AVX	(4*32+28) /* Advanced Vector Extensions */
     43#define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
     44#define X86_FEATURE_AVX512F     (9*32+16) /* AVX-512 Foundation */
     45#define X86_FEATURE_AVX512DQ    (9*32+17) /* AVX-512 DQ (Double/Quad granular)
     46					   * Instructions
     47					   */
     48#define X86_FEATURE_AVX512BW    (9*32+30) /* AVX-512 BW (Byte/Word granular)
     49					   * Instructions
     50					   */
     51#define X86_FEATURE_AVX512VL    (9*32+31) /* AVX-512 VL (128/256 Vector Length)
     52					   * Extensions
     53					   */
     54#define X86_FEATURE_MMXEXT	(1*32+22) /* AMD MMX extensions */
     55
     56/* Should work well enough on modern CPUs for testing */
     57static inline int boot_cpu_has(int flag)
     58{
     59	u32 eax, ebx, ecx, edx;
     60
     61	eax = (flag & 0x100) ? 7 :
     62		(flag & 0x20) ? 0x80000001 : 1;
     63	ecx = 0;
     64
     65	asm volatile("cpuid"
     66		     : "+a" (eax), "=b" (ebx), "=d" (edx), "+c" (ecx));
     67
     68	return ((flag & 0x100 ? ebx :
     69		(flag & 0x80) ? ecx : edx) >> (flag & 31)) & 1;
     70}
     71
     72#endif /* ndef __KERNEL__ */
     73
     74#endif
     75#endif