cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dfltcc_util.h (2290B)

      1// SPDX-License-Identifier: Zlib
      2#ifndef DFLTCC_UTIL_H
      3#define DFLTCC_UTIL_H
      4
      5#include <linux/zutil.h>
      6
      7/*
      8 * C wrapper for the DEFLATE CONVERSION CALL instruction.
      9 */
     10typedef enum {
     11    DFLTCC_CC_OK = 0,
     12    DFLTCC_CC_OP1_TOO_SHORT = 1,
     13    DFLTCC_CC_OP2_TOO_SHORT = 2,
     14    DFLTCC_CC_OP2_CORRUPT = 2,
     15    DFLTCC_CC_AGAIN = 3,
     16} dfltcc_cc;
     17
     18#define DFLTCC_QAF 0
     19#define DFLTCC_GDHT 1
     20#define DFLTCC_CMPR 2
     21#define DFLTCC_XPND 4
     22#define HBT_CIRCULAR (1 << 7)
     23#define HB_BITS 15
     24#define HB_SIZE (1 << HB_BITS)
     25
     26static inline dfltcc_cc dfltcc(
     27    int fn,
     28    void *param,
     29    Byte **op1,
     30    size_t *len1,
     31    const Byte **op2,
     32    size_t *len2,
     33    void *hist
     34)
     35{
     36    Byte *t2 = op1 ? *op1 : NULL;
     37    size_t t3 = len1 ? *len1 : 0;
     38    const Byte *t4 = op2 ? *op2 : NULL;
     39    size_t t5 = len2 ? *len2 : 0;
     40    register int r0 __asm__("r0") = fn;
     41    register void *r1 __asm__("r1") = param;
     42    register Byte *r2 __asm__("r2") = t2;
     43    register size_t r3 __asm__("r3") = t3;
     44    register const Byte *r4 __asm__("r4") = t4;
     45    register size_t r5 __asm__("r5") = t5;
     46    int cc;
     47
     48    __asm__ volatile(
     49                     ".insn rrf,0xb9390000,%[r2],%[r4],%[hist],0\n"
     50                     "ipm %[cc]\n"
     51                     : [r2] "+r" (r2)
     52                     , [r3] "+r" (r3)
     53                     , [r4] "+r" (r4)
     54                     , [r5] "+r" (r5)
     55                     , [cc] "=r" (cc)
     56                     : [r0] "r" (r0)
     57                     , [r1] "r" (r1)
     58                     , [hist] "r" (hist)
     59                     : "cc", "memory");
     60    t2 = r2; t3 = r3; t4 = r4; t5 = r5;
     61
     62    if (op1)
     63        *op1 = t2;
     64    if (len1)
     65        *len1 = t3;
     66    if (op2)
     67        *op2 = t4;
     68    if (len2)
     69        *len2 = t5;
     70    return (cc >> 28) & 3;
     71}
     72
     73static inline int is_bit_set(
     74    const char *bits,
     75    int n
     76)
     77{
     78    return bits[n / 8] & (1 << (7 - (n % 8)));
     79}
     80
     81static inline void turn_bit_off(
     82    char *bits,
     83    int n
     84)
     85{
     86    bits[n / 8] &= ~(1 << (7 - (n % 8)));
     87}
     88
     89static inline int dfltcc_are_params_ok(
     90    int level,
     91    uInt window_bits,
     92    int strategy,
     93    uLong level_mask
     94)
     95{
     96    return (level_mask & (1 << level)) != 0 &&
     97        (window_bits == HB_BITS) &&
     98        (strategy == Z_DEFAULT_STRATEGY);
     99}
    100
    101char *oesc_msg(char *buf, int oesc);
    102
    103#endif /* DFLTCC_UTIL_H */