cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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aw2-tsl.c (3442B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*****************************************************************************
      3 *
      4 * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
      5 * Jean-Christian Hassler <jhassler@free.fr>
      6 * Copyright 1998 Emagic Soft- und Hardware GmbH
      7 * Copyright 2002 Martijn Sipkema
      8 *
      9 * This file is part of the Audiowerk2 ALSA driver
     10 *
     11 *****************************************************************************/
     12
     13#define TSL_WS0		(1UL << 31)
     14#define	TSL_WS1		(1UL << 30)
     15#define	TSL_WS2		(1UL << 29)
     16#define TSL_WS3		(1UL << 28)
     17#define TSL_WS4		(1UL << 27)
     18#define	TSL_DIS_A1	(1UL << 24)
     19#define TSL_SDW_A1	(1UL << 23)
     20#define TSL_SIB_A1	(1UL << 22)
     21#define TSL_SF_A1	(1UL << 21)
     22#define	TSL_LF_A1	(1UL << 20)
     23#define TSL_BSEL_A1	(1UL << 17)
     24#define TSL_DOD_A1	(1UL << 15)
     25#define TSL_LOW_A1	(1UL << 14)
     26#define TSL_DIS_A2	(1UL << 11)
     27#define TSL_SDW_A2	(1UL << 10)
     28#define TSL_SIB_A2	(1UL << 9)
     29#define TSL_SF_A2	(1UL << 8)
     30#define TSL_LF_A2	(1UL << 7)
     31#define TSL_BSEL_A2	(1UL << 4)
     32#define TSL_DOD_A2	(1UL << 2)
     33#define TSL_LOW_A2	(1UL << 1)
     34#define TSL_EOS		(1UL << 0)
     35
     36    /* Audiowerk8 hardware setup: */
     37    /*      WS0, SD4, TSL1  - Analog/ digital in */
     38    /*      WS1, SD0, TSL1  - Analog out #1, digital out */
     39    /*      WS2, SD2, TSL1  - Analog out #2 */
     40    /*      WS3, SD1, TSL2  - Analog out #3 */
     41    /*      WS4, SD3, TSL2  - Analog out #4 */
     42
     43    /* Audiowerk8 timing: */
     44    /*      Timeslot:     | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
     45
     46    /*      A1_INPUT: */
     47    /*      SD4:          <_ADC-L_>-------<_ADC-R_>-------< */
     48    /*      WS0:          _______________/---------------\_ */
     49
     50    /*      A1_OUTPUT: */
     51    /*      SD0:          <_1-L___>-------<_1-R___>-------< */
     52    /*      WS1:          _______________/---------------\_ */
     53    /*      SD2:          >-------<_2-L___>-------<_2-R___> */
     54    /*      WS2:          -------\_______________/--------- */
     55
     56    /*      A2_OUTPUT: */
     57    /*      SD1:          <_3-L___>-------<_3-R___>-------< */
     58    /*      WS3:          _______________/---------------\_ */
     59    /*      SD3:          >-------<_4-L___>-------<_4-R___> */
     60    /*      WS4:          -------\_______________/--------- */
     61
     62static const int tsl1[8] = {
     63	1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
     64	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
     65
     66	1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
     67	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
     68
     69	0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
     70	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
     71
     72	0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
     73	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
     74
     75	1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
     76	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
     77
     78	1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
     79	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
     80
     81	0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
     82	0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
     83
     84	0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
     85	0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
     86};
     87
     88static const int tsl2[8] = {
     89	0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
     90	0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
     91	0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
     92	0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
     93	0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
     94	0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
     95	0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
     96	0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
     97};