ct20k2reg.h (2996B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. 4 */ 5 6#ifndef _20K2REGISTERS_H_ 7#define _20K2REGISTERS_H_ 8 9 10/* Timer Registers */ 11#define WC 0x1b7000 12#define TIMR 0x1b7004 13# define TIMR_IE (1<<15) 14# define TIMR_IP (1<<14) 15#define GIP 0x1b7010 16#define GIE 0x1b7014 17 18/* I2C Registers */ 19#define I2C_IF_ADDRESS 0x1B9000 20#define I2C_IF_WDATA 0x1B9004 21#define I2C_IF_RDATA 0x1B9008 22#define I2C_IF_STATUS 0x1B900C 23#define I2C_IF_WLOCK 0x1B9010 24 25/* Global Control Registers */ 26#define GLOBAL_CNTL_GCTL 0x1B7090 27 28/* PLL Registers */ 29#define PLL_CTL 0x1B7080 30#define PLL_STAT 0x1B7084 31#define PLL_ENB 0x1B7088 32 33/* SRC Registers */ 34#define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */ 35#define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */ 36#define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */ 37#define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */ 38#define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */ 39#define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */ 40#define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */ 41#define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */ 42#define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */ 43#define SRC_MCTL 0x1A012C 44#define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */ 45#define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */ 46#define SRC_ENBSTAT 0x1A202C 47#define SRC_ENBSA 0x1A232C 48#define SRC_DN0Z 0x1A0030 49#define SRC_DN1Z 0x1A0040 50#define SRC_UPZ 0x1A0060 51 52/* GPIO Registers */ 53#define GPIO_DATA 0x1B7020 54#define GPIO_CTRL 0x1B7024 55#define GPIO_EXT_DATA 0x1B70A0 56 57/* Virtual memory registers */ 58#define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */ 59#define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */ 60#define VMEM_CTL 0x1C7000 61 62/* Transport Registers */ 63#define TRANSPORT_ENB 0x1B6000 64#define TRANSPORT_CTL 0x1B6004 65#define TRANSPORT_INT 0x1B6008 66 67/* Audio IO */ 68#define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */ 69#define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */ 70#define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */ 71#define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */ 72#define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */ 73#define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */ 74#define AUDIO_IO_MCLK 0x1B5600 75#define AUDIO_IO_TX_BLRCLK 0x1B5604 76#define AUDIO_IO_RX_BLRCLK 0x1B5608 77 78/* Mixer */ 79#define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */ 80#define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */ 81#define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */ 82#define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */ 83#define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */ 84#define MIXER_AR_ENABLE 0x19000C 85 86#endif