ca0132_regs.h (13683B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * HD audio interface patch for Creative CA0132 chip. 4 * CA0132 registers defines. 5 * 6 * Copyright (c) 2011, Creative Technology Ltd. 7 */ 8 9#ifndef __CA0132_REGS_H 10#define __CA0132_REGS_H 11 12#define DSP_CHIP_OFFSET 0x100000 13#define DSP_DBGCNTL_MODULE_OFFSET 0xE30 14#define DSP_DBGCNTL_INST_OFFSET \ 15 (DSP_CHIP_OFFSET + DSP_DBGCNTL_MODULE_OFFSET) 16 17#define DSP_DBGCNTL_EXEC_LOBIT 0x0 18#define DSP_DBGCNTL_EXEC_HIBIT 0x3 19#define DSP_DBGCNTL_EXEC_MASK 0xF 20 21#define DSP_DBGCNTL_SS_LOBIT 0x4 22#define DSP_DBGCNTL_SS_HIBIT 0x7 23#define DSP_DBGCNTL_SS_MASK 0xF0 24 25#define DSP_DBGCNTL_STATE_LOBIT 0xA 26#define DSP_DBGCNTL_STATE_HIBIT 0xD 27#define DSP_DBGCNTL_STATE_MASK 0x3C00 28 29#define XRAM_CHIP_OFFSET 0x0 30#define XRAM_XRAM_CHANNEL_COUNT 0xE000 31#define XRAM_XRAM_MODULE_OFFSET 0x0 32#define XRAM_XRAM_CHAN_INCR 4 33#define XRAM_XRAM_INST_OFFSET(_chan) \ 34 (XRAM_CHIP_OFFSET + XRAM_XRAM_MODULE_OFFSET + \ 35 (_chan * XRAM_XRAM_CHAN_INCR)) 36 37#define YRAM_CHIP_OFFSET 0x40000 38#define YRAM_YRAM_CHANNEL_COUNT 0x8000 39#define YRAM_YRAM_MODULE_OFFSET 0x0 40#define YRAM_YRAM_CHAN_INCR 4 41#define YRAM_YRAM_INST_OFFSET(_chan) \ 42 (YRAM_CHIP_OFFSET + YRAM_YRAM_MODULE_OFFSET + \ 43 (_chan * YRAM_YRAM_CHAN_INCR)) 44 45#define UC_CHIP_OFFSET 0x80000 46#define UC_UC_CHANNEL_COUNT 0x10000 47#define UC_UC_MODULE_OFFSET 0x0 48#define UC_UC_CHAN_INCR 4 49#define UC_UC_INST_OFFSET(_chan) \ 50 (UC_CHIP_OFFSET + UC_UC_MODULE_OFFSET + \ 51 (_chan * UC_UC_CHAN_INCR)) 52 53#define AXRAM_CHIP_OFFSET 0x3C000 54#define AXRAM_AXRAM_CHANNEL_COUNT 0x1000 55#define AXRAM_AXRAM_MODULE_OFFSET 0x0 56#define AXRAM_AXRAM_CHAN_INCR 4 57#define AXRAM_AXRAM_INST_OFFSET(_chan) \ 58 (AXRAM_CHIP_OFFSET + AXRAM_AXRAM_MODULE_OFFSET + \ 59 (_chan * AXRAM_AXRAM_CHAN_INCR)) 60 61#define AYRAM_CHIP_OFFSET 0x78000 62#define AYRAM_AYRAM_CHANNEL_COUNT 0x1000 63#define AYRAM_AYRAM_MODULE_OFFSET 0x0 64#define AYRAM_AYRAM_CHAN_INCR 4 65#define AYRAM_AYRAM_INST_OFFSET(_chan) \ 66 (AYRAM_CHIP_OFFSET + AYRAM_AYRAM_MODULE_OFFSET + \ 67 (_chan * AYRAM_AYRAM_CHAN_INCR)) 68 69#define DSPDMAC_CHIP_OFFSET 0x110000 70#define DSPDMAC_DMA_CFG_CHANNEL_COUNT 12 71#define DSPDMAC_DMACFG_MODULE_OFFSET 0xF00 72#define DSPDMAC_DMACFG_CHAN_INCR 0x10 73#define DSPDMAC_DMACFG_INST_OFFSET(_chan) \ 74 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DMACFG_MODULE_OFFSET + \ 75 (_chan * DSPDMAC_DMACFG_CHAN_INCR)) 76 77#define DSPDMAC_DMACFG_DBADR_LOBIT 0x0 78#define DSPDMAC_DMACFG_DBADR_HIBIT 0x10 79#define DSPDMAC_DMACFG_DBADR_MASK 0x1FFFF 80#define DSPDMAC_DMACFG_LP_LOBIT 0x11 81#define DSPDMAC_DMACFG_LP_HIBIT 0x11 82#define DSPDMAC_DMACFG_LP_MASK 0x20000 83 84#define DSPDMAC_DMACFG_AINCR_LOBIT 0x12 85#define DSPDMAC_DMACFG_AINCR_HIBIT 0x12 86#define DSPDMAC_DMACFG_AINCR_MASK 0x40000 87 88#define DSPDMAC_DMACFG_DWR_LOBIT 0x13 89#define DSPDMAC_DMACFG_DWR_HIBIT 0x13 90#define DSPDMAC_DMACFG_DWR_MASK 0x80000 91 92#define DSPDMAC_DMACFG_AJUMP_LOBIT 0x14 93#define DSPDMAC_DMACFG_AJUMP_HIBIT 0x17 94#define DSPDMAC_DMACFG_AJUMP_MASK 0xF00000 95 96#define DSPDMAC_DMACFG_AMODE_LOBIT 0x18 97#define DSPDMAC_DMACFG_AMODE_HIBIT 0x19 98#define DSPDMAC_DMACFG_AMODE_MASK 0x3000000 99 100#define DSPDMAC_DMACFG_LK_LOBIT 0x1A 101#define DSPDMAC_DMACFG_LK_HIBIT 0x1A 102#define DSPDMAC_DMACFG_LK_MASK 0x4000000 103 104#define DSPDMAC_DMACFG_AICS_LOBIT 0x1B 105#define DSPDMAC_DMACFG_AICS_HIBIT 0x1F 106#define DSPDMAC_DMACFG_AICS_MASK 0xF8000000 107 108#define DSPDMAC_DMACFG_LP_SINGLE 0 109#define DSPDMAC_DMACFG_LP_LOOPING 1 110 111#define DSPDMAC_DMACFG_AINCR_XANDY 0 112#define DSPDMAC_DMACFG_AINCR_XORY 1 113 114#define DSPDMAC_DMACFG_DWR_DMA_RD 0 115#define DSPDMAC_DMACFG_DWR_DMA_WR 1 116 117#define DSPDMAC_DMACFG_AMODE_LINEAR 0 118#define DSPDMAC_DMACFG_AMODE_RSV1 1 119#define DSPDMAC_DMACFG_AMODE_WINTLV 2 120#define DSPDMAC_DMACFG_AMODE_GINTLV 3 121 122#define DSPDMAC_DSP_ADR_OFS_CHANNEL_COUNT 12 123#define DSPDMAC_DSPADROFS_MODULE_OFFSET 0xF04 124#define DSPDMAC_DSPADROFS_CHAN_INCR 0x10 125#define DSPDMAC_DSPADROFS_INST_OFFSET(_chan) \ 126 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADROFS_MODULE_OFFSET + \ 127 (_chan * DSPDMAC_DSPADROFS_CHAN_INCR)) 128 129#define DSPDMAC_DSPADROFS_COFS_LOBIT 0x0 130#define DSPDMAC_DSPADROFS_COFS_HIBIT 0xF 131#define DSPDMAC_DSPADROFS_COFS_MASK 0xFFFF 132 133#define DSPDMAC_DSPADROFS_BOFS_LOBIT 0x10 134#define DSPDMAC_DSPADROFS_BOFS_HIBIT 0x1F 135#define DSPDMAC_DSPADROFS_BOFS_MASK 0xFFFF0000 136 137#define DSPDMAC_DSP_ADR_WOFS_CHANNEL_COUNT 12 138#define DSPDMAC_DSPADRWOFS_MODULE_OFFSET 0xF04 139#define DSPDMAC_DSPADRWOFS_CHAN_INCR 0x10 140 141#define DSPDMAC_DSPADRWOFS_INST_OFFSET(_chan) \ 142 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRWOFS_MODULE_OFFSET + \ 143 (_chan * DSPDMAC_DSPADRWOFS_CHAN_INCR)) 144 145#define DSPDMAC_DSPADRWOFS_WCOFS_LOBIT 0x0 146#define DSPDMAC_DSPADRWOFS_WCOFS_HIBIT 0xA 147#define DSPDMAC_DSPADRWOFS_WCOFS_MASK 0x7FF 148 149#define DSPDMAC_DSPADRWOFS_WCBFR_LOBIT 0xB 150#define DSPDMAC_DSPADRWOFS_WCBFR_HIBIT 0xF 151#define DSPDMAC_DSPADRWOFS_WCBFR_MASK 0xF800 152 153#define DSPDMAC_DSPADRWOFS_WBOFS_LOBIT 0x10 154#define DSPDMAC_DSPADRWOFS_WBOFS_HIBIT 0x1A 155#define DSPDMAC_DSPADRWOFS_WBOFS_MASK 0x7FF0000 156 157#define DSPDMAC_DSPADRWOFS_WBBFR_LOBIT 0x1B 158#define DSPDMAC_DSPADRWOFS_WBBFR_HIBIT 0x1F 159#define DSPDMAC_DSPADRWOFS_WBBFR_MASK 0xF8000000 160 161#define DSPDMAC_DSP_ADR_GOFS_CHANNEL_COUNT 12 162#define DSPDMAC_DSPADRGOFS_MODULE_OFFSET 0xF04 163#define DSPDMAC_DSPADRGOFS_CHAN_INCR 0x10 164#define DSPDMAC_DSPADRGOFS_INST_OFFSET(_chan) \ 165 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRGOFS_MODULE_OFFSET + \ 166 (_chan * DSPDMAC_DSPADRGOFS_CHAN_INCR)) 167 168#define DSPDMAC_DSPADRGOFS_GCOFS_LOBIT 0x0 169#define DSPDMAC_DSPADRGOFS_GCOFS_HIBIT 0x9 170#define DSPDMAC_DSPADRGOFS_GCOFS_MASK 0x3FF 171 172#define DSPDMAC_DSPADRGOFS_GCS_LOBIT 0xA 173#define DSPDMAC_DSPADRGOFS_GCS_HIBIT 0xC 174#define DSPDMAC_DSPADRGOFS_GCS_MASK 0x1C00 175 176#define DSPDMAC_DSPADRGOFS_GCBFR_LOBIT 0xD 177#define DSPDMAC_DSPADRGOFS_GCBFR_HIBIT 0xF 178#define DSPDMAC_DSPADRGOFS_GCBFR_MASK 0xE000 179 180#define DSPDMAC_DSPADRGOFS_GBOFS_LOBIT 0x10 181#define DSPDMAC_DSPADRGOFS_GBOFS_HIBIT 0x19 182#define DSPDMAC_DSPADRGOFS_GBOFS_MASK 0x3FF0000 183 184#define DSPDMAC_DSPADRGOFS_GBS_LOBIT 0x1A 185#define DSPDMAC_DSPADRGOFS_GBS_HIBIT 0x1C 186#define DSPDMAC_DSPADRGOFS_GBS_MASK 0x1C000000 187 188#define DSPDMAC_DSPADRGOFS_GBBFR_LOBIT 0x1D 189#define DSPDMAC_DSPADRGOFS_GBBFR_HIBIT 0x1F 190#define DSPDMAC_DSPADRGOFS_GBBFR_MASK 0xE0000000 191 192#define DSPDMAC_XFR_CNT_CHANNEL_COUNT 12 193#define DSPDMAC_XFRCNT_MODULE_OFFSET 0xF08 194#define DSPDMAC_XFRCNT_CHAN_INCR 0x10 195 196#define DSPDMAC_XFRCNT_INST_OFFSET(_chan) \ 197 (DSPDMAC_CHIP_OFFSET + DSPDMAC_XFRCNT_MODULE_OFFSET + \ 198 (_chan * DSPDMAC_XFRCNT_CHAN_INCR)) 199 200#define DSPDMAC_XFRCNT_CCNT_LOBIT 0x0 201#define DSPDMAC_XFRCNT_CCNT_HIBIT 0xF 202#define DSPDMAC_XFRCNT_CCNT_MASK 0xFFFF 203 204#define DSPDMAC_XFRCNT_BCNT_LOBIT 0x10 205#define DSPDMAC_XFRCNT_BCNT_HIBIT 0x1F 206#define DSPDMAC_XFRCNT_BCNT_MASK 0xFFFF0000 207 208#define DSPDMAC_IRQ_CNT_CHANNEL_COUNT 12 209#define DSPDMAC_IRQCNT_MODULE_OFFSET 0xF0C 210#define DSPDMAC_IRQCNT_CHAN_INCR 0x10 211#define DSPDMAC_IRQCNT_INST_OFFSET(_chan) \ 212 (DSPDMAC_CHIP_OFFSET + DSPDMAC_IRQCNT_MODULE_OFFSET + \ 213 (_chan * DSPDMAC_IRQCNT_CHAN_INCR)) 214 215#define DSPDMAC_IRQCNT_CICNT_LOBIT 0x0 216#define DSPDMAC_IRQCNT_CICNT_HIBIT 0xF 217#define DSPDMAC_IRQCNT_CICNT_MASK 0xFFFF 218 219#define DSPDMAC_IRQCNT_BICNT_LOBIT 0x10 220#define DSPDMAC_IRQCNT_BICNT_HIBIT 0x1F 221#define DSPDMAC_IRQCNT_BICNT_MASK 0xFFFF0000 222 223#define DSPDMAC_AUD_CHSEL_CHANNEL_COUNT 12 224#define DSPDMAC_AUDCHSEL_MODULE_OFFSET 0xFC0 225#define DSPDMAC_AUDCHSEL_CHAN_INCR 0x4 226#define DSPDMAC_AUDCHSEL_INST_OFFSET(_chan) \ 227 (DSPDMAC_CHIP_OFFSET + DSPDMAC_AUDCHSEL_MODULE_OFFSET + \ 228 (_chan * DSPDMAC_AUDCHSEL_CHAN_INCR)) 229 230#define DSPDMAC_AUDCHSEL_ACS_LOBIT 0x0 231#define DSPDMAC_AUDCHSEL_ACS_HIBIT 0x1F 232#define DSPDMAC_AUDCHSEL_ACS_MASK 0xFFFFFFFF 233 234#define DSPDMAC_CHNLSTART_MODULE_OFFSET 0xFF0 235#define DSPDMAC_CHNLSTART_INST_OFFSET \ 236 (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTART_MODULE_OFFSET) 237 238#define DSPDMAC_CHNLSTART_EN_LOBIT 0x0 239#define DSPDMAC_CHNLSTART_EN_HIBIT 0xB 240#define DSPDMAC_CHNLSTART_EN_MASK 0xFFF 241 242#define DSPDMAC_CHNLSTART_VAI1_LOBIT 0xC 243#define DSPDMAC_CHNLSTART_VAI1_HIBIT 0xF 244#define DSPDMAC_CHNLSTART_VAI1_MASK 0xF000 245 246#define DSPDMAC_CHNLSTART_DIS_LOBIT 0x10 247#define DSPDMAC_CHNLSTART_DIS_HIBIT 0x1B 248#define DSPDMAC_CHNLSTART_DIS_MASK 0xFFF0000 249 250#define DSPDMAC_CHNLSTART_VAI2_LOBIT 0x1C 251#define DSPDMAC_CHNLSTART_VAI2_HIBIT 0x1F 252#define DSPDMAC_CHNLSTART_VAI2_MASK 0xF0000000 253 254#define DSPDMAC_CHNLSTATUS_MODULE_OFFSET 0xFF4 255#define DSPDMAC_CHNLSTATUS_INST_OFFSET \ 256 (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTATUS_MODULE_OFFSET) 257 258#define DSPDMAC_CHNLSTATUS_ISC_LOBIT 0x0 259#define DSPDMAC_CHNLSTATUS_ISC_HIBIT 0xB 260#define DSPDMAC_CHNLSTATUS_ISC_MASK 0xFFF 261 262#define DSPDMAC_CHNLSTATUS_AOO_LOBIT 0xC 263#define DSPDMAC_CHNLSTATUS_AOO_HIBIT 0xC 264#define DSPDMAC_CHNLSTATUS_AOO_MASK 0x1000 265 266#define DSPDMAC_CHNLSTATUS_AOU_LOBIT 0xD 267#define DSPDMAC_CHNLSTATUS_AOU_HIBIT 0xD 268#define DSPDMAC_CHNLSTATUS_AOU_MASK 0x2000 269 270#define DSPDMAC_CHNLSTATUS_AIO_LOBIT 0xE 271#define DSPDMAC_CHNLSTATUS_AIO_HIBIT 0xE 272#define DSPDMAC_CHNLSTATUS_AIO_MASK 0x4000 273 274#define DSPDMAC_CHNLSTATUS_AIU_LOBIT 0xF 275#define DSPDMAC_CHNLSTATUS_AIU_HIBIT 0xF 276#define DSPDMAC_CHNLSTATUS_AIU_MASK 0x8000 277 278#define DSPDMAC_CHNLSTATUS_IEN_LOBIT 0x10 279#define DSPDMAC_CHNLSTATUS_IEN_HIBIT 0x1B 280#define DSPDMAC_CHNLSTATUS_IEN_MASK 0xFFF0000 281 282#define DSPDMAC_CHNLSTATUS_VAI0_LOBIT 0x1C 283#define DSPDMAC_CHNLSTATUS_VAI0_HIBIT 0x1F 284#define DSPDMAC_CHNLSTATUS_VAI0_MASK 0xF0000000 285 286#define DSPDMAC_CHNLPROP_MODULE_OFFSET 0xFF8 287#define DSPDMAC_CHNLPROP_INST_OFFSET \ 288 (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLPROP_MODULE_OFFSET) 289 290#define DSPDMAC_CHNLPROP_DCON_LOBIT 0x0 291#define DSPDMAC_CHNLPROP_DCON_HIBIT 0xB 292#define DSPDMAC_CHNLPROP_DCON_MASK 0xFFF 293 294#define DSPDMAC_CHNLPROP_FFS_LOBIT 0xC 295#define DSPDMAC_CHNLPROP_FFS_HIBIT 0xC 296#define DSPDMAC_CHNLPROP_FFS_MASK 0x1000 297 298#define DSPDMAC_CHNLPROP_NAJ_LOBIT 0xD 299#define DSPDMAC_CHNLPROP_NAJ_HIBIT 0xD 300#define DSPDMAC_CHNLPROP_NAJ_MASK 0x2000 301 302#define DSPDMAC_CHNLPROP_ENH_LOBIT 0xE 303#define DSPDMAC_CHNLPROP_ENH_HIBIT 0xE 304#define DSPDMAC_CHNLPROP_ENH_MASK 0x4000 305 306#define DSPDMAC_CHNLPROP_MSPCE_LOBIT 0x10 307#define DSPDMAC_CHNLPROP_MSPCE_HIBIT 0x1B 308#define DSPDMAC_CHNLPROP_MSPCE_MASK 0xFFF0000 309 310#define DSPDMAC_CHNLPROP_AC_LOBIT 0x1C 311#define DSPDMAC_CHNLPROP_AC_HIBIT 0x1F 312#define DSPDMAC_CHNLPROP_AC_MASK 0xF0000000 313 314#define DSPDMAC_ACTIVE_MODULE_OFFSET 0xFFC 315#define DSPDMAC_ACTIVE_INST_OFFSET \ 316 (DSPDMAC_CHIP_OFFSET + DSPDMAC_ACTIVE_MODULE_OFFSET) 317 318#define DSPDMAC_ACTIVE_AAR_LOBIT 0x0 319#define DSPDMAC_ACTIVE_AAR_HIBIT 0xB 320#define DSPDMAC_ACTIVE_AAR_MASK 0xFFF 321 322#define DSPDMAC_ACTIVE_WFR_LOBIT 0xC 323#define DSPDMAC_ACTIVE_WFR_HIBIT 0x17 324#define DSPDMAC_ACTIVE_WFR_MASK 0xFFF000 325 326#define DSP_AUX_MEM_BASE 0xE000 327#define INVALID_CHIP_ADDRESS (~0U) 328 329#define X_SIZE (XRAM_XRAM_CHANNEL_COUNT * XRAM_XRAM_CHAN_INCR) 330#define Y_SIZE (YRAM_YRAM_CHANNEL_COUNT * YRAM_YRAM_CHAN_INCR) 331#define AX_SIZE (AXRAM_AXRAM_CHANNEL_COUNT * AXRAM_AXRAM_CHAN_INCR) 332#define AY_SIZE (AYRAM_AYRAM_CHANNEL_COUNT * AYRAM_AYRAM_CHAN_INCR) 333#define UC_SIZE (UC_UC_CHANNEL_COUNT * UC_UC_CHAN_INCR) 334 335#define XEXT_SIZE (X_SIZE + AX_SIZE) 336#define YEXT_SIZE (Y_SIZE + AY_SIZE) 337 338#define U64K 0x10000UL 339 340#define X_END (XRAM_CHIP_OFFSET + X_SIZE) 341#define X_EXT (XRAM_CHIP_OFFSET + XEXT_SIZE) 342#define AX_END (XRAM_CHIP_OFFSET + U64K*4) 343 344#define Y_END (YRAM_CHIP_OFFSET + Y_SIZE) 345#define Y_EXT (YRAM_CHIP_OFFSET + YEXT_SIZE) 346#define AY_END (YRAM_CHIP_OFFSET + U64K*4) 347 348#define UC_END (UC_CHIP_OFFSET + UC_SIZE) 349 350#define X_RANGE_MAIN(a, s) \ 351 (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_END)) 352#define X_RANGE_AUX(a, s) \ 353 (((a) >= X_END) && ((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END)) 354#define X_RANGE_EXT(a, s) \ 355 (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_EXT)) 356#define X_RANGE_ALL(a, s) \ 357 (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END)) 358 359#define Y_RANGE_MAIN(a, s) \ 360 (((a) >= YRAM_CHIP_OFFSET) && \ 361 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_END)) 362#define Y_RANGE_AUX(a, s) \ 363 (((a) >= Y_END) && \ 364 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END)) 365#define Y_RANGE_EXT(a, s) \ 366 (((a) >= YRAM_CHIP_OFFSET) && \ 367 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_EXT)) 368#define Y_RANGE_ALL(a, s) \ 369 (((a) >= YRAM_CHIP_OFFSET) && \ 370 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END)) 371 372#define UC_RANGE(a, s) \ 373 (((a) >= UC_CHIP_OFFSET) && \ 374 ((a)+((s)-1)*UC_UC_CHAN_INCR < UC_END)) 375 376#define X_OFF(a) \ 377 (((a) - XRAM_CHIP_OFFSET) / XRAM_XRAM_CHAN_INCR) 378#define AX_OFF(a) \ 379 (((a) % (AXRAM_AXRAM_CHANNEL_COUNT * \ 380 AXRAM_AXRAM_CHAN_INCR)) / AXRAM_AXRAM_CHAN_INCR) 381 382#define Y_OFF(a) \ 383 (((a) - YRAM_CHIP_OFFSET) / YRAM_YRAM_CHAN_INCR) 384#define AY_OFF(a) \ 385 (((a) % (AYRAM_AYRAM_CHANNEL_COUNT * \ 386 AYRAM_AYRAM_CHAN_INCR)) / AYRAM_AYRAM_CHAN_INCR) 387 388#define UC_OFF(a) (((a) - UC_CHIP_OFFSET) / UC_UC_CHAN_INCR) 389 390#define X_EXT_MAIN_SIZE(a) (XRAM_XRAM_CHANNEL_COUNT - X_OFF(a)) 391#define X_EXT_AUX_SIZE(a, s) ((s) - X_EXT_MAIN_SIZE(a)) 392 393#define Y_EXT_MAIN_SIZE(a) (YRAM_YRAM_CHANNEL_COUNT - Y_OFF(a)) 394#define Y_EXT_AUX_SIZE(a, s) ((s) - Y_EXT_MAIN_SIZE(a)) 395 396#endif