cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel8x0.c (89704B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 *   ALSA driver for Intel ICH (i8x0) chipsets
      4 *
      5 *	Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
      6 *
      7 *   This code also contains alpha support for SiS 735 chipsets provided
      8 *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
      9 *   for SiS735, so the code is not fully functional.
     10 *
     11
     12 */      
     13
     14#include <linux/io.h>
     15#include <linux/delay.h>
     16#include <linux/interrupt.h>
     17#include <linux/init.h>
     18#include <linux/pci.h>
     19#include <linux/slab.h>
     20#include <linux/module.h>
     21#include <sound/core.h>
     22#include <sound/pcm.h>
     23#include <sound/ac97_codec.h>
     24#include <sound/info.h>
     25#include <sound/initval.h>
     26
     27MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
     28MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
     29MODULE_LICENSE("GPL");
     30
     31static int index = SNDRV_DEFAULT_IDX1;	/* Index 0-MAX */
     32static char *id = SNDRV_DEFAULT_STR1;	/* ID for this card */
     33static int ac97_clock;
     34static char *ac97_quirk;
     35static bool buggy_semaphore;
     36static int buggy_irq = -1; /* auto-check */
     37static bool xbox;
     38static int spdif_aclink = -1;
     39static int inside_vm = -1;
     40
     41module_param(index, int, 0444);
     42MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
     43module_param(id, charp, 0444);
     44MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
     45module_param(ac97_clock, int, 0444);
     46MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
     47module_param(ac97_quirk, charp, 0444);
     48MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
     49module_param(buggy_semaphore, bool, 0444);
     50MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
     51module_param(buggy_irq, bint, 0444);
     52MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
     53module_param(xbox, bool, 0444);
     54MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
     55module_param(spdif_aclink, int, 0444);
     56MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
     57module_param(inside_vm, bint, 0444);
     58MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
     59
     60/* just for backward compatibility */
     61static bool enable;
     62module_param(enable, bool, 0444);
     63static int joystick;
     64module_param(joystick, int, 0444);
     65
     66/*
     67 *  Direct registers
     68 */
     69enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
     70
     71#define ICHREG(x) ICH_REG_##x
     72
     73#define DEFINE_REGSET(name,base) \
     74enum { \
     75	ICH_REG_##name##_BDBAR	= base + 0x0,	/* dword - buffer descriptor list base address */ \
     76	ICH_REG_##name##_CIV	= base + 0x04,	/* byte - current index value */ \
     77	ICH_REG_##name##_LVI	= base + 0x05,	/* byte - last valid index */ \
     78	ICH_REG_##name##_SR	= base + 0x06,	/* byte - status register */ \
     79	ICH_REG_##name##_PICB	= base + 0x08,	/* word - position in current buffer */ \
     80	ICH_REG_##name##_PIV	= base + 0x0a,	/* byte - prefetched index value */ \
     81	ICH_REG_##name##_CR	= base + 0x0b,	/* byte - control register */ \
     82}
     83
     84/* busmaster blocks */
     85DEFINE_REGSET(OFF, 0);		/* offset */
     86DEFINE_REGSET(PI, 0x00);	/* PCM in */
     87DEFINE_REGSET(PO, 0x10);	/* PCM out */
     88DEFINE_REGSET(MC, 0x20);	/* Mic in */
     89
     90/* ICH4 busmaster blocks */
     91DEFINE_REGSET(MC2, 0x40);	/* Mic in 2 */
     92DEFINE_REGSET(PI2, 0x50);	/* PCM in 2 */
     93DEFINE_REGSET(SP, 0x60);	/* SPDIF out */
     94
     95/* values for each busmaster block */
     96
     97/* LVI */
     98#define ICH_REG_LVI_MASK		0x1f
     99
    100/* SR */
    101#define ICH_FIFOE			0x10	/* FIFO error */
    102#define ICH_BCIS			0x08	/* buffer completion interrupt status */
    103#define ICH_LVBCI			0x04	/* last valid buffer completion interrupt */
    104#define ICH_CELV			0x02	/* current equals last valid */
    105#define ICH_DCH				0x01	/* DMA controller halted */
    106
    107/* PIV */
    108#define ICH_REG_PIV_MASK		0x1f	/* mask */
    109
    110/* CR */
    111#define ICH_IOCE			0x10	/* interrupt on completion enable */
    112#define ICH_FEIE			0x08	/* fifo error interrupt enable */
    113#define ICH_LVBIE			0x04	/* last valid buffer interrupt enable */
    114#define ICH_RESETREGS			0x02	/* reset busmaster registers */
    115#define ICH_STARTBM			0x01	/* start busmaster operation */
    116
    117
    118/* global block */
    119#define ICH_REG_GLOB_CNT		0x2c	/* dword - global control */
    120#define   ICH_PCM_SPDIF_MASK	0xc0000000	/* s/pdif pcm slot mask (ICH4) */
    121#define   ICH_PCM_SPDIF_NONE	0x00000000	/* reserved - undefined */
    122#define   ICH_PCM_SPDIF_78	0x40000000	/* s/pdif pcm on slots 7&8 */
    123#define   ICH_PCM_SPDIF_69	0x80000000	/* s/pdif pcm on slots 6&9 */
    124#define   ICH_PCM_SPDIF_1011	0xc0000000	/* s/pdif pcm on slots 10&11 */
    125#define   ICH_PCM_20BIT		0x00400000	/* 20-bit samples (ICH4) */
    126#define   ICH_PCM_246_MASK	0x00300000	/* chan mask (not all chips) */
    127#define   ICH_PCM_8		0x00300000      /* 8 channels (not all chips) */
    128#define   ICH_PCM_6		0x00200000	/* 6 channels (not all chips) */
    129#define   ICH_PCM_4		0x00100000	/* 4 channels (not all chips) */
    130#define   ICH_PCM_2		0x00000000	/* 2 channels (stereo) */
    131#define   ICH_SIS_PCM_246_MASK	0x000000c0	/* 6 channels (SIS7012) */
    132#define   ICH_SIS_PCM_6		0x00000080	/* 6 channels (SIS7012) */
    133#define   ICH_SIS_PCM_4		0x00000040	/* 4 channels (SIS7012) */
    134#define   ICH_SIS_PCM_2		0x00000000	/* 2 channels (SIS7012) */
    135#define   ICH_TRIE		0x00000040	/* tertiary resume interrupt enable */
    136#define   ICH_SRIE		0x00000020	/* secondary resume interrupt enable */
    137#define   ICH_PRIE		0x00000010	/* primary resume interrupt enable */
    138#define   ICH_ACLINK		0x00000008	/* AClink shut off */
    139#define   ICH_AC97WARM		0x00000004	/* AC'97 warm reset */
    140#define   ICH_AC97COLD		0x00000002	/* AC'97 cold reset */
    141#define   ICH_GIE		0x00000001	/* GPI interrupt enable */
    142#define ICH_REG_GLOB_STA		0x30	/* dword - global status */
    143#define   ICH_TRI		0x20000000	/* ICH4: tertiary (AC_SDIN2) resume interrupt */
    144#define   ICH_TCR		0x10000000	/* ICH4: tertiary (AC_SDIN2) codec ready */
    145#define   ICH_BCS		0x08000000	/* ICH4: bit clock stopped */
    146#define   ICH_SPINT		0x04000000	/* ICH4: S/PDIF interrupt */
    147#define   ICH_P2INT		0x02000000	/* ICH4: PCM2-In interrupt */
    148#define   ICH_M2INT		0x01000000	/* ICH4: Mic2-In interrupt */
    149#define   ICH_SAMPLE_CAP	0x00c00000	/* ICH4: sample capability bits (RO) */
    150#define   ICH_SAMPLE_16_20	0x00400000	/* ICH4: 16- and 20-bit samples */
    151#define   ICH_MULTICHAN_CAP	0x00300000	/* ICH4: multi-channel capability bits (RO) */
    152#define   ICH_SIS_TRI		0x00080000	/* SIS: tertiary resume irq */
    153#define   ICH_SIS_TCR		0x00040000	/* SIS: tertiary codec ready */
    154#define   ICH_MD3		0x00020000	/* modem power down semaphore */
    155#define   ICH_AD3		0x00010000	/* audio power down semaphore */
    156#define   ICH_RCS		0x00008000	/* read completion status */
    157#define   ICH_BIT3		0x00004000	/* bit 3 slot 12 */
    158#define   ICH_BIT2		0x00002000	/* bit 2 slot 12 */
    159#define   ICH_BIT1		0x00001000	/* bit 1 slot 12 */
    160#define   ICH_SRI		0x00000800	/* secondary (AC_SDIN1) resume interrupt */
    161#define   ICH_PRI		0x00000400	/* primary (AC_SDIN0) resume interrupt */
    162#define   ICH_SCR		0x00000200	/* secondary (AC_SDIN1) codec ready */
    163#define   ICH_PCR		0x00000100	/* primary (AC_SDIN0) codec ready */
    164#define   ICH_MCINT		0x00000080	/* MIC capture interrupt */
    165#define   ICH_POINT		0x00000040	/* playback interrupt */
    166#define   ICH_PIINT		0x00000020	/* capture interrupt */
    167#define   ICH_NVSPINT		0x00000010	/* nforce spdif interrupt */
    168#define   ICH_MOINT		0x00000004	/* modem playback interrupt */
    169#define   ICH_MIINT		0x00000002	/* modem capture interrupt */
    170#define   ICH_GSCI		0x00000001	/* GPI status change interrupt */
    171#define ICH_REG_ACC_SEMA		0x34	/* byte - codec write semaphore */
    172#define   ICH_CAS		0x01		/* codec access semaphore */
    173#define ICH_REG_SDM		0x80
    174#define   ICH_DI2L_MASK		0x000000c0	/* PCM In 2, Mic In 2 data in line */
    175#define   ICH_DI2L_SHIFT	6
    176#define   ICH_DI1L_MASK		0x00000030	/* PCM In 1, Mic In 1 data in line */
    177#define   ICH_DI1L_SHIFT	4
    178#define   ICH_SE		0x00000008	/* steer enable */
    179#define   ICH_LDI_MASK		0x00000003	/* last codec read data input */
    180
    181#define ICH_MAX_FRAGS		32		/* max hw frags */
    182
    183
    184/*
    185 * registers for Ali5455
    186 */
    187
    188/* ALi 5455 busmaster blocks */
    189DEFINE_REGSET(AL_PI, 0x40);	/* ALi PCM in */
    190DEFINE_REGSET(AL_PO, 0x50);	/* Ali PCM out */
    191DEFINE_REGSET(AL_MC, 0x60);	/* Ali Mic in */
    192DEFINE_REGSET(AL_CDC_SPO, 0x70);	/* Ali Codec SPDIF out */
    193DEFINE_REGSET(AL_CENTER, 0x80);		/* Ali center out */
    194DEFINE_REGSET(AL_LFE, 0x90);		/* Ali center out */
    195DEFINE_REGSET(AL_CLR_SPI, 0xa0);	/* Ali Controller SPDIF in */
    196DEFINE_REGSET(AL_CLR_SPO, 0xb0);	/* Ali Controller SPDIF out */
    197DEFINE_REGSET(AL_I2S, 0xc0);	/* Ali I2S in */
    198DEFINE_REGSET(AL_PI2, 0xd0);	/* Ali PCM2 in */
    199DEFINE_REGSET(AL_MC2, 0xe0);	/* Ali Mic2 in */
    200
    201enum {
    202	ICH_REG_ALI_SCR = 0x00,		/* System Control Register */
    203	ICH_REG_ALI_SSR = 0x04,		/* System Status Register  */
    204	ICH_REG_ALI_DMACR = 0x08,	/* DMA Control Register    */
    205	ICH_REG_ALI_FIFOCR1 = 0x0c,	/* FIFO Control Register 1  */
    206	ICH_REG_ALI_INTERFACECR = 0x10,	/* Interface Control Register */
    207	ICH_REG_ALI_INTERRUPTCR = 0x14,	/* Interrupt control Register */
    208	ICH_REG_ALI_INTERRUPTSR = 0x18,	/* Interrupt  Status Register */
    209	ICH_REG_ALI_FIFOCR2 = 0x1c,	/* FIFO Control Register 2   */
    210	ICH_REG_ALI_CPR = 0x20,		/* Command Port Register     */
    211	ICH_REG_ALI_CPR_ADDR = 0x22,	/* ac97 addr write */
    212	ICH_REG_ALI_SPR = 0x24,		/* Status Port Register      */
    213	ICH_REG_ALI_SPR_ADDR = 0x26,	/* ac97 addr read */
    214	ICH_REG_ALI_FIFOCR3 = 0x2c,	/* FIFO Control Register 3  */
    215	ICH_REG_ALI_TTSR = 0x30,	/* Transmit Tag Slot Register */
    216	ICH_REG_ALI_RTSR = 0x34,	/* Receive Tag Slot  Register */
    217	ICH_REG_ALI_CSPSR = 0x38,	/* Command/Status Port Status Register */
    218	ICH_REG_ALI_CAS = 0x3c,		/* Codec Write Semaphore Register */
    219	ICH_REG_ALI_HWVOL = 0xf0,	/* hardware volume control/status */
    220	ICH_REG_ALI_I2SCR = 0xf4,	/* I2S control/status */
    221	ICH_REG_ALI_SPDIFCSR = 0xf8,	/* spdif channel status register  */
    222	ICH_REG_ALI_SPDIFICS = 0xfc,	/* spdif interface control/status  */
    223};
    224
    225#define ALI_CAS_SEM_BUSY	0x80000000
    226#define ALI_CPR_ADDR_SECONDARY	0x100
    227#define ALI_CPR_ADDR_READ	0x80
    228#define ALI_CSPSR_CODEC_READY	0x08
    229#define ALI_CSPSR_READ_OK	0x02
    230#define ALI_CSPSR_WRITE_OK	0x01
    231
    232/* interrupts for the whole chip by interrupt status register finish */
    233 
    234#define ALI_INT_MICIN2		(1<<26)
    235#define ALI_INT_PCMIN2		(1<<25)
    236#define ALI_INT_I2SIN		(1<<24)
    237#define ALI_INT_SPDIFOUT	(1<<23)	/* controller spdif out INTERRUPT */
    238#define ALI_INT_SPDIFIN		(1<<22)
    239#define ALI_INT_LFEOUT		(1<<21)
    240#define ALI_INT_CENTEROUT	(1<<20)
    241#define ALI_INT_CODECSPDIFOUT	(1<<19)
    242#define ALI_INT_MICIN		(1<<18)
    243#define ALI_INT_PCMOUT		(1<<17)
    244#define ALI_INT_PCMIN		(1<<16)
    245#define ALI_INT_CPRAIS		(1<<7)	/* command port available */
    246#define ALI_INT_SPRAIS		(1<<5)	/* status port available */
    247#define ALI_INT_GPIO		(1<<1)
    248#define ALI_INT_MASK		(ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
    249				 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
    250
    251#define ICH_ALI_SC_RESET	(1<<31)	/* master reset */
    252#define ICH_ALI_SC_AC97_DBL	(1<<30)
    253#define ICH_ALI_SC_CODEC_SPDF	(3<<20)	/* 1=7/8, 2=6/9, 3=10/11 */
    254#define ICH_ALI_SC_IN_BITS	(3<<18)
    255#define ICH_ALI_SC_OUT_BITS	(3<<16)
    256#define ICH_ALI_SC_6CH_CFG	(3<<14)
    257#define ICH_ALI_SC_PCM_4	(1<<8)
    258#define ICH_ALI_SC_PCM_6	(2<<8)
    259#define ICH_ALI_SC_PCM_246_MASK	(3<<8)
    260
    261#define ICH_ALI_SS_SEC_ID	(3<<5)
    262#define ICH_ALI_SS_PRI_ID	(3<<3)
    263
    264#define ICH_ALI_IF_AC97SP	(1<<21)
    265#define ICH_ALI_IF_MC		(1<<20)
    266#define ICH_ALI_IF_PI		(1<<19)
    267#define ICH_ALI_IF_MC2		(1<<18)
    268#define ICH_ALI_IF_PI2		(1<<17)
    269#define ICH_ALI_IF_LINE_SRC	(1<<15)	/* 0/1 = slot 3/6 */
    270#define ICH_ALI_IF_MIC_SRC	(1<<14)	/* 0/1 = slot 3/6 */
    271#define ICH_ALI_IF_SPDF_SRC	(3<<12)	/* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
    272#define ICH_ALI_IF_AC97_OUT	(3<<8)	/* 00 = PCM, 10 = spdif-in, 11 = i2s */
    273#define ICH_ALI_IF_PO_SPDF	(1<<3)
    274#define ICH_ALI_IF_PO		(1<<1)
    275
    276/*
    277 *  
    278 */
    279
    280enum {
    281	ICHD_PCMIN,
    282	ICHD_PCMOUT,
    283	ICHD_MIC,
    284	ICHD_MIC2,
    285	ICHD_PCM2IN,
    286	ICHD_SPBAR,
    287	ICHD_LAST = ICHD_SPBAR
    288};
    289enum {
    290	NVD_PCMIN,
    291	NVD_PCMOUT,
    292	NVD_MIC,
    293	NVD_SPBAR,
    294	NVD_LAST = NVD_SPBAR
    295};
    296enum {
    297	ALID_PCMIN,
    298	ALID_PCMOUT,
    299	ALID_MIC,
    300	ALID_AC97SPDIFOUT,
    301	ALID_SPDIFIN,
    302	ALID_SPDIFOUT,
    303	ALID_LAST = ALID_SPDIFOUT
    304};
    305
    306#define get_ichdev(substream) (substream->runtime->private_data)
    307
    308struct ichdev {
    309	unsigned int ichd;			/* ich device number */
    310	unsigned long reg_offset;		/* offset to bmaddr */
    311	__le32 *bdbar;				/* CPU address (32bit) */
    312	unsigned int bdbar_addr;		/* PCI bus address (32bit) */
    313	struct snd_pcm_substream *substream;
    314	unsigned int physbuf;			/* physical address (32bit) */
    315        unsigned int size;
    316        unsigned int fragsize;
    317        unsigned int fragsize1;
    318        unsigned int position;
    319	unsigned int pos_shift;
    320	unsigned int last_pos;
    321        int frags;
    322        int lvi;
    323        int lvi_frag;
    324	int civ;
    325	int ack;
    326	int ack_reload;
    327	unsigned int ack_bit;
    328	unsigned int roff_sr;
    329	unsigned int roff_picb;
    330	unsigned int int_sta_mask;		/* interrupt status mask */
    331	unsigned int ali_slot;			/* ALI DMA slot */
    332	struct ac97_pcm *pcm;
    333	int pcm_open_flag;
    334	unsigned int prepared:1;
    335	unsigned int suspended: 1;
    336};
    337
    338struct intel8x0 {
    339	unsigned int device_type;
    340
    341	int irq;
    342
    343	void __iomem *addr;
    344	void __iomem *bmaddr;
    345
    346	struct pci_dev *pci;
    347	struct snd_card *card;
    348
    349	int pcm_devs;
    350	struct snd_pcm *pcm[6];
    351	struct ichdev ichd[6];
    352
    353	unsigned multi4: 1,
    354		 multi6: 1,
    355		 multi8 :1,
    356		 dra: 1,
    357		 smp20bit: 1;
    358	unsigned in_ac97_init: 1,
    359		 in_sdin_init: 1;
    360	unsigned in_measurement: 1;	/* during ac97 clock measurement */
    361	unsigned fix_nocache: 1; 	/* workaround for 440MX */
    362	unsigned buggy_irq: 1;		/* workaround for buggy mobos */
    363	unsigned xbox: 1;		/* workaround for Xbox AC'97 detection */
    364	unsigned buggy_semaphore: 1;	/* workaround for buggy codec semaphore */
    365	unsigned inside_vm: 1;		/* enable VM optimization */
    366
    367	int spdif_idx;	/* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
    368	unsigned int sdm_saved;	/* SDM reg value */
    369
    370	struct snd_ac97_bus *ac97_bus;
    371	struct snd_ac97 *ac97[3];
    372	unsigned int ac97_sdin[3];
    373	unsigned int max_codecs, ncodecs;
    374	const unsigned int *codec_bit;
    375	unsigned int codec_isr_bits;
    376	unsigned int codec_ready_bits;
    377
    378	spinlock_t reg_lock;
    379	
    380	u32 bdbars_count;
    381	struct snd_dma_buffer *bdbars;
    382	u32 int_sta_reg;		/* interrupt status register */
    383	u32 int_sta_mask;		/* interrupt status mask */
    384};
    385
    386static const struct pci_device_id snd_intel8x0_ids[] = {
    387	{ PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },	/* 82801AA */
    388	{ PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },	/* 82901AB */
    389	{ PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },	/* 82801BA */
    390	{ PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },	/* ICH3 */
    391	{ PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
    392	{ PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
    393	{ PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
    394	{ PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
    395	{ PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
    396	{ PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
    397	{ PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },	/* 440MX */
    398	{ PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },	/* SI7012 */
    399	{ PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE },	/* NFORCE */
    400	{ PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE },	/* MCP04 */
    401	{ PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE },	/* NFORCE2 */
    402	{ PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE },	/* CK804 */
    403	{ PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE },	/* CK8 */
    404	{ PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE },	/* NFORCE3 */
    405	{ PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE },	/* CK8S */
    406	{ PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE },	/* MCP51 */
    407	{ PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },	/* AMD8111 */
    408	{ PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },	/* AMD768 */
    409	{ PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
    410	{ 0, }
    411};
    412
    413MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
    414
    415/*
    416 *  Lowlevel I/O - busmaster
    417 */
    418
    419static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
    420{
    421	return ioread8(chip->bmaddr + offset);
    422}
    423
    424static inline u16 igetword(struct intel8x0 *chip, u32 offset)
    425{
    426	return ioread16(chip->bmaddr + offset);
    427}
    428
    429static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
    430{
    431	return ioread32(chip->bmaddr + offset);
    432}
    433
    434static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
    435{
    436	iowrite8(val, chip->bmaddr + offset);
    437}
    438
    439static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
    440{
    441	iowrite16(val, chip->bmaddr + offset);
    442}
    443
    444static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
    445{
    446	iowrite32(val, chip->bmaddr + offset);
    447}
    448
    449/*
    450 *  Lowlevel I/O - AC'97 registers
    451 */
    452
    453static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
    454{
    455	return ioread16(chip->addr + offset);
    456}
    457
    458static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
    459{
    460	iowrite16(val, chip->addr + offset);
    461}
    462
    463/*
    464 *  Basic I/O
    465 */
    466
    467/*
    468 * access to AC97 codec via normal i/o (for ICH and SIS7012)
    469 */
    470
    471static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
    472{
    473	int time;
    474	
    475	if (codec > 2)
    476		return -EIO;
    477	if (chip->in_sdin_init) {
    478		/* we don't know the ready bit assignment at the moment */
    479		/* so we check any */
    480		codec = chip->codec_isr_bits;
    481	} else {
    482		codec = chip->codec_bit[chip->ac97_sdin[codec]];
    483	}
    484
    485	/* codec ready ? */
    486	if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
    487		return -EIO;
    488
    489	if (chip->buggy_semaphore)
    490		return 0; /* just ignore ... */
    491
    492	/* Anyone holding a semaphore for 1 msec should be shot... */
    493	time = 100;
    494      	do {
    495      		if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
    496      			return 0;
    497		udelay(10);
    498	} while (time--);
    499
    500	/* access to some forbidden (non existent) ac97 registers will not
    501	 * reset the semaphore. So even if you don't get the semaphore, still
    502	 * continue the access. We don't need the semaphore anyway. */
    503	dev_err(chip->card->dev,
    504		"codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
    505			igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
    506	iagetword(chip, 0);	/* clear semaphore flag */
    507	/* I don't care about the semaphore */
    508	return -EBUSY;
    509}
    510 
    511static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
    512				     unsigned short reg,
    513				     unsigned short val)
    514{
    515	struct intel8x0 *chip = ac97->private_data;
    516	
    517	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
    518		if (! chip->in_ac97_init)
    519			dev_err(chip->card->dev,
    520				"codec_write %d: semaphore is not ready for register 0x%x\n",
    521				ac97->num, reg);
    522	}
    523	iaputword(chip, reg + ac97->num * 0x80, val);
    524}
    525
    526static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
    527					      unsigned short reg)
    528{
    529	struct intel8x0 *chip = ac97->private_data;
    530	unsigned short res;
    531	unsigned int tmp;
    532
    533	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
    534		if (! chip->in_ac97_init)
    535			dev_err(chip->card->dev,
    536				"codec_read %d: semaphore is not ready for register 0x%x\n",
    537				ac97->num, reg);
    538		res = 0xffff;
    539	} else {
    540		res = iagetword(chip, reg + ac97->num * 0x80);
    541		tmp = igetdword(chip, ICHREG(GLOB_STA));
    542		if (tmp & ICH_RCS) {
    543			/* reset RCS and preserve other R/WC bits */
    544			iputdword(chip, ICHREG(GLOB_STA), tmp &
    545				  ~(chip->codec_ready_bits | ICH_GSCI));
    546			if (! chip->in_ac97_init)
    547				dev_err(chip->card->dev,
    548					"codec_read %d: read timeout for register 0x%x\n",
    549					ac97->num, reg);
    550			res = 0xffff;
    551		}
    552	}
    553	return res;
    554}
    555
    556static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
    557					 unsigned int codec)
    558{
    559	unsigned int tmp;
    560
    561	if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
    562		iagetword(chip, codec * 0x80);
    563		tmp = igetdword(chip, ICHREG(GLOB_STA));
    564		if (tmp & ICH_RCS) {
    565			/* reset RCS and preserve other R/WC bits */
    566			iputdword(chip, ICHREG(GLOB_STA), tmp &
    567				  ~(chip->codec_ready_bits | ICH_GSCI));
    568		}
    569	}
    570}
    571
    572/*
    573 * access to AC97 for Ali5455
    574 */
    575static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
    576{
    577	int count = 0;
    578	for (count = 0; count < 0x7f; count++) {
    579		int val = igetbyte(chip, ICHREG(ALI_CSPSR));
    580		if (val & mask)
    581			return 0;
    582	}
    583	if (! chip->in_ac97_init)
    584		dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
    585	return -EBUSY;
    586}
    587
    588static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
    589{
    590	int time = 100;
    591	if (chip->buggy_semaphore)
    592		return 0; /* just ignore ... */
    593	while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
    594		udelay(1);
    595	if (! time && ! chip->in_ac97_init)
    596		dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
    597	return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
    598}
    599
    600static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
    601{
    602	struct intel8x0 *chip = ac97->private_data;
    603	unsigned short data = 0xffff;
    604
    605	if (snd_intel8x0_ali_codec_semaphore(chip))
    606		goto __err;
    607	reg |= ALI_CPR_ADDR_READ;
    608	if (ac97->num)
    609		reg |= ALI_CPR_ADDR_SECONDARY;
    610	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
    611	if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
    612		goto __err;
    613	data = igetword(chip, ICHREG(ALI_SPR));
    614 __err:
    615	return data;
    616}
    617
    618static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
    619					 unsigned short val)
    620{
    621	struct intel8x0 *chip = ac97->private_data;
    622
    623	if (snd_intel8x0_ali_codec_semaphore(chip))
    624		return;
    625	iputword(chip, ICHREG(ALI_CPR), val);
    626	if (ac97->num)
    627		reg |= ALI_CPR_ADDR_SECONDARY;
    628	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
    629	snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
    630}
    631
    632
    633/*
    634 * DMA I/O
    635 */
    636static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
    637{
    638	int idx;
    639	__le32 *bdbar = ichdev->bdbar;
    640	unsigned long port = ichdev->reg_offset;
    641
    642	iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
    643	if (ichdev->size == ichdev->fragsize) {
    644		ichdev->ack_reload = ichdev->ack = 2;
    645		ichdev->fragsize1 = ichdev->fragsize >> 1;
    646		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
    647			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
    648			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
    649						     ichdev->fragsize1 >> ichdev->pos_shift);
    650			bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
    651			bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
    652						     ichdev->fragsize1 >> ichdev->pos_shift);
    653		}
    654		ichdev->frags = 2;
    655	} else {
    656		ichdev->ack_reload = ichdev->ack = 1;
    657		ichdev->fragsize1 = ichdev->fragsize;
    658		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
    659			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
    660						     (((idx >> 1) * ichdev->fragsize) %
    661						      ichdev->size));
    662			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
    663						     ichdev->fragsize >> ichdev->pos_shift);
    664#if 0
    665			dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
    666			       idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
    667#endif
    668		}
    669		ichdev->frags = ichdev->size / ichdev->fragsize;
    670	}
    671	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
    672	ichdev->civ = 0;
    673	iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
    674	ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
    675	ichdev->position = 0;
    676#if 0
    677	dev_dbg(chip->card->dev,
    678		"lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
    679	       ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
    680	       ichdev->fragsize1);
    681#endif
    682	/* clear interrupts */
    683	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
    684}
    685
    686/*
    687 *  Interrupt handler
    688 */
    689
    690static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
    691{
    692	unsigned long port = ichdev->reg_offset;
    693	unsigned long flags;
    694	int status, civ, i, step;
    695	int ack = 0;
    696
    697	if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
    698		return;
    699
    700	spin_lock_irqsave(&chip->reg_lock, flags);
    701	status = igetbyte(chip, port + ichdev->roff_sr);
    702	civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
    703	if (!(status & ICH_BCIS)) {
    704		step = 0;
    705	} else if (civ == ichdev->civ) {
    706		// snd_printd("civ same %d\n", civ);
    707		step = 1;
    708		ichdev->civ++;
    709		ichdev->civ &= ICH_REG_LVI_MASK;
    710	} else {
    711		step = civ - ichdev->civ;
    712		if (step < 0)
    713			step += ICH_REG_LVI_MASK + 1;
    714		// if (step != 1)
    715		//	snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
    716		ichdev->civ = civ;
    717	}
    718
    719	ichdev->position += step * ichdev->fragsize1;
    720	if (! chip->in_measurement)
    721		ichdev->position %= ichdev->size;
    722	ichdev->lvi += step;
    723	ichdev->lvi &= ICH_REG_LVI_MASK;
    724	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
    725	for (i = 0; i < step; i++) {
    726		ichdev->lvi_frag++;
    727		ichdev->lvi_frag %= ichdev->frags;
    728		ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
    729#if 0
    730	dev_dbg(chip->card->dev,
    731		"new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
    732	       ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
    733	       ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
    734	       inl(port + 4), inb(port + ICH_REG_OFF_CR));
    735#endif
    736		if (--ichdev->ack == 0) {
    737			ichdev->ack = ichdev->ack_reload;
    738			ack = 1;
    739		}
    740	}
    741	spin_unlock_irqrestore(&chip->reg_lock, flags);
    742	if (ack && ichdev->substream) {
    743		snd_pcm_period_elapsed(ichdev->substream);
    744	}
    745	iputbyte(chip, port + ichdev->roff_sr,
    746		 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
    747}
    748
    749static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
    750{
    751	struct intel8x0 *chip = dev_id;
    752	struct ichdev *ichdev;
    753	unsigned int status;
    754	unsigned int i;
    755
    756	status = igetdword(chip, chip->int_sta_reg);
    757	if (status == 0xffffffff)	/* we are not yet resumed */
    758		return IRQ_NONE;
    759
    760	if ((status & chip->int_sta_mask) == 0) {
    761		if (status) {
    762			/* ack */
    763			iputdword(chip, chip->int_sta_reg, status);
    764			if (! chip->buggy_irq)
    765				status = 0;
    766		}
    767		return IRQ_RETVAL(status);
    768	}
    769
    770	for (i = 0; i < chip->bdbars_count; i++) {
    771		ichdev = &chip->ichd[i];
    772		if (status & ichdev->int_sta_mask)
    773			snd_intel8x0_update(chip, ichdev);
    774	}
    775
    776	/* ack them */
    777	iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
    778	
    779	return IRQ_HANDLED;
    780}
    781
    782/*
    783 *  PCM part
    784 */
    785
    786static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
    787{
    788	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
    789	struct ichdev *ichdev = get_ichdev(substream);
    790	unsigned char val = 0;
    791	unsigned long port = ichdev->reg_offset;
    792
    793	switch (cmd) {
    794	case SNDRV_PCM_TRIGGER_RESUME:
    795		ichdev->suspended = 0;
    796		fallthrough;
    797	case SNDRV_PCM_TRIGGER_START:
    798	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
    799		val = ICH_IOCE | ICH_STARTBM;
    800		ichdev->last_pos = ichdev->position;
    801		break;
    802	case SNDRV_PCM_TRIGGER_SUSPEND:
    803		ichdev->suspended = 1;
    804		fallthrough;
    805	case SNDRV_PCM_TRIGGER_STOP:
    806		val = 0;
    807		break;
    808	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
    809		val = ICH_IOCE;
    810		break;
    811	default:
    812		return -EINVAL;
    813	}
    814	iputbyte(chip, port + ICH_REG_OFF_CR, val);
    815	if (cmd == SNDRV_PCM_TRIGGER_STOP) {
    816		/* wait until DMA stopped */
    817		while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
    818		/* reset whole DMA things */
    819		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
    820	}
    821	return 0;
    822}
    823
    824static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
    825{
    826	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
    827	struct ichdev *ichdev = get_ichdev(substream);
    828	unsigned long port = ichdev->reg_offset;
    829	static const int fiforeg[] = {
    830		ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
    831	};
    832	unsigned int val, fifo;
    833
    834	val = igetdword(chip, ICHREG(ALI_DMACR));
    835	switch (cmd) {
    836	case SNDRV_PCM_TRIGGER_RESUME:
    837		ichdev->suspended = 0;
    838		fallthrough;
    839	case SNDRV_PCM_TRIGGER_START:
    840	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
    841		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
    842			/* clear FIFO for synchronization of channels */
    843			fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
    844			fifo &= ~(0xff << (ichdev->ali_slot % 4));  
    845			fifo |= 0x83 << (ichdev->ali_slot % 4); 
    846			iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
    847		}
    848		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
    849		val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
    850		/* start DMA */
    851		iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
    852		break;
    853	case SNDRV_PCM_TRIGGER_SUSPEND:
    854		ichdev->suspended = 1;
    855		fallthrough;
    856	case SNDRV_PCM_TRIGGER_STOP:
    857	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
    858		/* pause */
    859		iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
    860		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
    861		while (igetbyte(chip, port + ICH_REG_OFF_CR))
    862			;
    863		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
    864			break;
    865		/* reset whole DMA things */
    866		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
    867		/* clear interrupts */
    868		iputbyte(chip, port + ICH_REG_OFF_SR,
    869			 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
    870		iputdword(chip, ICHREG(ALI_INTERRUPTSR),
    871			  igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
    872		break;
    873	default:
    874		return -EINVAL;
    875	}
    876	return 0;
    877}
    878
    879static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
    880				  struct snd_pcm_hw_params *hw_params)
    881{
    882	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
    883	struct ichdev *ichdev = get_ichdev(substream);
    884	int dbl = params_rate(hw_params) > 48000;
    885	int err;
    886
    887	if (ichdev->pcm_open_flag) {
    888		snd_ac97_pcm_close(ichdev->pcm);
    889		ichdev->pcm_open_flag = 0;
    890		ichdev->prepared = 0;
    891	}
    892	err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
    893				params_channels(hw_params),
    894				ichdev->pcm->r[dbl].slots);
    895	if (err >= 0) {
    896		ichdev->pcm_open_flag = 1;
    897		/* Force SPDIF setting */
    898		if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
    899			snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
    900					  params_rate(hw_params));
    901	}
    902	return err;
    903}
    904
    905static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
    906{
    907	struct ichdev *ichdev = get_ichdev(substream);
    908
    909	if (ichdev->pcm_open_flag) {
    910		snd_ac97_pcm_close(ichdev->pcm);
    911		ichdev->pcm_open_flag = 0;
    912		ichdev->prepared = 0;
    913	}
    914	return 0;
    915}
    916
    917static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
    918				       struct snd_pcm_runtime *runtime)
    919{
    920	unsigned int cnt;
    921	int dbl = runtime->rate > 48000;
    922
    923	spin_lock_irq(&chip->reg_lock);
    924	switch (chip->device_type) {
    925	case DEVICE_ALI:
    926		cnt = igetdword(chip, ICHREG(ALI_SCR));
    927		cnt &= ~ICH_ALI_SC_PCM_246_MASK;
    928		if (runtime->channels == 4 || dbl)
    929			cnt |= ICH_ALI_SC_PCM_4;
    930		else if (runtime->channels == 6)
    931			cnt |= ICH_ALI_SC_PCM_6;
    932		iputdword(chip, ICHREG(ALI_SCR), cnt);
    933		break;
    934	case DEVICE_SIS:
    935		cnt = igetdword(chip, ICHREG(GLOB_CNT));
    936		cnt &= ~ICH_SIS_PCM_246_MASK;
    937		if (runtime->channels == 4 || dbl)
    938			cnt |= ICH_SIS_PCM_4;
    939		else if (runtime->channels == 6)
    940			cnt |= ICH_SIS_PCM_6;
    941		iputdword(chip, ICHREG(GLOB_CNT), cnt);
    942		break;
    943	default:
    944		cnt = igetdword(chip, ICHREG(GLOB_CNT));
    945		cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
    946		if (runtime->channels == 4 || dbl)
    947			cnt |= ICH_PCM_4;
    948		else if (runtime->channels == 6)
    949			cnt |= ICH_PCM_6;
    950		else if (runtime->channels == 8)
    951			cnt |= ICH_PCM_8;
    952		if (chip->device_type == DEVICE_NFORCE) {
    953			/* reset to 2ch once to keep the 6 channel data in alignment,
    954			 * to start from Front Left always
    955			 */
    956			if (cnt & ICH_PCM_246_MASK) {
    957				iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
    958				spin_unlock_irq(&chip->reg_lock);
    959				msleep(50); /* grrr... */
    960				spin_lock_irq(&chip->reg_lock);
    961			}
    962		} else if (chip->device_type == DEVICE_INTEL_ICH4) {
    963			if (runtime->sample_bits > 16)
    964				cnt |= ICH_PCM_20BIT;
    965		}
    966		iputdword(chip, ICHREG(GLOB_CNT), cnt);
    967		break;
    968	}
    969	spin_unlock_irq(&chip->reg_lock);
    970}
    971
    972static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
    973{
    974	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
    975	struct snd_pcm_runtime *runtime = substream->runtime;
    976	struct ichdev *ichdev = get_ichdev(substream);
    977
    978	ichdev->physbuf = runtime->dma_addr;
    979	ichdev->size = snd_pcm_lib_buffer_bytes(substream);
    980	ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
    981	if (ichdev->ichd == ICHD_PCMOUT) {
    982		snd_intel8x0_setup_pcm_out(chip, runtime);
    983		if (chip->device_type == DEVICE_INTEL_ICH4)
    984			ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
    985	}
    986	snd_intel8x0_setup_periods(chip, ichdev);
    987	ichdev->prepared = 1;
    988	return 0;
    989}
    990
    991static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
    992{
    993	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
    994	struct ichdev *ichdev = get_ichdev(substream);
    995	size_t ptr1, ptr;
    996	int civ, timeout = 10;
    997	unsigned int position;
    998
    999	spin_lock(&chip->reg_lock);
   1000	do {
   1001		civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
   1002		ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
   1003		position = ichdev->position;
   1004		if (ptr1 == 0) {
   1005			udelay(10);
   1006			continue;
   1007		}
   1008		if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
   1009			continue;
   1010
   1011		/* IO read operation is very expensive inside virtual machine
   1012		 * as it is emulated. The probability that subsequent PICB read
   1013		 * will return different result is high enough to loop till
   1014		 * timeout here.
   1015		 * Same CIV is strict enough condition to be sure that PICB
   1016		 * is valid inside VM on emulated card. */
   1017		if (chip->inside_vm)
   1018			break;
   1019		if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
   1020			break;
   1021	} while (timeout--);
   1022	ptr = ichdev->last_pos;
   1023	if (ptr1 != 0) {
   1024		ptr1 <<= ichdev->pos_shift;
   1025		ptr = ichdev->fragsize1 - ptr1;
   1026		ptr += position;
   1027		if (ptr < ichdev->last_pos) {
   1028			unsigned int pos_base, last_base;
   1029			pos_base = position / ichdev->fragsize1;
   1030			last_base = ichdev->last_pos / ichdev->fragsize1;
   1031			/* another sanity check; ptr1 can go back to full
   1032			 * before the base position is updated
   1033			 */
   1034			if (pos_base == last_base)
   1035				ptr = ichdev->last_pos;
   1036		}
   1037	}
   1038	ichdev->last_pos = ptr;
   1039	spin_unlock(&chip->reg_lock);
   1040	if (ptr >= ichdev->size)
   1041		return 0;
   1042	return bytes_to_frames(substream->runtime, ptr);
   1043}
   1044
   1045static const struct snd_pcm_hardware snd_intel8x0_stream =
   1046{
   1047	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
   1048				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
   1049				 SNDRV_PCM_INFO_MMAP_VALID |
   1050				 SNDRV_PCM_INFO_PAUSE |
   1051				 SNDRV_PCM_INFO_RESUME),
   1052	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
   1053	.rates =		SNDRV_PCM_RATE_48000,
   1054	.rate_min =		48000,
   1055	.rate_max =		48000,
   1056	.channels_min =		2,
   1057	.channels_max =		2,
   1058	.buffer_bytes_max =	128 * 1024,
   1059	.period_bytes_min =	32,
   1060	.period_bytes_max =	128 * 1024,
   1061	.periods_min =		1,
   1062	.periods_max =		1024,
   1063	.fifo_size =		0,
   1064};
   1065
   1066static const unsigned int channels4[] = {
   1067	2, 4,
   1068};
   1069
   1070static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
   1071	.count = ARRAY_SIZE(channels4),
   1072	.list = channels4,
   1073	.mask = 0,
   1074};
   1075
   1076static const unsigned int channels6[] = {
   1077	2, 4, 6,
   1078};
   1079
   1080static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
   1081	.count = ARRAY_SIZE(channels6),
   1082	.list = channels6,
   1083	.mask = 0,
   1084};
   1085
   1086static const unsigned int channels8[] = {
   1087	2, 4, 6, 8,
   1088};
   1089
   1090static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
   1091	.count = ARRAY_SIZE(channels8),
   1092	.list = channels8,
   1093	.mask = 0,
   1094};
   1095
   1096static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
   1097{
   1098	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1099	struct snd_pcm_runtime *runtime = substream->runtime;
   1100	int err;
   1101
   1102	ichdev->substream = substream;
   1103	runtime->hw = snd_intel8x0_stream;
   1104	runtime->hw.rates = ichdev->pcm->rates;
   1105	snd_pcm_limit_hw_rates(runtime);
   1106	if (chip->device_type == DEVICE_SIS) {
   1107		runtime->hw.buffer_bytes_max = 64*1024;
   1108		runtime->hw.period_bytes_max = 64*1024;
   1109	}
   1110	err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
   1111	if (err < 0)
   1112		return err;
   1113	runtime->private_data = ichdev;
   1114	return 0;
   1115}
   1116
   1117static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
   1118{
   1119	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1120	struct snd_pcm_runtime *runtime = substream->runtime;
   1121	int err;
   1122
   1123	err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
   1124	if (err < 0)
   1125		return err;
   1126
   1127	if (chip->multi8) {
   1128		runtime->hw.channels_max = 8;
   1129		snd_pcm_hw_constraint_list(runtime, 0,
   1130						SNDRV_PCM_HW_PARAM_CHANNELS,
   1131						&hw_constraints_channels8);
   1132	} else if (chip->multi6) {
   1133		runtime->hw.channels_max = 6;
   1134		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
   1135					   &hw_constraints_channels6);
   1136	} else if (chip->multi4) {
   1137		runtime->hw.channels_max = 4;
   1138		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
   1139					   &hw_constraints_channels4);
   1140	}
   1141	if (chip->dra) {
   1142		snd_ac97_pcm_double_rate_rules(runtime);
   1143	}
   1144	if (chip->smp20bit) {
   1145		runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
   1146		snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
   1147	}
   1148	return 0;
   1149}
   1150
   1151static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
   1152{
   1153	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1154
   1155	chip->ichd[ICHD_PCMOUT].substream = NULL;
   1156	return 0;
   1157}
   1158
   1159static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
   1160{
   1161	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1162
   1163	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
   1164}
   1165
   1166static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
   1167{
   1168	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1169
   1170	chip->ichd[ICHD_PCMIN].substream = NULL;
   1171	return 0;
   1172}
   1173
   1174static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
   1175{
   1176	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1177
   1178	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
   1179}
   1180
   1181static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
   1182{
   1183	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1184
   1185	chip->ichd[ICHD_MIC].substream = NULL;
   1186	return 0;
   1187}
   1188
   1189static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
   1190{
   1191	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1192
   1193	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
   1194}
   1195
   1196static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
   1197{
   1198	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1199
   1200	chip->ichd[ICHD_MIC2].substream = NULL;
   1201	return 0;
   1202}
   1203
   1204static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
   1205{
   1206	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1207
   1208	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
   1209}
   1210
   1211static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
   1212{
   1213	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1214
   1215	chip->ichd[ICHD_PCM2IN].substream = NULL;
   1216	return 0;
   1217}
   1218
   1219static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
   1220{
   1221	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1222	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
   1223
   1224	return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
   1225}
   1226
   1227static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
   1228{
   1229	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1230	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
   1231
   1232	chip->ichd[idx].substream = NULL;
   1233	return 0;
   1234}
   1235
   1236static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
   1237{
   1238	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1239	unsigned int val;
   1240
   1241	spin_lock_irq(&chip->reg_lock);
   1242	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
   1243	val |= ICH_ALI_IF_AC97SP;
   1244	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
   1245	/* also needs to set ALI_SC_CODEC_SPDF correctly */
   1246	spin_unlock_irq(&chip->reg_lock);
   1247
   1248	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
   1249}
   1250
   1251static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
   1252{
   1253	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1254	unsigned int val;
   1255
   1256	chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
   1257	spin_lock_irq(&chip->reg_lock);
   1258	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
   1259	val &= ~ICH_ALI_IF_AC97SP;
   1260	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
   1261	spin_unlock_irq(&chip->reg_lock);
   1262
   1263	return 0;
   1264}
   1265
   1266#if 0 // NYI
   1267static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
   1268{
   1269	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1270
   1271	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
   1272}
   1273
   1274static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
   1275{
   1276	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1277
   1278	chip->ichd[ALID_SPDIFIN].substream = NULL;
   1279	return 0;
   1280}
   1281
   1282static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
   1283{
   1284	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1285
   1286	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
   1287}
   1288
   1289static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
   1290{
   1291	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
   1292
   1293	chip->ichd[ALID_SPDIFOUT].substream = NULL;
   1294	return 0;
   1295}
   1296#endif
   1297
   1298static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
   1299	.open =		snd_intel8x0_playback_open,
   1300	.close =	snd_intel8x0_playback_close,
   1301	.hw_params =	snd_intel8x0_hw_params,
   1302	.hw_free =	snd_intel8x0_hw_free,
   1303	.prepare =	snd_intel8x0_pcm_prepare,
   1304	.trigger =	snd_intel8x0_pcm_trigger,
   1305	.pointer =	snd_intel8x0_pcm_pointer,
   1306};
   1307
   1308static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
   1309	.open =		snd_intel8x0_capture_open,
   1310	.close =	snd_intel8x0_capture_close,
   1311	.hw_params =	snd_intel8x0_hw_params,
   1312	.hw_free =	snd_intel8x0_hw_free,
   1313	.prepare =	snd_intel8x0_pcm_prepare,
   1314	.trigger =	snd_intel8x0_pcm_trigger,
   1315	.pointer =	snd_intel8x0_pcm_pointer,
   1316};
   1317
   1318static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
   1319	.open =		snd_intel8x0_mic_open,
   1320	.close =	snd_intel8x0_mic_close,
   1321	.hw_params =	snd_intel8x0_hw_params,
   1322	.hw_free =	snd_intel8x0_hw_free,
   1323	.prepare =	snd_intel8x0_pcm_prepare,
   1324	.trigger =	snd_intel8x0_pcm_trigger,
   1325	.pointer =	snd_intel8x0_pcm_pointer,
   1326};
   1327
   1328static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
   1329	.open =		snd_intel8x0_mic2_open,
   1330	.close =	snd_intel8x0_mic2_close,
   1331	.hw_params =	snd_intel8x0_hw_params,
   1332	.hw_free =	snd_intel8x0_hw_free,
   1333	.prepare =	snd_intel8x0_pcm_prepare,
   1334	.trigger =	snd_intel8x0_pcm_trigger,
   1335	.pointer =	snd_intel8x0_pcm_pointer,
   1336};
   1337
   1338static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
   1339	.open =		snd_intel8x0_capture2_open,
   1340	.close =	snd_intel8x0_capture2_close,
   1341	.hw_params =	snd_intel8x0_hw_params,
   1342	.hw_free =	snd_intel8x0_hw_free,
   1343	.prepare =	snd_intel8x0_pcm_prepare,
   1344	.trigger =	snd_intel8x0_pcm_trigger,
   1345	.pointer =	snd_intel8x0_pcm_pointer,
   1346};
   1347
   1348static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
   1349	.open =		snd_intel8x0_spdif_open,
   1350	.close =	snd_intel8x0_spdif_close,
   1351	.hw_params =	snd_intel8x0_hw_params,
   1352	.hw_free =	snd_intel8x0_hw_free,
   1353	.prepare =	snd_intel8x0_pcm_prepare,
   1354	.trigger =	snd_intel8x0_pcm_trigger,
   1355	.pointer =	snd_intel8x0_pcm_pointer,
   1356};
   1357
   1358static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
   1359	.open =		snd_intel8x0_playback_open,
   1360	.close =	snd_intel8x0_playback_close,
   1361	.hw_params =	snd_intel8x0_hw_params,
   1362	.hw_free =	snd_intel8x0_hw_free,
   1363	.prepare =	snd_intel8x0_pcm_prepare,
   1364	.trigger =	snd_intel8x0_ali_trigger,
   1365	.pointer =	snd_intel8x0_pcm_pointer,
   1366};
   1367
   1368static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
   1369	.open =		snd_intel8x0_capture_open,
   1370	.close =	snd_intel8x0_capture_close,
   1371	.hw_params =	snd_intel8x0_hw_params,
   1372	.hw_free =	snd_intel8x0_hw_free,
   1373	.prepare =	snd_intel8x0_pcm_prepare,
   1374	.trigger =	snd_intel8x0_ali_trigger,
   1375	.pointer =	snd_intel8x0_pcm_pointer,
   1376};
   1377
   1378static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
   1379	.open =		snd_intel8x0_mic_open,
   1380	.close =	snd_intel8x0_mic_close,
   1381	.hw_params =	snd_intel8x0_hw_params,
   1382	.hw_free =	snd_intel8x0_hw_free,
   1383	.prepare =	snd_intel8x0_pcm_prepare,
   1384	.trigger =	snd_intel8x0_ali_trigger,
   1385	.pointer =	snd_intel8x0_pcm_pointer,
   1386};
   1387
   1388static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
   1389	.open =		snd_intel8x0_ali_ac97spdifout_open,
   1390	.close =	snd_intel8x0_ali_ac97spdifout_close,
   1391	.hw_params =	snd_intel8x0_hw_params,
   1392	.hw_free =	snd_intel8x0_hw_free,
   1393	.prepare =	snd_intel8x0_pcm_prepare,
   1394	.trigger =	snd_intel8x0_ali_trigger,
   1395	.pointer =	snd_intel8x0_pcm_pointer,
   1396};
   1397
   1398#if 0 // NYI
   1399static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
   1400	.open =		snd_intel8x0_ali_spdifin_open,
   1401	.close =	snd_intel8x0_ali_spdifin_close,
   1402	.hw_params =	snd_intel8x0_hw_params,
   1403	.hw_free =	snd_intel8x0_hw_free,
   1404	.prepare =	snd_intel8x0_pcm_prepare,
   1405	.trigger =	snd_intel8x0_pcm_trigger,
   1406	.pointer =	snd_intel8x0_pcm_pointer,
   1407};
   1408
   1409static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
   1410	.open =		snd_intel8x0_ali_spdifout_open,
   1411	.close =	snd_intel8x0_ali_spdifout_close,
   1412	.hw_params =	snd_intel8x0_hw_params,
   1413	.hw_free =	snd_intel8x0_hw_free,
   1414	.prepare =	snd_intel8x0_pcm_prepare,
   1415	.trigger =	snd_intel8x0_pcm_trigger,
   1416	.pointer =	snd_intel8x0_pcm_pointer,
   1417};
   1418#endif // NYI
   1419
   1420struct ich_pcm_table {
   1421	char *suffix;
   1422	const struct snd_pcm_ops *playback_ops;
   1423	const struct snd_pcm_ops *capture_ops;
   1424	size_t prealloc_size;
   1425	size_t prealloc_max_size;
   1426	int ac97_idx;
   1427};
   1428
   1429#define intel8x0_dma_type(chip) \
   1430	((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_WC : SNDRV_DMA_TYPE_DEV)
   1431
   1432static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
   1433			     const struct ich_pcm_table *rec)
   1434{
   1435	struct snd_pcm *pcm;
   1436	int err;
   1437	char name[32];
   1438
   1439	if (rec->suffix)
   1440		sprintf(name, "Intel ICH - %s", rec->suffix);
   1441	else
   1442		strcpy(name, "Intel ICH");
   1443	err = snd_pcm_new(chip->card, name, device,
   1444			  rec->playback_ops ? 1 : 0,
   1445			  rec->capture_ops ? 1 : 0, &pcm);
   1446	if (err < 0)
   1447		return err;
   1448
   1449	if (rec->playback_ops)
   1450		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
   1451	if (rec->capture_ops)
   1452		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
   1453
   1454	pcm->private_data = chip;
   1455	pcm->info_flags = 0;
   1456	if (rec->suffix)
   1457		sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
   1458	else
   1459		strcpy(pcm->name, chip->card->shortname);
   1460	chip->pcm[device] = pcm;
   1461
   1462	snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
   1463				       &chip->pci->dev,
   1464				       rec->prealloc_size, rec->prealloc_max_size);
   1465
   1466	if (rec->playback_ops &&
   1467	    rec->playback_ops->open == snd_intel8x0_playback_open) {
   1468		struct snd_pcm_chmap *chmap;
   1469		int chs = 2;
   1470		if (chip->multi8)
   1471			chs = 8;
   1472		else if (chip->multi6)
   1473			chs = 6;
   1474		else if (chip->multi4)
   1475			chs = 4;
   1476		err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
   1477					     snd_pcm_alt_chmaps, chs, 0,
   1478					     &chmap);
   1479		if (err < 0)
   1480			return err;
   1481		chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
   1482		chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
   1483	}
   1484
   1485	return 0;
   1486}
   1487
   1488static const struct ich_pcm_table intel_pcms[] = {
   1489	{
   1490		.playback_ops = &snd_intel8x0_playback_ops,
   1491		.capture_ops = &snd_intel8x0_capture_ops,
   1492		.prealloc_size = 64 * 1024,
   1493		.prealloc_max_size = 128 * 1024,
   1494	},
   1495	{
   1496		.suffix = "MIC ADC",
   1497		.capture_ops = &snd_intel8x0_capture_mic_ops,
   1498		.prealloc_size = 0,
   1499		.prealloc_max_size = 128 * 1024,
   1500		.ac97_idx = ICHD_MIC,
   1501	},
   1502	{
   1503		.suffix = "MIC2 ADC",
   1504		.capture_ops = &snd_intel8x0_capture_mic2_ops,
   1505		.prealloc_size = 0,
   1506		.prealloc_max_size = 128 * 1024,
   1507		.ac97_idx = ICHD_MIC2,
   1508	},
   1509	{
   1510		.suffix = "ADC2",
   1511		.capture_ops = &snd_intel8x0_capture2_ops,
   1512		.prealloc_size = 0,
   1513		.prealloc_max_size = 128 * 1024,
   1514		.ac97_idx = ICHD_PCM2IN,
   1515	},
   1516	{
   1517		.suffix = "IEC958",
   1518		.playback_ops = &snd_intel8x0_spdif_ops,
   1519		.prealloc_size = 64 * 1024,
   1520		.prealloc_max_size = 128 * 1024,
   1521		.ac97_idx = ICHD_SPBAR,
   1522	},
   1523};
   1524
   1525static const struct ich_pcm_table nforce_pcms[] = {
   1526	{
   1527		.playback_ops = &snd_intel8x0_playback_ops,
   1528		.capture_ops = &snd_intel8x0_capture_ops,
   1529		.prealloc_size = 64 * 1024,
   1530		.prealloc_max_size = 128 * 1024,
   1531	},
   1532	{
   1533		.suffix = "MIC ADC",
   1534		.capture_ops = &snd_intel8x0_capture_mic_ops,
   1535		.prealloc_size = 0,
   1536		.prealloc_max_size = 128 * 1024,
   1537		.ac97_idx = NVD_MIC,
   1538	},
   1539	{
   1540		.suffix = "IEC958",
   1541		.playback_ops = &snd_intel8x0_spdif_ops,
   1542		.prealloc_size = 64 * 1024,
   1543		.prealloc_max_size = 128 * 1024,
   1544		.ac97_idx = NVD_SPBAR,
   1545	},
   1546};
   1547
   1548static const struct ich_pcm_table ali_pcms[] = {
   1549	{
   1550		.playback_ops = &snd_intel8x0_ali_playback_ops,
   1551		.capture_ops = &snd_intel8x0_ali_capture_ops,
   1552		.prealloc_size = 64 * 1024,
   1553		.prealloc_max_size = 128 * 1024,
   1554	},
   1555	{
   1556		.suffix = "MIC ADC",
   1557		.capture_ops = &snd_intel8x0_ali_capture_mic_ops,
   1558		.prealloc_size = 0,
   1559		.prealloc_max_size = 128 * 1024,
   1560		.ac97_idx = ALID_MIC,
   1561	},
   1562	{
   1563		.suffix = "IEC958",
   1564		.playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
   1565		/* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
   1566		.prealloc_size = 64 * 1024,
   1567		.prealloc_max_size = 128 * 1024,
   1568		.ac97_idx = ALID_AC97SPDIFOUT,
   1569	},
   1570#if 0 // NYI
   1571	{
   1572		.suffix = "HW IEC958",
   1573		.playback_ops = &snd_intel8x0_ali_spdifout_ops,
   1574		.prealloc_size = 64 * 1024,
   1575		.prealloc_max_size = 128 * 1024,
   1576	},
   1577#endif
   1578};
   1579
   1580static int snd_intel8x0_pcm(struct intel8x0 *chip)
   1581{
   1582	int i, tblsize, device, err;
   1583	const struct ich_pcm_table *tbl, *rec;
   1584
   1585	switch (chip->device_type) {
   1586	case DEVICE_INTEL_ICH4:
   1587		tbl = intel_pcms;
   1588		tblsize = ARRAY_SIZE(intel_pcms);
   1589		if (spdif_aclink)
   1590			tblsize--;
   1591		break;
   1592	case DEVICE_NFORCE:
   1593		tbl = nforce_pcms;
   1594		tblsize = ARRAY_SIZE(nforce_pcms);
   1595		if (spdif_aclink)
   1596			tblsize--;
   1597		break;
   1598	case DEVICE_ALI:
   1599		tbl = ali_pcms;
   1600		tblsize = ARRAY_SIZE(ali_pcms);
   1601		break;
   1602	default:
   1603		tbl = intel_pcms;
   1604		tblsize = 2;
   1605		break;
   1606	}
   1607
   1608	device = 0;
   1609	for (i = 0; i < tblsize; i++) {
   1610		rec = tbl + i;
   1611		if (i > 0 && rec->ac97_idx) {
   1612			/* activate PCM only when associated AC'97 codec */
   1613			if (! chip->ichd[rec->ac97_idx].pcm)
   1614				continue;
   1615		}
   1616		err = snd_intel8x0_pcm1(chip, device, rec);
   1617		if (err < 0)
   1618			return err;
   1619		device++;
   1620	}
   1621
   1622	chip->pcm_devs = device;
   1623	return 0;
   1624}
   1625	
   1626
   1627/*
   1628 *  Mixer part
   1629 */
   1630
   1631static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
   1632{
   1633	struct intel8x0 *chip = bus->private_data;
   1634	chip->ac97_bus = NULL;
   1635}
   1636
   1637static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
   1638{
   1639	struct intel8x0 *chip = ac97->private_data;
   1640	chip->ac97[ac97->num] = NULL;
   1641}
   1642
   1643static const struct ac97_pcm ac97_pcm_defs[] = {
   1644	/* front PCM */
   1645	{
   1646		.exclusive = 1,
   1647		.r = {	{
   1648				.slots = (1 << AC97_SLOT_PCM_LEFT) |
   1649					 (1 << AC97_SLOT_PCM_RIGHT) |
   1650					 (1 << AC97_SLOT_PCM_CENTER) |
   1651					 (1 << AC97_SLOT_PCM_SLEFT) |
   1652					 (1 << AC97_SLOT_PCM_SRIGHT) |
   1653					 (1 << AC97_SLOT_LFE)
   1654			},
   1655			{
   1656				.slots = (1 << AC97_SLOT_PCM_LEFT) |
   1657					 (1 << AC97_SLOT_PCM_RIGHT) |
   1658					 (1 << AC97_SLOT_PCM_LEFT_0) |
   1659					 (1 << AC97_SLOT_PCM_RIGHT_0)
   1660			}
   1661		}
   1662	},
   1663	/* PCM IN #1 */
   1664	{
   1665		.stream = 1,
   1666		.exclusive = 1,
   1667		.r = {	{
   1668				.slots = (1 << AC97_SLOT_PCM_LEFT) |
   1669					 (1 << AC97_SLOT_PCM_RIGHT)
   1670			}
   1671		}
   1672	},
   1673	/* MIC IN #1 */
   1674	{
   1675		.stream = 1,
   1676		.exclusive = 1,
   1677		.r = {	{
   1678				.slots = (1 << AC97_SLOT_MIC)
   1679			}
   1680		}
   1681	},
   1682	/* S/PDIF PCM */
   1683	{
   1684		.exclusive = 1,
   1685		.spdif = 1,
   1686		.r = {	{
   1687				.slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
   1688					 (1 << AC97_SLOT_SPDIF_RIGHT2)
   1689			}
   1690		}
   1691	},
   1692	/* PCM IN #2 */
   1693	{
   1694		.stream = 1,
   1695		.exclusive = 1,
   1696		.r = {	{
   1697				.slots = (1 << AC97_SLOT_PCM_LEFT) |
   1698					 (1 << AC97_SLOT_PCM_RIGHT)
   1699			}
   1700		}
   1701	},
   1702	/* MIC IN #2 */
   1703	{
   1704		.stream = 1,
   1705		.exclusive = 1,
   1706		.r = {	{
   1707				.slots = (1 << AC97_SLOT_MIC)
   1708			}
   1709		}
   1710	},
   1711};
   1712
   1713static const struct ac97_quirk ac97_quirks[] = {
   1714        {
   1715		.subvendor = 0x0e11,
   1716		.subdevice = 0x000e,
   1717		.name = "Compaq Deskpro EN",	/* AD1885 */
   1718		.type = AC97_TUNE_HP_ONLY
   1719        },
   1720	{
   1721		.subvendor = 0x0e11,
   1722		.subdevice = 0x008a,
   1723		.name = "Compaq Evo W4000",	/* AD1885 */
   1724		.type = AC97_TUNE_HP_ONLY
   1725	},
   1726	{
   1727		.subvendor = 0x0e11,
   1728		.subdevice = 0x00b8,
   1729		.name = "Compaq Evo D510C",
   1730		.type = AC97_TUNE_HP_ONLY
   1731	},
   1732        {
   1733		.subvendor = 0x0e11,
   1734		.subdevice = 0x0860,
   1735		.name = "HP/Compaq nx7010",
   1736		.type = AC97_TUNE_MUTE_LED
   1737        },
   1738	{
   1739		.subvendor = 0x1014,
   1740		.subdevice = 0x0534,
   1741		.name = "ThinkPad X31",
   1742		.type = AC97_TUNE_INV_EAPD
   1743	},
   1744	{
   1745		.subvendor = 0x1014,
   1746		.subdevice = 0x1f00,
   1747		.name = "MS-9128",
   1748		.type = AC97_TUNE_ALC_JACK
   1749	},
   1750	{
   1751		.subvendor = 0x1014,
   1752		.subdevice = 0x0267,
   1753		.name = "IBM NetVista A30p",	/* AD1981B */
   1754		.type = AC97_TUNE_HP_ONLY
   1755	},
   1756	{
   1757		.subvendor = 0x1025,
   1758		.subdevice = 0x0082,
   1759		.name = "Acer Travelmate 2310",
   1760		.type = AC97_TUNE_HP_ONLY
   1761	},
   1762	{
   1763		.subvendor = 0x1025,
   1764		.subdevice = 0x0083,
   1765		.name = "Acer Aspire 3003LCi",
   1766		.type = AC97_TUNE_HP_ONLY
   1767	},
   1768	{
   1769		.subvendor = 0x1028,
   1770		.subdevice = 0x00d8,
   1771		.name = "Dell Precision 530",	/* AD1885 */
   1772		.type = AC97_TUNE_HP_ONLY
   1773	},
   1774	{
   1775		.subvendor = 0x1028,
   1776		.subdevice = 0x010d,
   1777		.name = "Dell",	/* which model?  AD1885 */
   1778		.type = AC97_TUNE_HP_ONLY
   1779	},
   1780	{
   1781		.subvendor = 0x1028,
   1782		.subdevice = 0x0126,
   1783		.name = "Dell Optiplex GX260",	/* AD1981A */
   1784		.type = AC97_TUNE_HP_ONLY
   1785	},
   1786	{
   1787		.subvendor = 0x1028,
   1788		.subdevice = 0x012c,
   1789		.name = "Dell Precision 650",	/* AD1981A */
   1790		.type = AC97_TUNE_HP_ONLY
   1791	},
   1792	{
   1793		.subvendor = 0x1028,
   1794		.subdevice = 0x012d,
   1795		.name = "Dell Precision 450",	/* AD1981B*/
   1796		.type = AC97_TUNE_HP_ONLY
   1797	},
   1798	{
   1799		.subvendor = 0x1028,
   1800		.subdevice = 0x0147,
   1801		.name = "Dell",	/* which model?  AD1981B*/
   1802		.type = AC97_TUNE_HP_ONLY
   1803	},
   1804	{
   1805		.subvendor = 0x1028,
   1806		.subdevice = 0x0151,
   1807		.name = "Dell Optiplex GX270",  /* AD1981B */
   1808		.type = AC97_TUNE_HP_ONLY
   1809	},
   1810	{
   1811		.subvendor = 0x1028,
   1812		.subdevice = 0x014e,
   1813		.name = "Dell D800", /* STAC9750/51 */
   1814		.type = AC97_TUNE_HP_ONLY
   1815	},
   1816	{
   1817		.subvendor = 0x1028,
   1818		.subdevice = 0x0163,
   1819		.name = "Dell Unknown",	/* STAC9750/51 */
   1820		.type = AC97_TUNE_HP_ONLY
   1821	},
   1822	{
   1823		.subvendor = 0x1028,
   1824		.subdevice = 0x016a,
   1825		.name = "Dell Inspiron 8600",	/* STAC9750/51 */
   1826		.type = AC97_TUNE_HP_ONLY
   1827	},
   1828	{
   1829		.subvendor = 0x1028,
   1830		.subdevice = 0x0182,
   1831		.name = "Dell Latitude D610",	/* STAC9750/51 */
   1832		.type = AC97_TUNE_HP_ONLY
   1833	},
   1834	{
   1835		.subvendor = 0x1028,
   1836		.subdevice = 0x0186,
   1837		.name = "Dell Latitude D810", /* cf. Malone #41015 */
   1838		.type = AC97_TUNE_HP_MUTE_LED
   1839	},
   1840	{
   1841		.subvendor = 0x1028,
   1842		.subdevice = 0x0188,
   1843		.name = "Dell Inspiron 6000",
   1844		.type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
   1845	},
   1846	{
   1847		.subvendor = 0x1028,
   1848		.subdevice = 0x0189,
   1849		.name = "Dell Inspiron 9300",
   1850		.type = AC97_TUNE_HP_MUTE_LED
   1851	},
   1852	{
   1853		.subvendor = 0x1028,
   1854		.subdevice = 0x0191,
   1855		.name = "Dell Inspiron 8600",
   1856		.type = AC97_TUNE_HP_ONLY
   1857	},
   1858	{
   1859		.subvendor = 0x103c,
   1860		.subdevice = 0x006d,
   1861		.name = "HP zv5000",
   1862		.type = AC97_TUNE_MUTE_LED	/*AD1981B*/
   1863	},
   1864	{	/* FIXME: which codec? */
   1865		.subvendor = 0x103c,
   1866		.subdevice = 0x00c3,
   1867		.name = "HP xw6000",
   1868		.type = AC97_TUNE_HP_ONLY
   1869	},
   1870	{
   1871		.subvendor = 0x103c,
   1872		.subdevice = 0x088c,
   1873		.name = "HP nc8000",
   1874		.type = AC97_TUNE_HP_MUTE_LED
   1875	},
   1876	{
   1877		.subvendor = 0x103c,
   1878		.subdevice = 0x0890,
   1879		.name = "HP nc6000",
   1880		.type = AC97_TUNE_MUTE_LED
   1881	},
   1882	{
   1883		.subvendor = 0x103c,
   1884		.subdevice = 0x129d,
   1885		.name = "HP xw8000",
   1886		.type = AC97_TUNE_HP_ONLY
   1887	},
   1888	{
   1889		.subvendor = 0x103c,
   1890		.subdevice = 0x0938,
   1891		.name = "HP nc4200",
   1892		.type = AC97_TUNE_HP_MUTE_LED
   1893	},
   1894	{
   1895		.subvendor = 0x103c,
   1896		.subdevice = 0x099c,
   1897		.name = "HP nx6110/nc6120",
   1898		.type = AC97_TUNE_HP_MUTE_LED
   1899	},
   1900	{
   1901		.subvendor = 0x103c,
   1902		.subdevice = 0x0944,
   1903		.name = "HP nc6220",
   1904		.type = AC97_TUNE_HP_MUTE_LED
   1905	},
   1906	{
   1907		.subvendor = 0x103c,
   1908		.subdevice = 0x0934,
   1909		.name = "HP nc8220",
   1910		.type = AC97_TUNE_HP_MUTE_LED
   1911	},
   1912	{
   1913		.subvendor = 0x103c,
   1914		.subdevice = 0x12f1,
   1915		.name = "HP xw8200",	/* AD1981B*/
   1916		.type = AC97_TUNE_HP_ONLY
   1917	},
   1918	{
   1919		.subvendor = 0x103c,
   1920		.subdevice = 0x12f2,
   1921		.name = "HP xw6200",
   1922		.type = AC97_TUNE_HP_ONLY
   1923	},
   1924	{
   1925		.subvendor = 0x103c,
   1926		.subdevice = 0x3008,
   1927		.name = "HP xw4200",	/* AD1981B*/
   1928		.type = AC97_TUNE_HP_ONLY
   1929	},
   1930	{
   1931		.subvendor = 0x104d,
   1932		.subdevice = 0x8144,
   1933		.name = "Sony",
   1934		.type = AC97_TUNE_INV_EAPD
   1935	},
   1936	{
   1937		.subvendor = 0x104d,
   1938		.subdevice = 0x8197,
   1939		.name = "Sony S1XP",
   1940		.type = AC97_TUNE_INV_EAPD
   1941	},
   1942	{
   1943		.subvendor = 0x104d,
   1944		.subdevice = 0x81c0,
   1945		.name = "Sony VAIO VGN-T350P", /*AD1981B*/
   1946		.type = AC97_TUNE_INV_EAPD
   1947	},
   1948	{
   1949		.subvendor = 0x104d,
   1950		.subdevice = 0x81c5,
   1951		.name = "Sony VAIO VGN-B1VP", /*AD1981B*/
   1952		.type = AC97_TUNE_INV_EAPD
   1953	},
   1954 	{
   1955		.subvendor = 0x1043,
   1956		.subdevice = 0x80f3,
   1957		.name = "ASUS ICH5/AD1985",
   1958		.type = AC97_TUNE_AD_SHARING
   1959	},
   1960	{
   1961		.subvendor = 0x10cf,
   1962		.subdevice = 0x11c3,
   1963		.name = "Fujitsu-Siemens E4010",
   1964		.type = AC97_TUNE_HP_ONLY
   1965	},
   1966	{
   1967		.subvendor = 0x10cf,
   1968		.subdevice = 0x1225,
   1969		.name = "Fujitsu-Siemens T3010",
   1970		.type = AC97_TUNE_HP_ONLY
   1971	},
   1972	{
   1973		.subvendor = 0x10cf,
   1974		.subdevice = 0x1253,
   1975		.name = "Fujitsu S6210",	/* STAC9750/51 */
   1976		.type = AC97_TUNE_HP_ONLY
   1977	},
   1978	{
   1979		.subvendor = 0x10cf,
   1980		.subdevice = 0x127d,
   1981		.name = "Fujitsu Lifebook P7010",
   1982		.type = AC97_TUNE_HP_ONLY
   1983	},
   1984	{
   1985		.subvendor = 0x10cf,
   1986		.subdevice = 0x127e,
   1987		.name = "Fujitsu Lifebook C1211D",
   1988		.type = AC97_TUNE_HP_ONLY
   1989	},
   1990	{
   1991		.subvendor = 0x10cf,
   1992		.subdevice = 0x12ec,
   1993		.name = "Fujitsu-Siemens 4010",
   1994		.type = AC97_TUNE_HP_ONLY
   1995	},
   1996	{
   1997		.subvendor = 0x10cf,
   1998		.subdevice = 0x12f2,
   1999		.name = "Fujitsu-Siemens Celsius H320",
   2000		.type = AC97_TUNE_SWAP_HP
   2001	},
   2002	{
   2003		.subvendor = 0x10f1,
   2004		.subdevice = 0x2665,
   2005		.name = "Fujitsu-Siemens Celsius",	/* AD1981? */
   2006		.type = AC97_TUNE_HP_ONLY
   2007	},
   2008	{
   2009		.subvendor = 0x10f1,
   2010		.subdevice = 0x2885,
   2011		.name = "AMD64 Mobo",	/* ALC650 */
   2012		.type = AC97_TUNE_HP_ONLY
   2013	},
   2014	{
   2015		.subvendor = 0x10f1,
   2016		.subdevice = 0x2895,
   2017		.name = "Tyan Thunder K8WE",
   2018		.type = AC97_TUNE_HP_ONLY
   2019	},
   2020	{
   2021		.subvendor = 0x10f7,
   2022		.subdevice = 0x834c,
   2023		.name = "Panasonic CF-R4",
   2024		.type = AC97_TUNE_HP_ONLY,
   2025	},
   2026	{
   2027		.subvendor = 0x110a,
   2028		.subdevice = 0x0056,
   2029		.name = "Fujitsu-Siemens Scenic",	/* AD1981? */
   2030		.type = AC97_TUNE_HP_ONLY
   2031	},
   2032	{
   2033		.subvendor = 0x11d4,
   2034		.subdevice = 0x5375,
   2035		.name = "ADI AD1985 (discrete)",
   2036		.type = AC97_TUNE_HP_ONLY
   2037	},
   2038	{
   2039		.subvendor = 0x1462,
   2040		.subdevice = 0x5470,
   2041		.name = "MSI P4 ATX 645 Ultra",
   2042		.type = AC97_TUNE_HP_ONLY
   2043	},
   2044	{
   2045		.subvendor = 0x161f,
   2046		.subdevice = 0x202f,
   2047		.name = "Gateway M520",
   2048		.type = AC97_TUNE_INV_EAPD
   2049	},
   2050	{
   2051		.subvendor = 0x161f,
   2052		.subdevice = 0x203a,
   2053		.name = "Gateway 4525GZ",		/* AD1981B */
   2054		.type = AC97_TUNE_INV_EAPD
   2055	},
   2056	{
   2057		.subvendor = 0x1734,
   2058		.subdevice = 0x0088,
   2059		.name = "Fujitsu-Siemens D1522",	/* AD1981 */
   2060		.type = AC97_TUNE_HP_ONLY
   2061	},
   2062	{
   2063		.subvendor = 0x8086,
   2064		.subdevice = 0x2000,
   2065		.mask = 0xfff0,
   2066		.name = "Intel ICH5/AD1985",
   2067		.type = AC97_TUNE_AD_SHARING
   2068	},
   2069	{
   2070		.subvendor = 0x8086,
   2071		.subdevice = 0x4000,
   2072		.mask = 0xfff0,
   2073		.name = "Intel ICH5/AD1985",
   2074		.type = AC97_TUNE_AD_SHARING
   2075	},
   2076	{
   2077		.subvendor = 0x8086,
   2078		.subdevice = 0x4856,
   2079		.name = "Intel D845WN (82801BA)",
   2080		.type = AC97_TUNE_SWAP_HP
   2081	},
   2082	{
   2083		.subvendor = 0x8086,
   2084		.subdevice = 0x4d44,
   2085		.name = "Intel D850EMV2",	/* AD1885 */
   2086		.type = AC97_TUNE_HP_ONLY
   2087	},
   2088	{
   2089		.subvendor = 0x8086,
   2090		.subdevice = 0x4d56,
   2091		.name = "Intel ICH/AD1885",
   2092		.type = AC97_TUNE_HP_ONLY
   2093	},
   2094	{
   2095		.subvendor = 0x8086,
   2096		.subdevice = 0x6000,
   2097		.mask = 0xfff0,
   2098		.name = "Intel ICH5/AD1985",
   2099		.type = AC97_TUNE_AD_SHARING
   2100	},
   2101	{
   2102		.subvendor = 0x8086,
   2103		.subdevice = 0xe000,
   2104		.mask = 0xfff0,
   2105		.name = "Intel ICH5/AD1985",
   2106		.type = AC97_TUNE_AD_SHARING
   2107	},
   2108#if 0 /* FIXME: this seems wrong on most boards */
   2109	{
   2110		.subvendor = 0x8086,
   2111		.subdevice = 0xa000,
   2112		.mask = 0xfff0,
   2113		.name = "Intel ICH5/AD1985",
   2114		.type = AC97_TUNE_HP_ONLY
   2115	},
   2116#endif
   2117	{ } /* terminator */
   2118};
   2119
   2120static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
   2121			      const char *quirk_override)
   2122{
   2123	struct snd_ac97_bus *pbus;
   2124	struct snd_ac97_template ac97;
   2125	int err;
   2126	unsigned int i, codecs;
   2127	unsigned int glob_sta = 0;
   2128	const struct snd_ac97_bus_ops *ops;
   2129	static const struct snd_ac97_bus_ops standard_bus_ops = {
   2130		.write = snd_intel8x0_codec_write,
   2131		.read = snd_intel8x0_codec_read,
   2132	};
   2133	static const struct snd_ac97_bus_ops ali_bus_ops = {
   2134		.write = snd_intel8x0_ali_codec_write,
   2135		.read = snd_intel8x0_ali_codec_read,
   2136	};
   2137
   2138	chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
   2139	if (!spdif_aclink) {
   2140		switch (chip->device_type) {
   2141		case DEVICE_NFORCE:
   2142			chip->spdif_idx = NVD_SPBAR;
   2143			break;
   2144		case DEVICE_ALI:
   2145			chip->spdif_idx = ALID_AC97SPDIFOUT;
   2146			break;
   2147		case DEVICE_INTEL_ICH4:
   2148			chip->spdif_idx = ICHD_SPBAR;
   2149			break;
   2150		}
   2151	}
   2152
   2153	chip->in_ac97_init = 1;
   2154	
   2155	memset(&ac97, 0, sizeof(ac97));
   2156	ac97.private_data = chip;
   2157	ac97.private_free = snd_intel8x0_mixer_free_ac97;
   2158	ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
   2159	if (chip->xbox)
   2160		ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
   2161	if (chip->device_type != DEVICE_ALI) {
   2162		glob_sta = igetdword(chip, ICHREG(GLOB_STA));
   2163		ops = &standard_bus_ops;
   2164		chip->in_sdin_init = 1;
   2165		codecs = 0;
   2166		for (i = 0; i < chip->max_codecs; i++) {
   2167			if (! (glob_sta & chip->codec_bit[i]))
   2168				continue;
   2169			if (chip->device_type == DEVICE_INTEL_ICH4) {
   2170				snd_intel8x0_codec_read_test(chip, codecs);
   2171				chip->ac97_sdin[codecs] =
   2172					igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
   2173				if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
   2174					chip->ac97_sdin[codecs] = 0;
   2175			} else
   2176				chip->ac97_sdin[codecs] = i;
   2177			codecs++;
   2178		}
   2179		chip->in_sdin_init = 0;
   2180		if (! codecs)
   2181			codecs = 1;
   2182	} else {
   2183		ops = &ali_bus_ops;
   2184		codecs = 1;
   2185		/* detect the secondary codec */
   2186		for (i = 0; i < 100; i++) {
   2187			unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
   2188			if (reg & 0x40) {
   2189				codecs = 2;
   2190				break;
   2191			}
   2192			iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
   2193			udelay(1);
   2194		}
   2195	}
   2196	err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus);
   2197	if (err < 0)
   2198		goto __err;
   2199	pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
   2200	if (ac97_clock >= 8000 && ac97_clock <= 48000)
   2201		pbus->clock = ac97_clock;
   2202	/* FIXME: my test board doesn't work well with VRA... */
   2203	if (chip->device_type == DEVICE_ALI)
   2204		pbus->no_vra = 1;
   2205	else
   2206		pbus->dra = 1;
   2207	chip->ac97_bus = pbus;
   2208	chip->ncodecs = codecs;
   2209
   2210	ac97.pci = chip->pci;
   2211	for (i = 0; i < codecs; i++) {
   2212		ac97.num = i;
   2213		err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]);
   2214		if (err < 0) {
   2215			if (err != -EACCES)
   2216				dev_err(chip->card->dev,
   2217					"Unable to initialize codec #%d\n", i);
   2218			if (i == 0)
   2219				goto __err;
   2220		}
   2221	}
   2222	/* tune up the primary codec */
   2223	snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
   2224	/* enable separate SDINs for ICH4 */
   2225	if (chip->device_type == DEVICE_INTEL_ICH4)
   2226		pbus->isdin = 1;
   2227	/* find the available PCM streams */
   2228	i = ARRAY_SIZE(ac97_pcm_defs);
   2229	if (chip->device_type != DEVICE_INTEL_ICH4)
   2230		i -= 2;		/* do not allocate PCM2IN and MIC2 */
   2231	if (chip->spdif_idx < 0)
   2232		i--;		/* do not allocate S/PDIF */
   2233	err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
   2234	if (err < 0)
   2235		goto __err;
   2236	chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
   2237	chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
   2238	chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
   2239	if (chip->spdif_idx >= 0)
   2240		chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
   2241	if (chip->device_type == DEVICE_INTEL_ICH4) {
   2242		chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
   2243		chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
   2244	}
   2245	/* enable separate SDINs for ICH4 */
   2246	if (chip->device_type == DEVICE_INTEL_ICH4) {
   2247		struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
   2248		u8 tmp = igetbyte(chip, ICHREG(SDM));
   2249		tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
   2250		if (pcm) {
   2251			tmp |= ICH_SE;	/* steer enable for multiple SDINs */
   2252			tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
   2253			for (i = 1; i < 4; i++) {
   2254				if (pcm->r[0].codec[i]) {
   2255					tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
   2256					break;
   2257				}
   2258			}
   2259		} else {
   2260			tmp &= ~ICH_SE; /* steer disable */
   2261		}
   2262		iputbyte(chip, ICHREG(SDM), tmp);
   2263	}
   2264	if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
   2265		chip->multi4 = 1;
   2266		if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
   2267			chip->multi6 = 1;
   2268			if (chip->ac97[0]->flags & AC97_HAS_8CH)
   2269				chip->multi8 = 1;
   2270		}
   2271	}
   2272	if (pbus->pcms[0].r[1].rslots[0]) {
   2273		chip->dra = 1;
   2274	}
   2275	if (chip->device_type == DEVICE_INTEL_ICH4) {
   2276		if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
   2277			chip->smp20bit = 1;
   2278	}
   2279	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
   2280		/* 48kHz only */
   2281		chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
   2282	}
   2283	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
   2284		/* use slot 10/11 for SPDIF */
   2285		u32 val;
   2286		val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
   2287		val |= ICH_PCM_SPDIF_1011;
   2288		iputdword(chip, ICHREG(GLOB_CNT), val);
   2289		snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
   2290	}
   2291	chip->in_ac97_init = 0;
   2292	return 0;
   2293
   2294 __err:
   2295	/* clear the cold-reset bit for the next chance */
   2296	if (chip->device_type != DEVICE_ALI)
   2297		iputdword(chip, ICHREG(GLOB_CNT),
   2298			  igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
   2299	return err;
   2300}
   2301
   2302
   2303/*
   2304 *
   2305 */
   2306
   2307static void do_ali_reset(struct intel8x0 *chip)
   2308{
   2309	iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
   2310	iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
   2311	iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
   2312	iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
   2313	iputdword(chip, ICHREG(ALI_INTERFACECR),
   2314		  ICH_ALI_IF_PI|ICH_ALI_IF_PO);
   2315	iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
   2316	iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
   2317}
   2318
   2319#ifdef CONFIG_SND_AC97_POWER_SAVE
   2320static const struct snd_pci_quirk ich_chip_reset_mode[] = {
   2321	SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
   2322	{ } /* end */
   2323};
   2324
   2325static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
   2326{
   2327	unsigned int cnt;
   2328	/* ACLink on, 2 channels */
   2329
   2330	if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
   2331		return -EIO;
   2332
   2333	cnt = igetdword(chip, ICHREG(GLOB_CNT));
   2334	cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
   2335
   2336	/* do cold reset - the full ac97 powerdown may leave the controller
   2337	 * in a warm state but actually it cannot communicate with the codec.
   2338	 */
   2339	iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
   2340	cnt = igetdword(chip, ICHREG(GLOB_CNT));
   2341	udelay(10);
   2342	iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
   2343	msleep(1);
   2344	return 0;
   2345}
   2346#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
   2347	(!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
   2348#else
   2349#define snd_intel8x0_ich_chip_cold_reset(chip)	0
   2350#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
   2351#endif
   2352
   2353static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
   2354{
   2355	unsigned long end_time;
   2356	unsigned int cnt;
   2357	/* ACLink on, 2 channels */
   2358	cnt = igetdword(chip, ICHREG(GLOB_CNT));
   2359	cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
   2360	/* finish cold or do warm reset */
   2361	cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
   2362	iputdword(chip, ICHREG(GLOB_CNT), cnt);
   2363	end_time = (jiffies + (HZ / 4)) + 1;
   2364	do {
   2365		if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
   2366			return 0;
   2367		schedule_timeout_uninterruptible(1);
   2368	} while (time_after_eq(end_time, jiffies));
   2369	dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
   2370		   igetdword(chip, ICHREG(GLOB_CNT)));
   2371	return -EIO;
   2372}
   2373
   2374static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
   2375{
   2376	unsigned long end_time;
   2377	unsigned int status, nstatus;
   2378	unsigned int cnt;
   2379	int err;
   2380
   2381	/* put logic to right state */
   2382	/* first clear status bits */
   2383	status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
   2384	if (chip->device_type == DEVICE_NFORCE)
   2385		status |= ICH_NVSPINT;
   2386	cnt = igetdword(chip, ICHREG(GLOB_STA));
   2387	iputdword(chip, ICHREG(GLOB_STA), cnt & status);
   2388
   2389	if (snd_intel8x0_ich_chip_can_cold_reset(chip))
   2390		err = snd_intel8x0_ich_chip_cold_reset(chip);
   2391	else
   2392		err = snd_intel8x0_ich_chip_reset(chip);
   2393	if (err < 0)
   2394		return err;
   2395
   2396	if (probing) {
   2397		/* wait for any codec ready status.
   2398		 * Once it becomes ready it should remain ready
   2399		 * as long as we do not disable the ac97 link.
   2400		 */
   2401		end_time = jiffies + HZ;
   2402		do {
   2403			status = igetdword(chip, ICHREG(GLOB_STA)) &
   2404				chip->codec_isr_bits;
   2405			if (status)
   2406				break;
   2407			schedule_timeout_uninterruptible(1);
   2408		} while (time_after_eq(end_time, jiffies));
   2409		if (! status) {
   2410			/* no codec is found */
   2411			dev_err(chip->card->dev,
   2412				"codec_ready: codec is not ready [0x%x]\n",
   2413				   igetdword(chip, ICHREG(GLOB_STA)));
   2414			return -EIO;
   2415		}
   2416
   2417		/* wait for other codecs ready status. */
   2418		end_time = jiffies + HZ / 4;
   2419		while (status != chip->codec_isr_bits &&
   2420		       time_after_eq(end_time, jiffies)) {
   2421			schedule_timeout_uninterruptible(1);
   2422			status |= igetdword(chip, ICHREG(GLOB_STA)) &
   2423				chip->codec_isr_bits;
   2424		}
   2425
   2426	} else {
   2427		/* resume phase */
   2428		int i;
   2429		status = 0;
   2430		for (i = 0; i < chip->ncodecs; i++)
   2431			if (chip->ac97[i])
   2432				status |= chip->codec_bit[chip->ac97_sdin[i]];
   2433		/* wait until all the probed codecs are ready */
   2434		end_time = jiffies + HZ;
   2435		do {
   2436			nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
   2437				chip->codec_isr_bits;
   2438			if (status == nstatus)
   2439				break;
   2440			schedule_timeout_uninterruptible(1);
   2441		} while (time_after_eq(end_time, jiffies));
   2442	}
   2443
   2444	if (chip->device_type == DEVICE_SIS) {
   2445		/* unmute the output on SIS7012 */
   2446		iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
   2447	}
   2448	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
   2449		/* enable SPDIF interrupt */
   2450		unsigned int val;
   2451		pci_read_config_dword(chip->pci, 0x4c, &val);
   2452		val |= 0x1000000;
   2453		pci_write_config_dword(chip->pci, 0x4c, val);
   2454	}
   2455      	return 0;
   2456}
   2457
   2458static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
   2459{
   2460	u32 reg;
   2461	int i = 0;
   2462
   2463	reg = igetdword(chip, ICHREG(ALI_SCR));
   2464	if ((reg & 2) == 0)	/* Cold required */
   2465		reg |= 2;
   2466	else
   2467		reg |= 1;	/* Warm */
   2468	reg &= ~0x80000000;	/* ACLink on */
   2469	iputdword(chip, ICHREG(ALI_SCR), reg);
   2470
   2471	for (i = 0; i < HZ / 2; i++) {
   2472		if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
   2473			goto __ok;
   2474		schedule_timeout_uninterruptible(1);
   2475	}
   2476	dev_err(chip->card->dev, "AC'97 reset failed.\n");
   2477	if (probing)
   2478		return -EIO;
   2479
   2480 __ok:
   2481	for (i = 0; i < HZ / 2; i++) {
   2482		reg = igetdword(chip, ICHREG(ALI_RTSR));
   2483		if (reg & 0x80) /* primary codec */
   2484			break;
   2485		iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
   2486		schedule_timeout_uninterruptible(1);
   2487	}
   2488
   2489	do_ali_reset(chip);
   2490	return 0;
   2491}
   2492
   2493static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
   2494{
   2495	unsigned int i, timeout;
   2496	int err;
   2497	
   2498	if (chip->device_type != DEVICE_ALI) {
   2499		err = snd_intel8x0_ich_chip_init(chip, probing);
   2500		if (err < 0)
   2501			return err;
   2502		iagetword(chip, 0);	/* clear semaphore flag */
   2503	} else {
   2504		err = snd_intel8x0_ali_chip_init(chip, probing);
   2505		if (err < 0)
   2506			return err;
   2507	}
   2508
   2509	/* disable interrupts */
   2510	for (i = 0; i < chip->bdbars_count; i++)
   2511		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
   2512	/* reset channels */
   2513	for (i = 0; i < chip->bdbars_count; i++)
   2514		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
   2515	for (i = 0; i < chip->bdbars_count; i++) {
   2516	        timeout = 100000;
   2517	        while (--timeout != 0) {
   2518        		if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
   2519        		        break;
   2520                }
   2521                if (timeout == 0)
   2522			dev_err(chip->card->dev, "reset of registers failed?\n");
   2523        }
   2524	/* initialize Buffer Descriptor Lists */
   2525	for (i = 0; i < chip->bdbars_count; i++)
   2526		iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
   2527			  chip->ichd[i].bdbar_addr);
   2528	return 0;
   2529}
   2530
   2531static void snd_intel8x0_free(struct snd_card *card)
   2532{
   2533	struct intel8x0 *chip = card->private_data;
   2534	unsigned int i;
   2535
   2536	if (chip->irq < 0)
   2537		goto __hw_end;
   2538	/* disable interrupts */
   2539	for (i = 0; i < chip->bdbars_count; i++)
   2540		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
   2541	/* reset channels */
   2542	for (i = 0; i < chip->bdbars_count; i++)
   2543		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
   2544	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
   2545		/* stop the spdif interrupt */
   2546		unsigned int val;
   2547		pci_read_config_dword(chip->pci, 0x4c, &val);
   2548		val &= ~0x1000000;
   2549		pci_write_config_dword(chip->pci, 0x4c, val);
   2550	}
   2551	/* --- */
   2552
   2553      __hw_end:
   2554	if (chip->irq >= 0)
   2555		free_irq(chip->irq, chip);
   2556}
   2557
   2558#ifdef CONFIG_PM_SLEEP
   2559/*
   2560 * power management
   2561 */
   2562static int intel8x0_suspend(struct device *dev)
   2563{
   2564	struct snd_card *card = dev_get_drvdata(dev);
   2565	struct intel8x0 *chip = card->private_data;
   2566	int i;
   2567
   2568	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
   2569	for (i = 0; i < chip->ncodecs; i++)
   2570		snd_ac97_suspend(chip->ac97[i]);
   2571	if (chip->device_type == DEVICE_INTEL_ICH4)
   2572		chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
   2573
   2574	if (chip->irq >= 0) {
   2575		free_irq(chip->irq, chip);
   2576		chip->irq = -1;
   2577		card->sync_irq = -1;
   2578	}
   2579	return 0;
   2580}
   2581
   2582static int intel8x0_resume(struct device *dev)
   2583{
   2584	struct pci_dev *pci = to_pci_dev(dev);
   2585	struct snd_card *card = dev_get_drvdata(dev);
   2586	struct intel8x0 *chip = card->private_data;
   2587	int i;
   2588
   2589	snd_intel8x0_chip_init(chip, 0);
   2590	if (request_irq(pci->irq, snd_intel8x0_interrupt,
   2591			IRQF_SHARED, KBUILD_MODNAME, chip)) {
   2592		dev_err(dev, "unable to grab IRQ %d, disabling device\n",
   2593			pci->irq);
   2594		snd_card_disconnect(card);
   2595		return -EIO;
   2596	}
   2597	chip->irq = pci->irq;
   2598	card->sync_irq = chip->irq;
   2599
   2600	/* re-initialize mixer stuff */
   2601	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
   2602		/* enable separate SDINs for ICH4 */
   2603		iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
   2604		/* use slot 10/11 for SPDIF */
   2605		iputdword(chip, ICHREG(GLOB_CNT),
   2606			  (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
   2607			  ICH_PCM_SPDIF_1011);
   2608	}
   2609
   2610	for (i = 0; i < chip->ncodecs; i++)
   2611		snd_ac97_resume(chip->ac97[i]);
   2612
   2613	/* resume status */
   2614	for (i = 0; i < chip->bdbars_count; i++) {
   2615		struct ichdev *ichdev = &chip->ichd[i];
   2616		unsigned long port = ichdev->reg_offset;
   2617		if (! ichdev->substream || ! ichdev->suspended)
   2618			continue;
   2619		if (ichdev->ichd == ICHD_PCMOUT)
   2620			snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
   2621		iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
   2622		iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
   2623		iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
   2624		iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
   2625	}
   2626
   2627	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
   2628	return 0;
   2629}
   2630
   2631static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
   2632#define INTEL8X0_PM_OPS	&intel8x0_pm
   2633#else
   2634#define INTEL8X0_PM_OPS	NULL
   2635#endif /* CONFIG_PM_SLEEP */
   2636
   2637#define INTEL8X0_TESTBUF_SIZE	32768	/* enough large for one shot */
   2638
   2639static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
   2640{
   2641	struct snd_pcm_substream *subs;
   2642	struct ichdev *ichdev;
   2643	unsigned long port;
   2644	unsigned long pos, pos1, t;
   2645	int civ, timeout = 1000, attempt = 1;
   2646	ktime_t start_time, stop_time;
   2647
   2648	if (chip->ac97_bus->clock != 48000)
   2649		return; /* specified in module option */
   2650	if (chip->inside_vm && !ac97_clock)
   2651		return; /* no measurement on VM */
   2652
   2653      __again:
   2654	subs = chip->pcm[0]->streams[0].substream;
   2655	if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
   2656		dev_warn(chip->card->dev,
   2657			 "no playback buffer allocated - aborting measure ac97 clock\n");
   2658		return;
   2659	}
   2660	ichdev = &chip->ichd[ICHD_PCMOUT];
   2661	ichdev->physbuf = subs->dma_buffer.addr;
   2662	ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
   2663	ichdev->substream = NULL; /* don't process interrupts */
   2664
   2665	/* set rate */
   2666	if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
   2667		dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
   2668			chip->ac97_bus->clock);
   2669		return;
   2670	}
   2671	snd_intel8x0_setup_periods(chip, ichdev);
   2672	port = ichdev->reg_offset;
   2673	spin_lock_irq(&chip->reg_lock);
   2674	chip->in_measurement = 1;
   2675	/* trigger */
   2676	if (chip->device_type != DEVICE_ALI)
   2677		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
   2678	else {
   2679		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
   2680		iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
   2681	}
   2682	start_time = ktime_get();
   2683	spin_unlock_irq(&chip->reg_lock);
   2684	msleep(50);
   2685	spin_lock_irq(&chip->reg_lock);
   2686	/* check the position */
   2687	do {
   2688		civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
   2689		pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
   2690		if (pos1 == 0) {
   2691			udelay(10);
   2692			continue;
   2693		}
   2694		if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
   2695		    pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
   2696			break;
   2697	} while (timeout--);
   2698	if (pos1 == 0) {	/* oops, this value is not reliable */
   2699		pos = 0;
   2700	} else {
   2701		pos = ichdev->fragsize1;
   2702		pos -= pos1 << ichdev->pos_shift;
   2703		pos += ichdev->position;
   2704	}
   2705	chip->in_measurement = 0;
   2706	stop_time = ktime_get();
   2707	/* stop */
   2708	if (chip->device_type == DEVICE_ALI) {
   2709		iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
   2710		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
   2711		while (igetbyte(chip, port + ICH_REG_OFF_CR))
   2712			;
   2713	} else {
   2714		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
   2715		while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
   2716			;
   2717	}
   2718	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
   2719	spin_unlock_irq(&chip->reg_lock);
   2720
   2721	if (pos == 0) {
   2722		dev_err(chip->card->dev,
   2723			"measure - unreliable DMA position..\n");
   2724	      __retry:
   2725		if (attempt < 3) {
   2726			msleep(300);
   2727			attempt++;
   2728			goto __again;
   2729		}
   2730		goto __end;
   2731	}
   2732
   2733	pos /= 4;
   2734	t = ktime_us_delta(stop_time, start_time);
   2735	dev_info(chip->card->dev,
   2736		 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
   2737	if (t == 0) {
   2738		dev_err(chip->card->dev, "?? calculation error..\n");
   2739		goto __retry;
   2740	}
   2741	pos *= 1000;
   2742	pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
   2743	if (pos < 40000 || pos >= 60000) {
   2744		/* abnormal value. hw problem? */
   2745		dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
   2746		goto __retry;
   2747	} else if (pos > 40500 && pos < 41500)
   2748		/* first exception - 41000Hz reference clock */
   2749		chip->ac97_bus->clock = 41000;
   2750	else if (pos > 43600 && pos < 44600)
   2751		/* second exception - 44100HZ reference clock */
   2752		chip->ac97_bus->clock = 44100;
   2753	else if (pos < 47500 || pos > 48500)
   2754		/* not 48000Hz, tuning the clock.. */
   2755		chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
   2756      __end:
   2757	dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
   2758	snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
   2759}
   2760
   2761static const struct snd_pci_quirk intel8x0_clock_list[] = {
   2762	SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
   2763	SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
   2764	SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
   2765	SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
   2766	SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
   2767	SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
   2768	{ }	/* terminator */
   2769};
   2770
   2771static int intel8x0_in_clock_list(struct intel8x0 *chip)
   2772{
   2773	struct pci_dev *pci = chip->pci;
   2774	const struct snd_pci_quirk *wl;
   2775
   2776	wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
   2777	if (!wl)
   2778		return 0;
   2779	dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
   2780	       pci->subsystem_vendor, pci->subsystem_device, wl->value);
   2781	chip->ac97_bus->clock = wl->value;
   2782	return 1;
   2783}
   2784
   2785static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
   2786				   struct snd_info_buffer *buffer)
   2787{
   2788	struct intel8x0 *chip = entry->private_data;
   2789	unsigned int tmp;
   2790
   2791	snd_iprintf(buffer, "Intel8x0\n\n");
   2792	if (chip->device_type == DEVICE_ALI)
   2793		return;
   2794	tmp = igetdword(chip, ICHREG(GLOB_STA));
   2795	snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
   2796	snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
   2797	if (chip->device_type == DEVICE_INTEL_ICH4)
   2798		snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
   2799	snd_iprintf(buffer, "AC'97 codecs ready    :");
   2800	if (tmp & chip->codec_isr_bits) {
   2801		int i;
   2802		static const char *codecs[3] = {
   2803			"primary", "secondary", "tertiary"
   2804		};
   2805		for (i = 0; i < chip->max_codecs; i++)
   2806			if (tmp & chip->codec_bit[i])
   2807				snd_iprintf(buffer, " %s", codecs[i]);
   2808	} else
   2809		snd_iprintf(buffer, " none");
   2810	snd_iprintf(buffer, "\n");
   2811	if (chip->device_type == DEVICE_INTEL_ICH4 ||
   2812	    chip->device_type == DEVICE_SIS)
   2813		snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
   2814			chip->ac97_sdin[0],
   2815			chip->ac97_sdin[1],
   2816			chip->ac97_sdin[2]);
   2817}
   2818
   2819static void snd_intel8x0_proc_init(struct intel8x0 *chip)
   2820{
   2821	snd_card_ro_proc_new(chip->card, "intel8x0", chip,
   2822			     snd_intel8x0_proc_read);
   2823}
   2824
   2825struct ich_reg_info {
   2826	unsigned int int_sta_mask;
   2827	unsigned int offset;
   2828};
   2829
   2830static const unsigned int ich_codec_bits[3] = {
   2831	ICH_PCR, ICH_SCR, ICH_TCR
   2832};
   2833static const unsigned int sis_codec_bits[3] = {
   2834	ICH_PCR, ICH_SCR, ICH_SIS_TCR
   2835};
   2836
   2837static int snd_intel8x0_inside_vm(struct pci_dev *pci)
   2838{
   2839	int result  = inside_vm;
   2840	char *msg   = NULL;
   2841
   2842	/* check module parameter first (override detection) */
   2843	if (result >= 0) {
   2844		msg = result ? "enable (forced) VM" : "disable (forced) VM";
   2845		goto fini;
   2846	}
   2847
   2848	/* check for known (emulated) devices */
   2849	result = 0;
   2850	if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
   2851	    pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
   2852		/* KVM emulated sound, PCI SSID: 1af4:1100 */
   2853		msg = "enable KVM";
   2854		result = 1;
   2855	} else if (pci->subsystem_vendor == 0x1ab8) {
   2856		/* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
   2857		msg = "enable Parallels VM";
   2858		result = 1;
   2859	}
   2860
   2861fini:
   2862	if (msg != NULL)
   2863		dev_info(&pci->dev, "%s optimization\n", msg);
   2864
   2865	return result;
   2866}
   2867
   2868static int snd_intel8x0_init(struct snd_card *card,
   2869			     struct pci_dev *pci,
   2870			     unsigned long device_type)
   2871{
   2872	struct intel8x0 *chip = card->private_data;
   2873	int err;
   2874	unsigned int i;
   2875	unsigned int int_sta_masks;
   2876	struct ichdev *ichdev;
   2877
   2878	static const unsigned int bdbars[] = {
   2879		3, /* DEVICE_INTEL */
   2880		6, /* DEVICE_INTEL_ICH4 */
   2881		3, /* DEVICE_SIS */
   2882		6, /* DEVICE_ALI */
   2883		4, /* DEVICE_NFORCE */
   2884	};
   2885	static const struct ich_reg_info intel_regs[6] = {
   2886		{ ICH_PIINT, 0 },
   2887		{ ICH_POINT, 0x10 },
   2888		{ ICH_MCINT, 0x20 },
   2889		{ ICH_M2INT, 0x40 },
   2890		{ ICH_P2INT, 0x50 },
   2891		{ ICH_SPINT, 0x60 },
   2892	};
   2893	static const struct ich_reg_info nforce_regs[4] = {
   2894		{ ICH_PIINT, 0 },
   2895		{ ICH_POINT, 0x10 },
   2896		{ ICH_MCINT, 0x20 },
   2897		{ ICH_NVSPINT, 0x70 },
   2898	};
   2899	static const struct ich_reg_info ali_regs[6] = {
   2900		{ ALI_INT_PCMIN, 0x40 },
   2901		{ ALI_INT_PCMOUT, 0x50 },
   2902		{ ALI_INT_MICIN, 0x60 },
   2903		{ ALI_INT_CODECSPDIFOUT, 0x70 },
   2904		{ ALI_INT_SPDIFIN, 0xa0 },
   2905		{ ALI_INT_SPDIFOUT, 0xb0 },
   2906	};
   2907	const struct ich_reg_info *tbl;
   2908
   2909	err = pcim_enable_device(pci);
   2910	if (err < 0)
   2911		return err;
   2912
   2913	spin_lock_init(&chip->reg_lock);
   2914	chip->device_type = device_type;
   2915	chip->card = card;
   2916	chip->pci = pci;
   2917	chip->irq = -1;
   2918
   2919	/* module parameters */
   2920	chip->buggy_irq = buggy_irq;
   2921	chip->buggy_semaphore = buggy_semaphore;
   2922	if (xbox)
   2923		chip->xbox = 1;
   2924
   2925	chip->inside_vm = snd_intel8x0_inside_vm(pci);
   2926
   2927	/*
   2928	 * Intel 82443MX running a 100MHz processor system bus has a hardware
   2929	 * bug, which aborts PCI busmaster for audio transfer.  A workaround
   2930	 * is to set the pages as non-cached.  For details, see the errata in
   2931	 *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
   2932	 */
   2933	if (pci->vendor == PCI_VENDOR_ID_INTEL &&
   2934	    pci->device == PCI_DEVICE_ID_INTEL_440MX)
   2935		chip->fix_nocache = 1; /* enable workaround */
   2936
   2937	err = pci_request_regions(pci, card->shortname);
   2938	if (err < 0)
   2939		return err;
   2940
   2941	if (device_type == DEVICE_ALI) {
   2942		/* ALI5455 has no ac97 region */
   2943		chip->bmaddr = pcim_iomap(pci, 0, 0);
   2944	} else {
   2945		if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
   2946			chip->addr = pcim_iomap(pci, 2, 0);
   2947		else
   2948			chip->addr = pcim_iomap(pci, 0, 0);
   2949		if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
   2950			chip->bmaddr = pcim_iomap(pci, 3, 0);
   2951		else
   2952			chip->bmaddr = pcim_iomap(pci, 1, 0);
   2953	}
   2954
   2955	chip->bdbars_count = bdbars[device_type];
   2956
   2957	/* initialize offsets */
   2958	switch (device_type) {
   2959	case DEVICE_NFORCE:
   2960		tbl = nforce_regs;
   2961		break;
   2962	case DEVICE_ALI:
   2963		tbl = ali_regs;
   2964		break;
   2965	default:
   2966		tbl = intel_regs;
   2967		break;
   2968	}
   2969	for (i = 0; i < chip->bdbars_count; i++) {
   2970		ichdev = &chip->ichd[i];
   2971		ichdev->ichd = i;
   2972		ichdev->reg_offset = tbl[i].offset;
   2973		ichdev->int_sta_mask = tbl[i].int_sta_mask;
   2974		if (device_type == DEVICE_SIS) {
   2975			/* SiS 7012 swaps the registers */
   2976			ichdev->roff_sr = ICH_REG_OFF_PICB;
   2977			ichdev->roff_picb = ICH_REG_OFF_SR;
   2978		} else {
   2979			ichdev->roff_sr = ICH_REG_OFF_SR;
   2980			ichdev->roff_picb = ICH_REG_OFF_PICB;
   2981		}
   2982		if (device_type == DEVICE_ALI)
   2983			ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
   2984		/* SIS7012 handles the pcm data in bytes, others are in samples */
   2985		ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
   2986	}
   2987
   2988	/* allocate buffer descriptor lists */
   2989	/* the start of each lists must be aligned to 8 bytes */
   2990	chip->bdbars = snd_devm_alloc_pages(&pci->dev, intel8x0_dma_type(chip),
   2991					    chip->bdbars_count * sizeof(u32) *
   2992					    ICH_MAX_FRAGS * 2);
   2993	if (!chip->bdbars)
   2994		return -ENOMEM;
   2995
   2996	/* tables must be aligned to 8 bytes here, but the kernel pages
   2997	   are much bigger, so we don't care (on i386) */
   2998	int_sta_masks = 0;
   2999	for (i = 0; i < chip->bdbars_count; i++) {
   3000		ichdev = &chip->ichd[i];
   3001		ichdev->bdbar = ((__le32 *)chip->bdbars->area) +
   3002			(i * ICH_MAX_FRAGS * 2);
   3003		ichdev->bdbar_addr = chip->bdbars->addr +
   3004			(i * sizeof(u32) * ICH_MAX_FRAGS * 2);
   3005		int_sta_masks |= ichdev->int_sta_mask;
   3006	}
   3007	chip->int_sta_reg = device_type == DEVICE_ALI ?
   3008		ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
   3009	chip->int_sta_mask = int_sta_masks;
   3010
   3011	pci_set_master(pci);
   3012
   3013	switch(chip->device_type) {
   3014	case DEVICE_INTEL_ICH4:
   3015		/* ICH4 can have three codecs */
   3016		chip->max_codecs = 3;
   3017		chip->codec_bit = ich_codec_bits;
   3018		chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
   3019		break;
   3020	case DEVICE_SIS:
   3021		/* recent SIS7012 can have three codecs */
   3022		chip->max_codecs = 3;
   3023		chip->codec_bit = sis_codec_bits;
   3024		chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
   3025		break;
   3026	default:
   3027		/* others up to two codecs */
   3028		chip->max_codecs = 2;
   3029		chip->codec_bit = ich_codec_bits;
   3030		chip->codec_ready_bits = ICH_PRI | ICH_SRI;
   3031		break;
   3032	}
   3033	for (i = 0; i < chip->max_codecs; i++)
   3034		chip->codec_isr_bits |= chip->codec_bit[i];
   3035
   3036	err = snd_intel8x0_chip_init(chip, 1);
   3037	if (err < 0)
   3038		return err;
   3039
   3040	/* request irq after initializaing int_sta_mask, etc */
   3041	/* NOTE: we don't use devm version here since it's released /
   3042	 * re-acquired in PM callbacks.
   3043	 * It's released explicitly in snd_intel8x0_free(), too.
   3044	 */
   3045	if (request_irq(pci->irq, snd_intel8x0_interrupt,
   3046			IRQF_SHARED, KBUILD_MODNAME, chip)) {
   3047		dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
   3048		return -EBUSY;
   3049	}
   3050	chip->irq = pci->irq;
   3051	card->sync_irq = chip->irq;
   3052
   3053	card->private_free = snd_intel8x0_free;
   3054
   3055	return 0;
   3056}
   3057
   3058static struct shortname_table {
   3059	unsigned int id;
   3060	const char *s;
   3061} shortnames[] = {
   3062	{ PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
   3063	{ PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
   3064	{ PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
   3065	{ PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
   3066	{ PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
   3067	{ PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
   3068	{ PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
   3069	{ PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
   3070	{ PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
   3071	{ PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
   3072	{ PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
   3073	{ PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
   3074	{ PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
   3075	{ PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
   3076	{ PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
   3077	{ PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
   3078	{ PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
   3079	{ PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
   3080	{ 0x003a, "NVidia MCP04" },
   3081	{ 0x746d, "AMD AMD8111" },
   3082	{ 0x7445, "AMD AMD768" },
   3083	{ 0x5455, "ALi M5455" },
   3084	{ 0, NULL },
   3085};
   3086
   3087static const struct snd_pci_quirk spdif_aclink_defaults[] = {
   3088	SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
   3089	{ } /* end */
   3090};
   3091
   3092/* look up allow/deny list for SPDIF over ac-link */
   3093static int check_default_spdif_aclink(struct pci_dev *pci)
   3094{
   3095	const struct snd_pci_quirk *w;
   3096
   3097	w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
   3098	if (w) {
   3099		if (w->value)
   3100			dev_dbg(&pci->dev,
   3101				"Using SPDIF over AC-Link for %s\n",
   3102				    snd_pci_quirk_name(w));
   3103		else
   3104			dev_dbg(&pci->dev,
   3105				"Using integrated SPDIF DMA for %s\n",
   3106				    snd_pci_quirk_name(w));
   3107		return w->value;
   3108	}
   3109	return 0;
   3110}
   3111
   3112static int __snd_intel8x0_probe(struct pci_dev *pci,
   3113				const struct pci_device_id *pci_id)
   3114{
   3115	struct snd_card *card;
   3116	struct intel8x0 *chip;
   3117	int err;
   3118	struct shortname_table *name;
   3119
   3120	err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
   3121				sizeof(*chip), &card);
   3122	if (err < 0)
   3123		return err;
   3124	chip = card->private_data;
   3125
   3126	if (spdif_aclink < 0)
   3127		spdif_aclink = check_default_spdif_aclink(pci);
   3128
   3129	strcpy(card->driver, "ICH");
   3130	if (!spdif_aclink) {
   3131		switch (pci_id->driver_data) {
   3132		case DEVICE_NFORCE:
   3133			strcpy(card->driver, "NFORCE");
   3134			break;
   3135		case DEVICE_INTEL_ICH4:
   3136			strcpy(card->driver, "ICH4");
   3137		}
   3138	}
   3139
   3140	strcpy(card->shortname, "Intel ICH");
   3141	for (name = shortnames; name->id; name++) {
   3142		if (pci->device == name->id) {
   3143			strcpy(card->shortname, name->s);
   3144			break;
   3145		}
   3146	}
   3147
   3148	if (buggy_irq < 0) {
   3149		/* some Nforce[2] and ICH boards have problems with IRQ handling.
   3150		 * Needs to return IRQ_HANDLED for unknown irqs.
   3151		 */
   3152		if (pci_id->driver_data == DEVICE_NFORCE)
   3153			buggy_irq = 1;
   3154		else
   3155			buggy_irq = 0;
   3156	}
   3157
   3158	err = snd_intel8x0_init(card, pci, pci_id->driver_data);
   3159	if (err < 0)
   3160		return err;
   3161
   3162	err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk);
   3163	if (err < 0)
   3164		return err;
   3165	err = snd_intel8x0_pcm(chip);
   3166	if (err < 0)
   3167		return err;
   3168	
   3169	snd_intel8x0_proc_init(chip);
   3170
   3171	snprintf(card->longname, sizeof(card->longname),
   3172		 "%s with %s at irq %i", card->shortname,
   3173		 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
   3174
   3175	if (ac97_clock == 0 || ac97_clock == 1) {
   3176		if (ac97_clock == 0) {
   3177			if (intel8x0_in_clock_list(chip) == 0)
   3178				intel8x0_measure_ac97_clock(chip);
   3179		} else {
   3180			intel8x0_measure_ac97_clock(chip);
   3181		}
   3182	}
   3183
   3184	err = snd_card_register(card);
   3185	if (err < 0)
   3186		return err;
   3187
   3188	pci_set_drvdata(pci, card);
   3189	return 0;
   3190}
   3191
   3192static int snd_intel8x0_probe(struct pci_dev *pci,
   3193			      const struct pci_device_id *pci_id)
   3194{
   3195	return snd_card_free_on_error(&pci->dev, __snd_intel8x0_probe(pci, pci_id));
   3196}
   3197
   3198static struct pci_driver intel8x0_driver = {
   3199	.name = KBUILD_MODNAME,
   3200	.id_table = snd_intel8x0_ids,
   3201	.probe = snd_intel8x0_probe,
   3202	.driver = {
   3203		.pm = INTEL8X0_PM_OPS,
   3204	},
   3205};
   3206
   3207module_pci_driver(intel8x0_driver);