cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cs4398.h (2007B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* register 1 */
      3#define CS4398_REV_MASK		0x07
      4#define CS4398_PART_MASK	0xf8
      5#define CS4398_PART_CS4398	0x70
      6/* register 2 */
      7#define CS4398_FM_MASK		0x03
      8#define CS4398_FM_SINGLE	0x00
      9#define CS4398_FM_DOUBLE	0x01
     10#define CS4398_FM_QUAD		0x02
     11#define CS4398_FM_DSD		0x03
     12#define CS4398_DEM_MASK		0x0c
     13#define CS4398_DEM_NONE		0x00
     14#define CS4398_DEM_44100	0x04
     15#define CS4398_DEM_48000	0x08
     16#define CS4398_DEM_32000	0x0c
     17#define CS4398_DIF_MASK		0x70
     18#define CS4398_DIF_LJUST	0x00
     19#define CS4398_DIF_I2S		0x10
     20#define CS4398_DIF_RJUST_16	0x20
     21#define CS4398_DIF_RJUST_24	0x30
     22#define CS4398_DIF_RJUST_20	0x40
     23#define CS4398_DIF_RJUST_18	0x50
     24#define CS4398_DSD_SRC		0x80
     25/* register 3 */
     26#define CS4398_ATAPI_MASK	0x1f
     27#define CS4398_ATAPI_B_MUTE	0x00
     28#define CS4398_ATAPI_B_R	0x01
     29#define CS4398_ATAPI_B_L	0x02
     30#define CS4398_ATAPI_B_LR	0x03
     31#define CS4398_ATAPI_A_MUTE	0x00
     32#define CS4398_ATAPI_A_R	0x04
     33#define CS4398_ATAPI_A_L	0x08
     34#define CS4398_ATAPI_A_LR	0x0c
     35#define CS4398_ATAPI_MIX_LR_VOL	0x10
     36#define CS4398_INVERT_B		0x20
     37#define CS4398_INVERT_A		0x40
     38#define CS4398_VOL_B_EQ_A	0x80
     39/* register 4 */
     40#define CS4398_MUTEP_MASK	0x03
     41#define CS4398_MUTEP_AUTO	0x00
     42#define CS4398_MUTEP_LOW	0x02
     43#define CS4398_MUTEP_HIGH	0x03
     44#define CS4398_MUTE_B		0x08
     45#define CS4398_MUTE_A		0x10
     46#define CS4398_MUTEC_A_EQ_B	0x20
     47#define CS4398_DAMUTE		0x40
     48#define CS4398_PAMUTE		0x80
     49/* register 5 */
     50#define CS4398_VOL_A_MASK	0xff
     51/* register 6 */
     52#define CS4398_VOL_B_MASK	0xff
     53/* register 7 */
     54#define CS4398_DIR_DSD		0x01
     55#define CS4398_FILT_SEL		0x04
     56#define CS4398_RMP_DN		0x10
     57#define CS4398_RMP_UP		0x20
     58#define CS4398_ZERO_CROSS	0x40
     59#define CS4398_SOFT_RAMP	0x80
     60/* register 8 */
     61#define CS4398_MCLKDIV3		0x08
     62#define CS4398_MCLKDIV2		0x10
     63#define CS4398_FREEZE		0x20
     64#define CS4398_CPEN		0x40
     65#define CS4398_PDN		0x80
     66/* register 9 */
     67#define CS4398_DSD_PM_EN	0x01
     68#define CS4398_DSD_PM_MODE	0x02
     69#define CS4398_INVALID_DSD	0x04
     70#define CS4398_STATIC_DSD	0x08