cs35l41-lib.c - cachepc-linux - Fork of AMDESE/linux with modifications for CachePC side-channel attack

	cachepc-linux Fork of AMDESE/linux with modifications for CachePC side-channel attack
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cs35l41-lib.c (42025B)
      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// cs35l41-lib.c -- CS35L41 Common functions for HDA and ASoC Audio drivers
      4//
      5// Copyright 2017-2021 Cirrus Logic, Inc.
      6//
      7// Author: David Rhodes <david.rhodes@cirrus.com>
      8// Author: Lucas Tanure <lucas.tanure@cirrus.com>
      9
     10#include <linux/dev_printk.h>
     11#include <linux/module.h>
     12#include <linux/regmap.h>
     13#include <linux/regulator/consumer.h>
     14#include <linux/slab.h>
     15#include <linux/firmware/cirrus/wmfw.h>
     16
     17#include <sound/cs35l41.h>
     18
     19static const struct reg_default cs35l41_reg[] = {
     20	{ CS35L41_PWR_CTRL1,			0x00000000 },
     21	{ CS35L41_PWR_CTRL2,			0x00000000 },
     22	{ CS35L41_PWR_CTRL3,			0x01000010 },
     23	{ CS35L41_GPIO_PAD_CONTROL,		0x00000000 },
     24	{ CS35L41_GLOBAL_CLK_CTRL,		0x00000003 },
     25	{ CS35L41_TST_FS_MON0,			0x00020016 },
     26	{ CS35L41_BSTCVRT_COEFF,		0x00002424 },
     27	{ CS35L41_BSTCVRT_SLOPE_LBST,		0x00007500 },
     28	{ CS35L41_BSTCVRT_PEAK_CUR,		0x0000004A },
     29	{ CS35L41_SP_ENABLES,			0x00000000 },
     30	{ CS35L41_SP_RATE_CTRL,			0x00000028 },
     31	{ CS35L41_SP_FORMAT,			0x18180200 },
     32	{ CS35L41_SP_HIZ_CTRL,			0x00000002 },
     33	{ CS35L41_SP_FRAME_TX_SLOT,		0x03020100 },
     34	{ CS35L41_SP_FRAME_RX_SLOT,		0x00000100 },
     35	{ CS35L41_SP_TX_WL,			0x00000018 },
     36	{ CS35L41_SP_RX_WL,			0x00000018 },
     37	{ CS35L41_DAC_PCM1_SRC,			0x00000008 },
     38	{ CS35L41_ASP_TX1_SRC,			0x00000018 },
     39	{ CS35L41_ASP_TX2_SRC,			0x00000019 },
     40	{ CS35L41_ASP_TX3_SRC,			0x00000000 },
     41	{ CS35L41_ASP_TX4_SRC,			0x00000000 },
     42	{ CS35L41_DSP1_RX1_SRC,			0x00000008 },
     43	{ CS35L41_DSP1_RX2_SRC,			0x00000009 },
     44	{ CS35L41_DSP1_RX3_SRC,			0x00000018 },
     45	{ CS35L41_DSP1_RX4_SRC,			0x00000019 },
     46	{ CS35L41_DSP1_RX5_SRC,			0x00000020 },
     47	{ CS35L41_DSP1_RX6_SRC,			0x00000021 },
     48	{ CS35L41_DSP1_RX7_SRC,			0x0000003A },
     49	{ CS35L41_DSP1_RX8_SRC,			0x00000001 },
     50	{ CS35L41_NGATE1_SRC,			0x00000008 },
     51	{ CS35L41_NGATE2_SRC,			0x00000009 },
     52	{ CS35L41_AMP_DIG_VOL_CTRL,		0x00008000 },
     53	{ CS35L41_CLASSH_CFG,			0x000B0405 },
     54	{ CS35L41_WKFET_CFG,			0x00000111 },
     55	{ CS35L41_NG_CFG,			0x00000033 },
     56	{ CS35L41_AMP_GAIN_CTRL,		0x00000000 },
     57	{ CS35L41_IRQ1_MASK1,			0xFFFFFFFF },
     58	{ CS35L41_IRQ1_MASK2,			0xFFFFFFFF },
     59	{ CS35L41_IRQ1_MASK3,			0xFFFF87FF },
     60	{ CS35L41_IRQ1_MASK4,			0xFEFFFFFF },
     61	{ CS35L41_GPIO1_CTRL1,			0xE1000001 },
     62	{ CS35L41_GPIO2_CTRL1,			0xE1000001 },
     63	{ CS35L41_MIXER_NGATE_CFG,		0x00000000 },
     64	{ CS35L41_MIXER_NGATE_CH1_CFG,		0x00000303 },
     65	{ CS35L41_MIXER_NGATE_CH2_CFG,		0x00000303 },
     66	{ CS35L41_DSP1_CCM_CORE_CTRL,		0x00000101 },
     67};
     68
     69static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
     70{
     71	switch (reg) {
     72	case CS35L41_DEVID:
     73	case CS35L41_REVID:
     74	case CS35L41_FABID:
     75	case CS35L41_RELID:
     76	case CS35L41_OTPID:
     77	case CS35L41_TEST_KEY_CTL:
     78	case CS35L41_USER_KEY_CTL:
     79	case CS35L41_OTP_CTRL0:
     80	case CS35L41_OTP_CTRL3:
     81	case CS35L41_OTP_CTRL4:
     82	case CS35L41_OTP_CTRL5:
     83	case CS35L41_OTP_CTRL6:
     84	case CS35L41_OTP_CTRL7:
     85	case CS35L41_OTP_CTRL8:
     86	case CS35L41_PWR_CTRL1:
     87	case CS35L41_PWR_CTRL2:
     88	case CS35L41_PWR_CTRL3:
     89	case CS35L41_CTRL_OVRRIDE:
     90	case CS35L41_AMP_OUT_MUTE:
     91	case CS35L41_PROTECT_REL_ERR_IGN:
     92	case CS35L41_GPIO_PAD_CONTROL:
     93	case CS35L41_JTAG_CONTROL:
     94	case CS35L41_PWRMGT_CTL:
     95	case CS35L41_WAKESRC_CTL:
     96	case CS35L41_PWRMGT_STS:
     97	case CS35L41_PLL_CLK_CTRL:
     98	case CS35L41_DSP_CLK_CTRL:
     99	case CS35L41_GLOBAL_CLK_CTRL:
    100	case CS35L41_DATA_FS_SEL:
    101	case CS35L41_TST_FS_MON0:
    102	case CS35L41_MDSYNC_EN:
    103	case CS35L41_MDSYNC_TX_ID:
    104	case CS35L41_MDSYNC_PWR_CTRL:
    105	case CS35L41_MDSYNC_DATA_TX:
    106	case CS35L41_MDSYNC_TX_STATUS:
    107	case CS35L41_MDSYNC_DATA_RX:
    108	case CS35L41_MDSYNC_RX_STATUS:
    109	case CS35L41_MDSYNC_ERR_STATUS:
    110	case CS35L41_MDSYNC_SYNC_PTE2:
    111	case CS35L41_MDSYNC_SYNC_PTE3:
    112	case CS35L41_MDSYNC_SYNC_MSM_STATUS:
    113	case CS35L41_BSTCVRT_VCTRL1:
    114	case CS35L41_BSTCVRT_VCTRL2:
    115	case CS35L41_BSTCVRT_PEAK_CUR:
    116	case CS35L41_BSTCVRT_SFT_RAMP:
    117	case CS35L41_BSTCVRT_COEFF:
    118	case CS35L41_BSTCVRT_SLOPE_LBST:
    119	case CS35L41_BSTCVRT_SW_FREQ:
    120	case CS35L41_BSTCVRT_DCM_CTRL:
    121	case CS35L41_BSTCVRT_DCM_MODE_FORCE:
    122	case CS35L41_BSTCVRT_OVERVOLT_CTRL:
    123	case CS35L41_VI_VOL_POL:
    124	case CS35L41_DTEMP_WARN_THLD:
    125	case CS35L41_DTEMP_CFG:
    126	case CS35L41_DTEMP_EN:
    127	case CS35L41_VPVBST_FS_SEL:
    128	case CS35L41_SP_ENABLES:
    129	case CS35L41_SP_RATE_CTRL:
    130	case CS35L41_SP_FORMAT:
    131	case CS35L41_SP_HIZ_CTRL:
    132	case CS35L41_SP_FRAME_TX_SLOT:
    133	case CS35L41_SP_FRAME_RX_SLOT:
    134	case CS35L41_SP_TX_WL:
    135	case CS35L41_SP_RX_WL:
    136	case CS35L41_DAC_PCM1_SRC:
    137	case CS35L41_ASP_TX1_SRC:
    138	case CS35L41_ASP_TX2_SRC:
    139	case CS35L41_ASP_TX3_SRC:
    140	case CS35L41_ASP_TX4_SRC:
    141	case CS35L41_DSP1_RX1_SRC:
    142	case CS35L41_DSP1_RX2_SRC:
    143	case CS35L41_DSP1_RX3_SRC:
    144	case CS35L41_DSP1_RX4_SRC:
    145	case CS35L41_DSP1_RX5_SRC:
    146	case CS35L41_DSP1_RX6_SRC:
    147	case CS35L41_DSP1_RX7_SRC:
    148	case CS35L41_DSP1_RX8_SRC:
    149	case CS35L41_NGATE1_SRC:
    150	case CS35L41_NGATE2_SRC:
    151	case CS35L41_AMP_DIG_VOL_CTRL:
    152	case CS35L41_VPBR_CFG:
    153	case CS35L41_VBBR_CFG:
    154	case CS35L41_VPBR_STATUS:
    155	case CS35L41_VBBR_STATUS:
    156	case CS35L41_OVERTEMP_CFG:
    157	case CS35L41_AMP_ERR_VOL:
    158	case CS35L41_VOL_STATUS_TO_DSP:
    159	case CS35L41_CLASSH_CFG:
    160	case CS35L41_WKFET_CFG:
    161	case CS35L41_NG_CFG:
    162	case CS35L41_AMP_GAIN_CTRL:
    163	case CS35L41_DAC_MSM_CFG:
    164	case CS35L41_IRQ1_CFG:
    165	case CS35L41_IRQ1_STATUS:
    166	case CS35L41_IRQ1_STATUS1:
    167	case CS35L41_IRQ1_STATUS2:
    168	case CS35L41_IRQ1_STATUS3:
    169	case CS35L41_IRQ1_STATUS4:
    170	case CS35L41_IRQ1_RAW_STATUS1:
    171	case CS35L41_IRQ1_RAW_STATUS2:
    172	case CS35L41_IRQ1_RAW_STATUS3:
    173	case CS35L41_IRQ1_RAW_STATUS4:
    174	case CS35L41_IRQ1_MASK1:
    175	case CS35L41_IRQ1_MASK2:
    176	case CS35L41_IRQ1_MASK3:
    177	case CS35L41_IRQ1_MASK4:
    178	case CS35L41_IRQ1_FRC1:
    179	case CS35L41_IRQ1_FRC2:
    180	case CS35L41_IRQ1_FRC3:
    181	case CS35L41_IRQ1_FRC4:
    182	case CS35L41_IRQ1_EDGE1:
    183	case CS35L41_IRQ1_EDGE4:
    184	case CS35L41_IRQ1_POL1:
    185	case CS35L41_IRQ1_POL2:
    186	case CS35L41_IRQ1_POL3:
    187	case CS35L41_IRQ1_POL4:
    188	case CS35L41_IRQ1_DB3:
    189	case CS35L41_IRQ2_CFG:
    190	case CS35L41_IRQ2_STATUS:
    191	case CS35L41_IRQ2_STATUS1:
    192	case CS35L41_IRQ2_STATUS2:
    193	case CS35L41_IRQ2_STATUS3:
    194	case CS35L41_IRQ2_STATUS4:
    195	case CS35L41_IRQ2_RAW_STATUS1:
    196	case CS35L41_IRQ2_RAW_STATUS2:
    197	case CS35L41_IRQ2_RAW_STATUS3:
    198	case CS35L41_IRQ2_RAW_STATUS4:
    199	case CS35L41_IRQ2_MASK1:
    200	case CS35L41_IRQ2_MASK2:
    201	case CS35L41_IRQ2_MASK3:
    202	case CS35L41_IRQ2_MASK4:
    203	case CS35L41_IRQ2_FRC1:
    204	case CS35L41_IRQ2_FRC2:
    205	case CS35L41_IRQ2_FRC3:
    206	case CS35L41_IRQ2_FRC4:
    207	case CS35L41_IRQ2_EDGE1:
    208	case CS35L41_IRQ2_EDGE4:
    209	case CS35L41_IRQ2_POL1:
    210	case CS35L41_IRQ2_POL2:
    211	case CS35L41_IRQ2_POL3:
    212	case CS35L41_IRQ2_POL4:
    213	case CS35L41_IRQ2_DB3:
    214	case CS35L41_GPIO_STATUS1:
    215	case CS35L41_GPIO1_CTRL1:
    216	case CS35L41_GPIO2_CTRL1:
    217	case CS35L41_MIXER_NGATE_CFG:
    218	case CS35L41_MIXER_NGATE_CH1_CFG:
    219	case CS35L41_MIXER_NGATE_CH2_CFG:
    220	case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
    221	case CS35L41_CLOCK_DETECT_1:
    222	case CS35L41_DIE_STS1:
    223	case CS35L41_DIE_STS2:
    224	case CS35L41_TEMP_CAL1:
    225	case CS35L41_TEMP_CAL2:
    226	case CS35L41_DSP1_TIMESTAMP_COUNT:
    227	case CS35L41_DSP1_SYS_ID:
    228	case CS35L41_DSP1_SYS_VERSION:
    229	case CS35L41_DSP1_SYS_CORE_ID:
    230	case CS35L41_DSP1_SYS_AHB_ADDR:
    231	case CS35L41_DSP1_SYS_XSRAM_SIZE:
    232	case CS35L41_DSP1_SYS_YSRAM_SIZE:
    233	case CS35L41_DSP1_SYS_PSRAM_SIZE:
    234	case CS35L41_DSP1_SYS_PM_BOOT_SIZE:
    235	case CS35L41_DSP1_SYS_FEATURES:
    236	case CS35L41_DSP1_SYS_FIR_FILTERS:
    237	case CS35L41_DSP1_SYS_LMS_FILTERS:
    238	case CS35L41_DSP1_SYS_XM_BANK_SIZE:
    239	case CS35L41_DSP1_SYS_YM_BANK_SIZE:
    240	case CS35L41_DSP1_SYS_PM_BANK_SIZE:
    241	case CS35L41_DSP1_RX1_RATE:
    242	case CS35L41_DSP1_RX2_RATE:
    243	case CS35L41_DSP1_RX3_RATE:
    244	case CS35L41_DSP1_RX4_RATE:
    245	case CS35L41_DSP1_RX5_RATE:
    246	case CS35L41_DSP1_RX6_RATE:
    247	case CS35L41_DSP1_RX7_RATE:
    248	case CS35L41_DSP1_RX8_RATE:
    249	case CS35L41_DSP1_TX1_RATE:
    250	case CS35L41_DSP1_TX2_RATE:
    251	case CS35L41_DSP1_TX3_RATE:
    252	case CS35L41_DSP1_TX4_RATE:
    253	case CS35L41_DSP1_TX5_RATE:
    254	case CS35L41_DSP1_TX6_RATE:
    255	case CS35L41_DSP1_TX7_RATE:
    256	case CS35L41_DSP1_TX8_RATE:
    257	case CS35L41_DSP1_SCRATCH1:
    258	case CS35L41_DSP1_SCRATCH2:
    259	case CS35L41_DSP1_SCRATCH3:
    260	case CS35L41_DSP1_SCRATCH4:
    261	case CS35L41_DSP1_CCM_CORE_CTRL:
    262	case CS35L41_DSP1_CCM_CLK_OVERRIDE:
    263	case CS35L41_DSP1_XM_MSTR_EN:
    264	case CS35L41_DSP1_XM_CORE_PRI:
    265	case CS35L41_DSP1_XM_AHB_PACK_PL_PRI:
    266	case CS35L41_DSP1_XM_AHB_UP_PL_PRI:
    267	case CS35L41_DSP1_XM_ACCEL_PL0_PRI:
    268	case CS35L41_DSP1_XM_NPL0_PRI:
    269	case CS35L41_DSP1_YM_MSTR_EN:
    270	case CS35L41_DSP1_YM_CORE_PRI:
    271	case CS35L41_DSP1_YM_AHB_PACK_PL_PRI:
    272	case CS35L41_DSP1_YM_AHB_UP_PL_PRI:
    273	case CS35L41_DSP1_YM_ACCEL_PL0_PRI:
    274	case CS35L41_DSP1_YM_NPL0_PRI:
    275	case CS35L41_DSP1_MPU_XM_ACCESS0:
    276	case CS35L41_DSP1_MPU_YM_ACCESS0:
    277	case CS35L41_DSP1_MPU_WNDW_ACCESS0:
    278	case CS35L41_DSP1_MPU_XREG_ACCESS0:
    279	case CS35L41_DSP1_MPU_YREG_ACCESS0:
    280	case CS35L41_DSP1_MPU_XM_ACCESS1:
    281	case CS35L41_DSP1_MPU_YM_ACCESS1:
    282	case CS35L41_DSP1_MPU_WNDW_ACCESS1:
    283	case CS35L41_DSP1_MPU_XREG_ACCESS1:
    284	case CS35L41_DSP1_MPU_YREG_ACCESS1:
    285	case CS35L41_DSP1_MPU_XM_ACCESS2:
    286	case CS35L41_DSP1_MPU_YM_ACCESS2:
    287	case CS35L41_DSP1_MPU_WNDW_ACCESS2:
    288	case CS35L41_DSP1_MPU_XREG_ACCESS2:
    289	case CS35L41_DSP1_MPU_YREG_ACCESS2:
    290	case CS35L41_DSP1_MPU_XM_ACCESS3:
    291	case CS35L41_DSP1_MPU_YM_ACCESS3:
    292	case CS35L41_DSP1_MPU_WNDW_ACCESS3:
    293	case CS35L41_DSP1_MPU_XREG_ACCESS3:
    294	case CS35L41_DSP1_MPU_YREG_ACCESS3:
    295	case CS35L41_DSP1_MPU_XM_VIO_ADDR:
    296	case CS35L41_DSP1_MPU_XM_VIO_STATUS:
    297	case CS35L41_DSP1_MPU_YM_VIO_ADDR:
    298	case CS35L41_DSP1_MPU_YM_VIO_STATUS:
    299	case CS35L41_DSP1_MPU_PM_VIO_ADDR:
    300	case CS35L41_DSP1_MPU_PM_VIO_STATUS:
    301	case CS35L41_DSP1_MPU_LOCK_CONFIG:
    302	case CS35L41_DSP1_MPU_WDT_RST_CTRL:
    303	case CS35L41_OTP_TRIM_1:
    304	case CS35L41_OTP_TRIM_2:
    305	case CS35L41_OTP_TRIM_3:
    306	case CS35L41_OTP_TRIM_4:
    307	case CS35L41_OTP_TRIM_5:
    308	case CS35L41_OTP_TRIM_6:
    309	case CS35L41_OTP_TRIM_7:
    310	case CS35L41_OTP_TRIM_8:
    311	case CS35L41_OTP_TRIM_9:
    312	case CS35L41_OTP_TRIM_10:
    313	case CS35L41_OTP_TRIM_11:
    314	case CS35L41_OTP_TRIM_12:
    315	case CS35L41_OTP_TRIM_13:
    316	case CS35L41_OTP_TRIM_14:
    317	case CS35L41_OTP_TRIM_15:
    318	case CS35L41_OTP_TRIM_16:
    319	case CS35L41_OTP_TRIM_17:
    320	case CS35L41_OTP_TRIM_18:
    321	case CS35L41_OTP_TRIM_19:
    322	case CS35L41_OTP_TRIM_20:
    323	case CS35L41_OTP_TRIM_21:
    324	case CS35L41_OTP_TRIM_22:
    325	case CS35L41_OTP_TRIM_23:
    326	case CS35L41_OTP_TRIM_24:
    327	case CS35L41_OTP_TRIM_25:
    328	case CS35L41_OTP_TRIM_26:
    329	case CS35L41_OTP_TRIM_27:
    330	case CS35L41_OTP_TRIM_28:
    331	case CS35L41_OTP_TRIM_29:
    332	case CS35L41_OTP_TRIM_30:
    333	case CS35L41_OTP_TRIM_31:
    334	case CS35L41_OTP_TRIM_32:
    335	case CS35L41_OTP_TRIM_33:
    336	case CS35L41_OTP_TRIM_34:
    337	case CS35L41_OTP_TRIM_35:
    338	case CS35L41_OTP_TRIM_36:
    339	case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
    340	case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
    341	case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
    342	case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
    343	case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
    344	case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
    345	case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
    346	case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
    347	/*test regs*/
    348	case CS35L41_PLL_OVR:
    349	case CS35L41_BST_TEST_DUTY:
    350	case CS35L41_DIGPWM_IOCTRL:
    351		return true;
    352	default:
    353		return false;
    354	}
    355}
    356
    357static bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
    358{
    359	switch (reg) {
    360	case CS35L41_TEST_KEY_CTL:
    361	case CS35L41_USER_KEY_CTL:
    362	case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
    363	case CS35L41_TST_FS_MON0:
    364	case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
    365	case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
    366	case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
    367		return true;
    368	default:
    369		return false;
    370	}
    371}
    372
    373static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
    374{
    375	switch (reg) {
    376	case CS35L41_DEVID:
    377	case CS35L41_SFT_RESET:
    378	case CS35L41_FABID:
    379	case CS35L41_REVID:
    380	case CS35L41_OTPID:
    381	case CS35L41_TEST_KEY_CTL:
    382	case CS35L41_USER_KEY_CTL:
    383	case CS35L41_PWRMGT_CTL:
    384	case CS35L41_WAKESRC_CTL:
    385	case CS35L41_PWRMGT_STS:
    386	case CS35L41_DTEMP_EN:
    387	case CS35L41_IRQ1_STATUS:
    388	case CS35L41_IRQ1_STATUS1:
    389	case CS35L41_IRQ1_STATUS2:
    390	case CS35L41_IRQ1_STATUS3:
    391	case CS35L41_IRQ1_STATUS4:
    392	case CS35L41_IRQ1_RAW_STATUS1:
    393	case CS35L41_IRQ1_RAW_STATUS2:
    394	case CS35L41_IRQ1_RAW_STATUS3:
    395	case CS35L41_IRQ1_RAW_STATUS4:
    396	case CS35L41_IRQ2_STATUS:
    397	case CS35L41_IRQ2_STATUS1:
    398	case CS35L41_IRQ2_STATUS2:
    399	case CS35L41_IRQ2_STATUS3:
    400	case CS35L41_IRQ2_STATUS4:
    401	case CS35L41_IRQ2_RAW_STATUS1:
    402	case CS35L41_IRQ2_RAW_STATUS2:
    403	case CS35L41_IRQ2_RAW_STATUS3:
    404	case CS35L41_IRQ2_RAW_STATUS4:
    405	case CS35L41_GPIO_STATUS1:
    406	case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
    407	case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
    408	case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
    409	case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093:
    410	case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
    411	case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
    412	case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
    413	case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
    414	case CS35L41_DSP1_SCRATCH1:
    415	case CS35L41_DSP1_SCRATCH2:
    416	case CS35L41_DSP1_SCRATCH3:
    417	case CS35L41_DSP1_SCRATCH4:
    418	case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS:
    419	case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
    420		return true;
    421	default:
    422		return false;
    423	}
    424}
    425
    426static const struct cs35l41_otp_packed_element_t otp_map_1[] = {
    427	/* addr         shift   size */
    428	{ 0x00002030,	0,	4 }, /*TRIM_OSC_FREQ_TRIM*/
    429	{ 0x00002030,	7,	1 }, /*TRIM_OSC_TRIM_DONE*/
    430	{ 0x0000208c,	24,	6 }, /*TST_DIGREG_VREF_TRIM*/
    431	{ 0x00002090,	14,	4 }, /*TST_REF_TRIM*/
    432	{ 0x00002090,	10,	4 }, /*TST_REF_TEMPCO_TRIM*/
    433	{ 0x0000300C,	11,	4 }, /*PLL_LDOA_TST_VREF_TRIM*/
    434	{ 0x0000394C,	23,	2 }, /*BST_ATEST_CM_VOFF*/
    435	{ 0x00003950,	0,	7 }, /*BST_ATRIM_IADC_OFFSET*/
    436	{ 0x00003950,	8,	7 }, /*BST_ATRIM_IADC_GAIN1*/
    437	{ 0x00003950,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
    438	{ 0x00003950,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
    439	{ 0x00003954,	0,	7 }, /*BST_ATRIM_IADC_OFFSET2*/
    440	{ 0x00003954,	8,	7 }, /*BST_ATRIM_IADC_GAIN2*/
    441	{ 0x00003954,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
    442	{ 0x00003954,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
    443	{ 0x00003958,	0,	7 }, /*BST_ATRIM_IADC_OFFSET3*/
    444	{ 0x00003958,	8,	7 }, /*BST_ATRIM_IADC_GAIN3*/
    445	{ 0x00003958,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
    446	{ 0x00003958,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
    447	{ 0x0000395C,	0,	7 }, /*BST_ATRIM_IADC_OFFSET4*/
    448	{ 0x0000395C,	8,	7 }, /*BST_ATRIM_IADC_GAIN4*/
    449	{ 0x0000395C,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
    450	{ 0x0000395C,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
    451	{ 0x0000416C,	0,	8 }, /*VMON_GAIN_OTP_VAL*/
    452	{ 0x00004160,	0,	7 }, /*VMON_OFFSET_OTP_VAL*/
    453	{ 0x0000416C,	8,	8 }, /*IMON_GAIN_OTP_VAL*/
    454	{ 0x00004160,	16,	10 }, /*IMON_OFFSET_OTP_VAL*/
    455	{ 0x0000416C,	16,	12 }, /*VMON_CM_GAIN_OTP_VAL*/
    456	{ 0x0000416C,	28,	1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
    457	{ 0x00004170,	0,	6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
    458	{ 0x00004170,	6,	1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
    459	{ 0x00004170,	8,	6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
    460	{ 0x00004170,	14,	1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
    461	{ 0x00004170,	16,	9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
    462	{ 0x00004360,	0,	5 }, /*TEMP_GAIN_OTP_VAL*/
    463	{ 0x00004360,	6,	9 }, /*TEMP_OFFSET_OTP_VAL*/
    464	{ 0x00004448,	0,	8 }, /*VP_SARADC_OFFSET*/
    465	{ 0x00004448,	8,	8 }, /*VP_GAIN_INDEX*/
    466	{ 0x00004448,	16,	8 }, /*VBST_SARADC_OFFSET*/
    467	{ 0x00004448,	24,	8 }, /*VBST_GAIN_INDEX*/
    468	{ 0x0000444C,	0,	3 }, /*ANA_SELINVREF*/
    469	{ 0x00006E30,	0,	5 }, /*GAIN_ERR_COEFF_0*/
    470	{ 0x00006E30,	8,	5 }, /*GAIN_ERR_COEFF_1*/
    471	{ 0x00006E30,	16,	5 }, /*GAIN_ERR_COEFF_2*/
    472	{ 0x00006E30,	24,	5 }, /*GAIN_ERR_COEFF_3*/
    473	{ 0x00006E34,	0,	5 }, /*GAIN_ERR_COEFF_4*/
    474	{ 0x00006E34,	8,	5 }, /*GAIN_ERR_COEFF_5*/
    475	{ 0x00006E34,	16,	5 }, /*GAIN_ERR_COEFF_6*/
    476	{ 0x00006E34,	24,	5 }, /*GAIN_ERR_COEFF_7*/
    477	{ 0x00006E38,	0,	5 }, /*GAIN_ERR_COEFF_8*/
    478	{ 0x00006E38,	8,	5 }, /*GAIN_ERR_COEFF_9*/
    479	{ 0x00006E38,	16,	5 }, /*GAIN_ERR_COEFF_10*/
    480	{ 0x00006E38,	24,	5 }, /*GAIN_ERR_COEFF_11*/
    481	{ 0x00006E3C,	0,	5 }, /*GAIN_ERR_COEFF_12*/
    482	{ 0x00006E3C,	8,	5 }, /*GAIN_ERR_COEFF_13*/
    483	{ 0x00006E3C,	16,	5 }, /*GAIN_ERR_COEFF_14*/
    484	{ 0x00006E3C,	24,	5 }, /*GAIN_ERR_COEFF_15*/
    485	{ 0x00006E40,	0,	5 }, /*GAIN_ERR_COEFF_16*/
    486	{ 0x00006E40,	8,	5 }, /*GAIN_ERR_COEFF_17*/
    487	{ 0x00006E40,	16,	5 }, /*GAIN_ERR_COEFF_18*/
    488	{ 0x00006E40,	24,	5 }, /*GAIN_ERR_COEFF_19*/
    489	{ 0x00006E44,	0,	5 }, /*GAIN_ERR_COEFF_20*/
    490	{ 0x00006E48,	0,	10 }, /*VOFF_GAIN_0*/
    491	{ 0x00006E48,	10,	10 }, /*VOFF_GAIN_1*/
    492	{ 0x00006E48,	20,	10 }, /*VOFF_GAIN_2*/
    493	{ 0x00006E4C,	0,	10 }, /*VOFF_GAIN_3*/
    494	{ 0x00006E4C,	10,	10 }, /*VOFF_GAIN_4*/
    495	{ 0x00006E4C,	20,	10 }, /*VOFF_GAIN_5*/
    496	{ 0x00006E50,	0,	10 }, /*VOFF_GAIN_6*/
    497	{ 0x00006E50,	10,	10 }, /*VOFF_GAIN_7*/
    498	{ 0x00006E50,	20,	10 }, /*VOFF_GAIN_8*/
    499	{ 0x00006E54,	0,	10 }, /*VOFF_GAIN_9*/
    500	{ 0x00006E54,	10,	10 }, /*VOFF_GAIN_10*/
    501	{ 0x00006E54,	20,	10 }, /*VOFF_GAIN_11*/
    502	{ 0x00006E58,	0,	10 }, /*VOFF_GAIN_12*/
    503	{ 0x00006E58,	10,	10 }, /*VOFF_GAIN_13*/
    504	{ 0x00006E58,	20,	10 }, /*VOFF_GAIN_14*/
    505	{ 0x00006E5C,	0,	10 }, /*VOFF_GAIN_15*/
    506	{ 0x00006E5C,	10,	10 }, /*VOFF_GAIN_16*/
    507	{ 0x00006E5C,	20,	10 }, /*VOFF_GAIN_17*/
    508	{ 0x00006E60,	0,	10 }, /*VOFF_GAIN_18*/
    509	{ 0x00006E60,	10,	10 }, /*VOFF_GAIN_19*/
    510	{ 0x00006E60,	20,	10 }, /*VOFF_GAIN_20*/
    511	{ 0x00006E64,	0,	10 }, /*VOFF_INT1*/
    512	{ 0x00007418,	7,	5 }, /*DS_SPK_INT1_CAP_TRIM*/
    513	{ 0x0000741C,	0,	5 }, /*DS_SPK_INT2_CAP_TRIM*/
    514	{ 0x0000741C,	11,	4 }, /*DS_SPK_LPF_CAP_TRIM*/
    515	{ 0x0000741C,	19,	4 }, /*DS_SPK_QUAN_CAP_TRIM*/
    516	{ 0x00007434,	17,	1 }, /*FORCE_CAL*/
    517	{ 0x00007434,	18,	7 }, /*CAL_OVERRIDE*/
    518	{ 0x00007068,	0,	9 }, /*MODIX*/
    519	{ 0x0000410C,	7,	1 }, /*VIMON_DLY_NOT_COMB*/
    520	{ 0x0000400C,	0,	7 }, /*VIMON_DLY*/
    521	{ 0x00000000,	0,	1 }, /*extra bit*/
    522	{ 0x00017040,	0,	8 }, /*X_COORDINATE*/
    523	{ 0x00017040,	8,	8 }, /*Y_COORDINATE*/
    524	{ 0x00017040,	16,	8 }, /*WAFER_ID*/
    525	{ 0x00017040,	24,	8 }, /*DVS*/
    526	{ 0x00017044,	0,	24 }, /*LOT_NUMBER*/
    527};
    528
    529static const struct cs35l41_otp_packed_element_t otp_map_2[] = {
    530	/* addr         shift   size */
    531	{ 0x00002030,	0,	4 }, /*TRIM_OSC_FREQ_TRIM*/
    532	{ 0x00002030,	7,	1 }, /*TRIM_OSC_TRIM_DONE*/
    533	{ 0x0000208c,	24,	6 }, /*TST_DIGREG_VREF_TRIM*/
    534	{ 0x00002090,	14,	4 }, /*TST_REF_TRIM*/
    535	{ 0x00002090,	10,	4 }, /*TST_REF_TEMPCO_TRIM*/
    536	{ 0x0000300C,	11,	4 }, /*PLL_LDOA_TST_VREF_TRIM*/
    537	{ 0x0000394C,	23,	2 }, /*BST_ATEST_CM_VOFF*/
    538	{ 0x00003950,	0,	7 }, /*BST_ATRIM_IADC_OFFSET*/
    539	{ 0x00003950,	8,	7 }, /*BST_ATRIM_IADC_GAIN1*/
    540	{ 0x00003950,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
    541	{ 0x00003950,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
    542	{ 0x00003954,	0,	7 }, /*BST_ATRIM_IADC_OFFSET2*/
    543	{ 0x00003954,	8,	7 }, /*BST_ATRIM_IADC_GAIN2*/
    544	{ 0x00003954,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
    545	{ 0x00003954,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
    546	{ 0x00003958,	0,	7 }, /*BST_ATRIM_IADC_OFFSET3*/
    547	{ 0x00003958,	8,	7 }, /*BST_ATRIM_IADC_GAIN3*/
    548	{ 0x00003958,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
    549	{ 0x00003958,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
    550	{ 0x0000395C,	0,	7 }, /*BST_ATRIM_IADC_OFFSET4*/
    551	{ 0x0000395C,	8,	7 }, /*BST_ATRIM_IADC_GAIN4*/
    552	{ 0x0000395C,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
    553	{ 0x0000395C,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
    554	{ 0x0000416C,	0,	8 }, /*VMON_GAIN_OTP_VAL*/
    555	{ 0x00004160,	0,	7 }, /*VMON_OFFSET_OTP_VAL*/
    556	{ 0x0000416C,	8,	8 }, /*IMON_GAIN_OTP_VAL*/
    557	{ 0x00004160,	16,	10 }, /*IMON_OFFSET_OTP_VAL*/
    558	{ 0x0000416C,	16,	12 }, /*VMON_CM_GAIN_OTP_VAL*/
    559	{ 0x0000416C,	28,	1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
    560	{ 0x00004170,	0,	6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
    561	{ 0x00004170,	6,	1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
    562	{ 0x00004170,	8,	6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
    563	{ 0x00004170,	14,	1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
    564	{ 0x00004170,	16,	9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
    565	{ 0x00004360,	0,	5 }, /*TEMP_GAIN_OTP_VAL*/
    566	{ 0x00004360,	6,	9 }, /*TEMP_OFFSET_OTP_VAL*/
    567	{ 0x00004448,	0,	8 }, /*VP_SARADC_OFFSET*/
    568	{ 0x00004448,	8,	8 }, /*VP_GAIN_INDEX*/
    569	{ 0x00004448,	16,	8 }, /*VBST_SARADC_OFFSET*/
    570	{ 0x00004448,	24,	8 }, /*VBST_GAIN_INDEX*/
    571	{ 0x0000444C,	0,	3 }, /*ANA_SELINVREF*/
    572	{ 0x00006E30,	0,	5 }, /*GAIN_ERR_COEFF_0*/
    573	{ 0x00006E30,	8,	5 }, /*GAIN_ERR_COEFF_1*/
    574	{ 0x00006E30,	16,	5 }, /*GAIN_ERR_COEFF_2*/
    575	{ 0x00006E30,	24,	5 }, /*GAIN_ERR_COEFF_3*/
    576	{ 0x00006E34,	0,	5 }, /*GAIN_ERR_COEFF_4*/
    577	{ 0x00006E34,	8,	5 }, /*GAIN_ERR_COEFF_5*/
    578	{ 0x00006E34,	16,	5 }, /*GAIN_ERR_COEFF_6*/
    579	{ 0x00006E34,	24,	5 }, /*GAIN_ERR_COEFF_7*/
    580	{ 0x00006E38,	0,	5 }, /*GAIN_ERR_COEFF_8*/
    581	{ 0x00006E38,	8,	5 }, /*GAIN_ERR_COEFF_9*/
    582	{ 0x00006E38,	16,	5 }, /*GAIN_ERR_COEFF_10*/
    583	{ 0x00006E38,	24,	5 }, /*GAIN_ERR_COEFF_11*/
    584	{ 0x00006E3C,	0,	5 }, /*GAIN_ERR_COEFF_12*/
    585	{ 0x00006E3C,	8,	5 }, /*GAIN_ERR_COEFF_13*/
    586	{ 0x00006E3C,	16,	5 }, /*GAIN_ERR_COEFF_14*/
    587	{ 0x00006E3C,	24,	5 }, /*GAIN_ERR_COEFF_15*/
    588	{ 0x00006E40,	0,	5 }, /*GAIN_ERR_COEFF_16*/
    589	{ 0x00006E40,	8,	5 }, /*GAIN_ERR_COEFF_17*/
    590	{ 0x00006E40,	16,	5 }, /*GAIN_ERR_COEFF_18*/
    591	{ 0x00006E40,	24,	5 }, /*GAIN_ERR_COEFF_19*/
    592	{ 0x00006E44,	0,	5 }, /*GAIN_ERR_COEFF_20*/
    593	{ 0x00006E48,	0,	10 }, /*VOFF_GAIN_0*/
    594	{ 0x00006E48,	10,	10 }, /*VOFF_GAIN_1*/
    595	{ 0x00006E48,	20,	10 }, /*VOFF_GAIN_2*/
    596	{ 0x00006E4C,	0,	10 }, /*VOFF_GAIN_3*/
    597	{ 0x00006E4C,	10,	10 }, /*VOFF_GAIN_4*/
    598	{ 0x00006E4C,	20,	10 }, /*VOFF_GAIN_5*/
    599	{ 0x00006E50,	0,	10 }, /*VOFF_GAIN_6*/
    600	{ 0x00006E50,	10,	10 }, /*VOFF_GAIN_7*/
    601	{ 0x00006E50,	20,	10 }, /*VOFF_GAIN_8*/
    602	{ 0x00006E54,	0,	10 }, /*VOFF_GAIN_9*/
    603	{ 0x00006E54,	10,	10 }, /*VOFF_GAIN_10*/
    604	{ 0x00006E54,	20,	10 }, /*VOFF_GAIN_11*/
    605	{ 0x00006E58,	0,	10 }, /*VOFF_GAIN_12*/
    606	{ 0x00006E58,	10,	10 }, /*VOFF_GAIN_13*/
    607	{ 0x00006E58,	20,	10 }, /*VOFF_GAIN_14*/
    608	{ 0x00006E5C,	0,	10 }, /*VOFF_GAIN_15*/
    609	{ 0x00006E5C,	10,	10 }, /*VOFF_GAIN_16*/
    610	{ 0x00006E5C,	20,	10 }, /*VOFF_GAIN_17*/
    611	{ 0x00006E60,	0,	10 }, /*VOFF_GAIN_18*/
    612	{ 0x00006E60,	10,	10 }, /*VOFF_GAIN_19*/
    613	{ 0x00006E60,	20,	10 }, /*VOFF_GAIN_20*/
    614	{ 0x00006E64,	0,	10 }, /*VOFF_INT1*/
    615	{ 0x00007418,	7,	5 }, /*DS_SPK_INT1_CAP_TRIM*/
    616	{ 0x0000741C,	0,	5 }, /*DS_SPK_INT2_CAP_TRIM*/
    617	{ 0x0000741C,	11,	4 }, /*DS_SPK_LPF_CAP_TRIM*/
    618	{ 0x0000741C,	19,	4 }, /*DS_SPK_QUAN_CAP_TRIM*/
    619	{ 0x00007434,	17,	1 }, /*FORCE_CAL*/
    620	{ 0x00007434,	18,	7 }, /*CAL_OVERRIDE*/
    621	{ 0x00007068,	0,	9 }, /*MODIX*/
    622	{ 0x0000410C,	7,	1 }, /*VIMON_DLY_NOT_COMB*/
    623	{ 0x0000400C,	0,	7 }, /*VIMON_DLY*/
    624	{ 0x00004000,	11,	1 }, /*VMON_POL*/
    625	{ 0x00017040,	0,	8 }, /*X_COORDINATE*/
    626	{ 0x00017040,	8,	8 }, /*Y_COORDINATE*/
    627	{ 0x00017040,	16,	8 }, /*WAFER_ID*/
    628	{ 0x00017040,	24,	8 }, /*DVS*/
    629	{ 0x00017044,	0,	24 }, /*LOT_NUMBER*/
    630};
    631
    632static const struct reg_sequence cs35l41_reva0_errata_patch[] = {
    633	{ 0x00003854,			 0x05180240 },
    634	{ CS35L41_VIMON_SPKMON_RESYNC,	 0x00000000 },
    635	{ 0x00004310,			 0x00000000 },
    636	{ CS35L41_VPVBST_FS_SEL,	 0x00000000 },
    637	{ CS35L41_OTP_TRIM_30,		 0x9091A1C8 },
    638	{ 0x00003014,			 0x0200EE0E },
    639	{ CS35L41_BSTCVRT_DCM_CTRL,	 0x00000051 },
    640	{ 0x00000054,			 0x00000004 },
    641	{ CS35L41_IRQ1_DB3,		 0x00000000 },
    642	{ CS35L41_IRQ2_DB3,		 0x00000000 },
    643	{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
    644	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
    645	{ CS35L41_PWR_CTRL2,		 0x00000000 },
    646	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
    647	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
    648	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
    649};
    650
    651static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
    652	{ CS35L41_VIMON_SPKMON_RESYNC,	 0x00000000 },
    653	{ 0x00004310,			 0x00000000 },
    654	{ CS35L41_VPVBST_FS_SEL,	 0x00000000 },
    655	{ CS35L41_BSTCVRT_DCM_CTRL,	 0x00000051 },
    656	{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
    657	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
    658	{ CS35L41_PWR_CTRL2,		 0x00000000 },
    659	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
    660	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
    661	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
    662};
    663
    664static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
    665	{ CS35L41_VIMON_SPKMON_RESYNC,	 0x00000000 },
    666	{ 0x00004310,			 0x00000000 },
    667	{ CS35L41_VPVBST_FS_SEL,	 0x00000000 },
    668	{ CS35L41_BSTCVRT_DCM_CTRL,	 0x00000051 },
    669	{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
    670	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
    671	{ CS35L41_PWR_CTRL2,		 0x00000000 },
    672	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
    673	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
    674	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
    675};
    676
    677static const struct reg_sequence cs35l41_fs_errata_patch[] = {
    678	{ CS35L41_DSP1_RX1_RATE,	0x00000001 },
    679	{ CS35L41_DSP1_RX2_RATE,	0x00000001 },
    680	{ CS35L41_DSP1_RX3_RATE,	0x00000001 },
    681	{ CS35L41_DSP1_RX4_RATE,	0x00000001 },
    682	{ CS35L41_DSP1_RX5_RATE,	0x00000001 },
    683	{ CS35L41_DSP1_RX6_RATE,	0x00000001 },
    684	{ CS35L41_DSP1_RX7_RATE,	0x00000001 },
    685	{ CS35L41_DSP1_RX8_RATE,	0x00000001 },
    686	{ CS35L41_DSP1_TX1_RATE,	0x00000001 },
    687	{ CS35L41_DSP1_TX2_RATE,	0x00000001 },
    688	{ CS35L41_DSP1_TX3_RATE,	0x00000001 },
    689	{ CS35L41_DSP1_TX4_RATE,	0x00000001 },
    690	{ CS35L41_DSP1_TX5_RATE,	0x00000001 },
    691	{ CS35L41_DSP1_TX6_RATE,	0x00000001 },
    692	{ CS35L41_DSP1_TX7_RATE,	0x00000001 },
    693	{ CS35L41_DSP1_TX8_RATE,	0x00000001 },
    694};
    695
    696static const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = {
    697	{
    698		.id = 0x01,
    699		.map = otp_map_1,
    700		.num_elements = ARRAY_SIZE(otp_map_1),
    701		.bit_offset = 16,
    702		.word_offset = 2,
    703	},
    704	{
    705		.id = 0x02,
    706		.map = otp_map_2,
    707		.num_elements = ARRAY_SIZE(otp_map_2),
    708		.bit_offset = 16,
    709		.word_offset = 2,
    710	},
    711	{
    712		.id = 0x03,
    713		.map = otp_map_2,
    714		.num_elements = ARRAY_SIZE(otp_map_2),
    715		.bit_offset = 16,
    716		.word_offset = 2,
    717	},
    718	{
    719		.id = 0x06,
    720		.map = otp_map_2,
    721		.num_elements = ARRAY_SIZE(otp_map_2),
    722		.bit_offset = 16,
    723		.word_offset = 2,
    724	},
    725	{
    726		.id = 0x08,
    727		.map = otp_map_1,
    728		.num_elements = ARRAY_SIZE(otp_map_1),
    729		.bit_offset = 16,
    730		.word_offset = 2,
    731	},
    732};
    733
    734struct regmap_config cs35l41_regmap_i2c = {
    735	.reg_bits = 32,
    736	.val_bits = 32,
    737	.reg_stride = CS35L41_REGSTRIDE,
    738	.reg_format_endian = REGMAP_ENDIAN_BIG,
    739	.val_format_endian = REGMAP_ENDIAN_BIG,
    740	.max_register = CS35L41_LASTREG,
    741	.reg_defaults = cs35l41_reg,
    742	.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
    743	.volatile_reg = cs35l41_volatile_reg,
    744	.readable_reg = cs35l41_readable_reg,
    745	.precious_reg = cs35l41_precious_reg,
    746	.cache_type = REGCACHE_RBTREE,
    747};
    748EXPORT_SYMBOL_GPL(cs35l41_regmap_i2c);
    749
    750struct regmap_config cs35l41_regmap_spi = {
    751	.reg_bits = 32,
    752	.val_bits = 32,
    753	.pad_bits = 16,
    754	.reg_stride = CS35L41_REGSTRIDE,
    755	.reg_format_endian = REGMAP_ENDIAN_BIG,
    756	.val_format_endian = REGMAP_ENDIAN_BIG,
    757	.max_register = CS35L41_LASTREG,
    758	.reg_defaults = cs35l41_reg,
    759	.num_reg_defaults = ARRAY_SIZE(cs35l41_reg),
    760	.volatile_reg = cs35l41_volatile_reg,
    761	.readable_reg = cs35l41_readable_reg,
    762	.precious_reg = cs35l41_precious_reg,
    763	.cache_type = REGCACHE_RBTREE,
    764};
    765EXPORT_SYMBOL_GPL(cs35l41_regmap_spi);
    766
    767static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id)
    768{
    769	int i;
    770
    771	for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) {
    772		if (cs35l41_otp_map_map[i].id == otp_id)
    773			return &cs35l41_otp_map_map[i];
    774	}
    775
    776	return NULL;
    777}
    778
    779int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap)
    780{
    781	static const struct reg_sequence unlock[] = {
    782		{ CS35L41_TEST_KEY_CTL, 0x00000055 },
    783		{ CS35L41_TEST_KEY_CTL, 0x000000AA },
    784	};
    785	int ret;
    786
    787	ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock));
    788	if (ret)
    789		dev_err(dev, "Failed to unlock test key: %d\n", ret);
    790
    791	return ret;
    792}
    793EXPORT_SYMBOL_GPL(cs35l41_test_key_unlock);
    794
    795int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap)
    796{
    797	static const struct reg_sequence unlock[] = {
    798		{ CS35L41_TEST_KEY_CTL, 0x000000CC },
    799		{ CS35L41_TEST_KEY_CTL, 0x00000033 },
    800	};
    801	int ret;
    802
    803	ret = regmap_multi_reg_write(regmap, unlock, ARRAY_SIZE(unlock));
    804	if (ret)
    805		dev_err(dev, "Failed to lock test key: %d\n", ret);
    806
    807	return ret;
    808}
    809EXPORT_SYMBOL_GPL(cs35l41_test_key_lock);
    810
    811/* Must be called with the TEST_KEY unlocked */
    812int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap)
    813{
    814	const struct cs35l41_otp_map_element_t *otp_map_match;
    815	const struct cs35l41_otp_packed_element_t *otp_map;
    816	int bit_offset, word_offset, ret, i;
    817	unsigned int bit_sum = 8;
    818	u32 otp_val, otp_id_reg;
    819	u32 *otp_mem;
    820
    821	otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL);
    822	if (!otp_mem)
    823		return -ENOMEM;
    824
    825	ret = regmap_read(regmap, CS35L41_OTPID, &otp_id_reg);
    826	if (ret) {
    827		dev_err(dev, "Read OTP ID failed: %d\n", ret);
    828		goto err_otp_unpack;
    829	}
    830
    831	otp_map_match = cs35l41_find_otp_map(otp_id_reg);
    832
    833	if (!otp_map_match) {
    834		dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg);
    835		ret = -EINVAL;
    836		goto err_otp_unpack;
    837	}
    838
    839	ret = regmap_bulk_read(regmap, CS35L41_OTP_MEM0, otp_mem, CS35L41_OTP_SIZE_WORDS);
    840	if (ret) {
    841		dev_err(dev, "Read OTP Mem failed: %d\n", ret);
    842		goto err_otp_unpack;
    843	}
    844
    845	otp_map = otp_map_match->map;
    846
    847	bit_offset = otp_map_match->bit_offset;
    848	word_offset = otp_map_match->word_offset;
    849
    850	for (i = 0; i < otp_map_match->num_elements; i++) {
    851		dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d, otp_map[i].size = %u\n",
    852			bit_offset, word_offset, bit_sum % 32, otp_map[i].size);
    853		if (bit_offset + otp_map[i].size - 1 >= 32) {
    854			otp_val = (otp_mem[word_offset] &
    855					GENMASK(31, bit_offset)) >> bit_offset;
    856			otp_val |= (otp_mem[++word_offset] &
    857					GENMASK(bit_offset + otp_map[i].size - 33, 0)) <<
    858					(32 - bit_offset);
    859			bit_offset += otp_map[i].size - 32;
    860		} else if (bit_offset + otp_map[i].size - 1 >= 0) {
    861			otp_val = (otp_mem[word_offset] &
    862				   GENMASK(bit_offset + otp_map[i].size - 1, bit_offset)
    863				  ) >> bit_offset;
    864			bit_offset += otp_map[i].size;
    865		} else /* both bit_offset and otp_map[i].size are 0 */
    866			otp_val = 0;
    867
    868		bit_sum += otp_map[i].size;
    869
    870		if (bit_offset == 32) {
    871			bit_offset = 0;
    872			word_offset++;
    873		}
    874
    875		if (otp_map[i].reg != 0) {
    876			ret = regmap_update_bits(regmap, otp_map[i].reg,
    877						 GENMASK(otp_map[i].shift + otp_map[i].size - 1,
    878							 otp_map[i].shift),
    879						 otp_val << otp_map[i].shift);
    880			if (ret < 0) {
    881				dev_err(dev, "Write OTP val failed: %d\n", ret);
    882				goto err_otp_unpack;
    883			}
    884		}
    885	}
    886
    887	ret = 0;
    888
    889err_otp_unpack:
    890	kfree(otp_mem);
    891
    892	return ret;
    893}
    894EXPORT_SYMBOL_GPL(cs35l41_otp_unpack);
    895
    896/* Must be called with the TEST_KEY unlocked */
    897int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid)
    898{
    899	char *rev;
    900	int ret;
    901
    902	switch (reg_revid) {
    903	case CS35L41_REVID_A0:
    904		ret = regmap_register_patch(reg, cs35l41_reva0_errata_patch,
    905					    ARRAY_SIZE(cs35l41_reva0_errata_patch));
    906		rev = "A0";
    907		break;
    908	case CS35L41_REVID_B0:
    909		ret = regmap_register_patch(reg, cs35l41_revb0_errata_patch,
    910					    ARRAY_SIZE(cs35l41_revb0_errata_patch));
    911		rev = "B0";
    912		break;
    913	case CS35L41_REVID_B2:
    914		ret = regmap_register_patch(reg, cs35l41_revb2_errata_patch,
    915					    ARRAY_SIZE(cs35l41_revb2_errata_patch));
    916		rev = "B2";
    917		break;
    918	default:
    919		ret = -EINVAL;
    920		rev = "XX";
    921		break;
    922	}
    923
    924	if (ret)
    925		dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret);
    926
    927	ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0);
    928	if (ret < 0)
    929		dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret);
    930
    931	return ret;
    932}
    933EXPORT_SYMBOL_GPL(cs35l41_register_errata_patch);
    934
    935int cs35l41_set_channels(struct device *dev, struct regmap *reg,
    936			 unsigned int tx_num, unsigned int *tx_slot,
    937			 unsigned int rx_num, unsigned int *rx_slot)
    938{
    939	unsigned int val, mask;
    940	int i;
    941
    942	if (tx_num > 4 || rx_num > 2)
    943		return -EINVAL;
    944
    945	val = 0;
    946	mask = 0;
    947	for (i = 0; i < rx_num; i++) {
    948		dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]);
    949		val |= rx_slot[i] << (i * 8);
    950		mask |= 0x3F << (i * 8);
    951	}
    952	regmap_update_bits(reg, CS35L41_SP_FRAME_RX_SLOT, mask, val);
    953
    954	val = 0;
    955	mask = 0;
    956	for (i = 0; i < tx_num; i++) {
    957		dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]);
    958		val |= tx_slot[i] << (i * 8);
    959		mask |= 0x3F << (i * 8);
    960	}
    961	regmap_update_bits(reg, CS35L41_SP_FRAME_TX_SLOT, mask, val);
    962
    963	return 0;
    964}
    965EXPORT_SYMBOL_GPL(cs35l41_set_channels);
    966
    967static const unsigned char cs35l41_bst_k1_table[4][5] = {
    968	{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
    969	{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
    970	{ 0x40, 0x32, 0x32, 0x4F, 0x57 },
    971	{ 0x40, 0x32, 0x32, 0x4F, 0x57 }
    972};
    973
    974static const unsigned char cs35l41_bst_k2_table[4][5] = {
    975	{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
    976	{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
    977	{ 0x48, 0x49, 0x66, 0xA3, 0xEA },
    978	{ 0x48, 0x49, 0x66, 0xA3, 0xEA }
    979};
    980
    981static const unsigned char cs35l41_bst_slope_table[4] = {
    982	0x75, 0x6B, 0x3B, 0x28
    983};
    984
    985static int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind,
    986				int boost_cap, int boost_ipk)
    987{
    988	unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled;
    989	int ret;
    990
    991	switch (boost_ind) {
    992	case 1000:	/* 1.0 uH */
    993		bst_lbst_val = 0;
    994		break;
    995	case 1200:	/* 1.2 uH */
    996		bst_lbst_val = 1;
    997		break;
    998	case 1500:	/* 1.5 uH */
    999		bst_lbst_val = 2;
   1000		break;
   1001	case 2200:	/* 2.2 uH */
   1002		bst_lbst_val = 3;
   1003		break;
   1004	default:
   1005		dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind);
   1006		return -EINVAL;
   1007	}
   1008
   1009	switch (boost_cap) {
   1010	case 0 ... 19:
   1011		bst_cbst_range = 0;
   1012		break;
   1013	case 20 ... 50:
   1014		bst_cbst_range = 1;
   1015		break;
   1016	case 51 ... 100:
   1017		bst_cbst_range = 2;
   1018		break;
   1019	case 101 ... 200:
   1020		bst_cbst_range = 3;
   1021		break;
   1022	default:
   1023		if (boost_cap < 0) {
   1024			dev_err(dev, "Invalid boost capacitor value: %d nH\n", boost_cap);
   1025			return -EINVAL;
   1026		}
   1027		/* 201 uF and greater */
   1028		bst_cbst_range = 4;
   1029	}
   1030
   1031	if (boost_ipk < 1600 || boost_ipk > 4500) {
   1032		dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk);
   1033		return -EINVAL;
   1034	}
   1035
   1036	ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF,
   1037				 CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK,
   1038				 cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range]
   1039					<< CS35L41_BST_K1_SHIFT |
   1040				 cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range]
   1041					<< CS35L41_BST_K2_SHIFT);
   1042	if (ret) {
   1043		dev_err(dev, "Failed to write boost coefficients: %d\n", ret);
   1044		return ret;
   1045	}
   1046
   1047	ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST,
   1048				 CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK,
   1049				 cs35l41_bst_slope_table[bst_lbst_val]
   1050					<< CS35L41_BST_SLOPE_SHIFT |
   1051				 bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT);
   1052	if (ret) {
   1053		dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret);
   1054		return ret;
   1055	}
   1056
   1057	bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10;
   1058
   1059	ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK,
   1060				 bst_ipk_scaled << CS35L41_BST_IPK_SHIFT);
   1061	if (ret) {
   1062		dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret);
   1063		return ret;
   1064	}
   1065
   1066	regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
   1067			   CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT);
   1068
   1069	return 0;
   1070}
   1071
   1072static const struct reg_sequence cs35l41_safe_to_reset[] = {
   1073	{ 0x00000040,			0x00000055 },
   1074	{ 0x00000040,			0x000000AA },
   1075	{ 0x0000393C,			0x000000C0, 6000},
   1076	{ 0x0000393C,			0x00000000 },
   1077	{ 0x00007414,			0x00C82222 },
   1078	{ 0x0000742C,			0x00000000 },
   1079	{ 0x00000040,			0x000000CC },
   1080	{ 0x00000040,			0x00000033 },
   1081};
   1082
   1083static const struct reg_sequence cs35l41_active_to_safe[] = {
   1084	{ 0x00000040,			0x00000055 },
   1085	{ 0x00000040,			0x000000AA },
   1086	{ 0x00007438,			0x00585941 },
   1087	{ CS35L41_PWR_CTRL1,		0x00000000 },
   1088	{ 0x0000742C,			0x00000009, 3000 },
   1089	{ 0x00007438,			0x00580941 },
   1090	{ 0x00000040,			0x000000CC },
   1091	{ 0x00000040,			0x00000033 },
   1092};
   1093
   1094static const struct reg_sequence cs35l41_safe_to_active[] = {
   1095	{ 0x00000040,			0x00000055 },
   1096	{ 0x00000040,			0x000000AA },
   1097	{ 0x0000742C,			0x0000000F },
   1098	{ 0x0000742C,			0x00000079 },
   1099	{ 0x00007438,			0x00585941 },
   1100	{ CS35L41_PWR_CTRL1,		0x00000001, 3000 }, // GLOBAL_EN = 1
   1101	{ 0x0000742C,			0x000000F9 },
   1102	{ 0x00007438,			0x00580941 },
   1103	{ 0x00000040,			0x000000CC },
   1104	{ 0x00000040,			0x00000033 },
   1105};
   1106
   1107static const struct reg_sequence cs35l41_reset_to_safe[] = {
   1108	{ 0x00000040,			0x00000055 },
   1109	{ 0x00000040,			0x000000AA },
   1110	{ 0x00007438,			0x00585941 },
   1111	{ 0x00007414,			0x08C82222 },
   1112	{ 0x0000742C,			0x00000009 },
   1113	{ 0x00000040,			0x000000CC },
   1114	{ 0x00000040,			0x00000033 },
   1115};
   1116
   1117int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
   1118		       struct cs35l41_hw_cfg *hw_cfg)
   1119{
   1120	int ret;
   1121
   1122	switch (hw_cfg->bst_type) {
   1123	case CS35L41_INT_BOOST:
   1124		ret = cs35l41_boost_config(dev, regmap, hw_cfg->bst_ind,
   1125					   hw_cfg->bst_cap, hw_cfg->bst_ipk);
   1126		if (ret)
   1127			dev_err(dev, "Error in Boost DT config: %d\n", ret);
   1128		break;
   1129	case CS35L41_EXT_BOOST:
   1130	case CS35L41_EXT_BOOST_NO_VSPK_SWITCH:
   1131		/* Only CLSA0100 doesn't use GPIO as VSPK switch, but even on that laptop we can
   1132		 * toggle GPIO1 as is not connected to anything.
   1133		 * There will be no other device without VSPK switch.
   1134		 */
   1135		regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001);
   1136		regmap_multi_reg_write(regmap, cs35l41_reset_to_safe,
   1137				       ARRAY_SIZE(cs35l41_reset_to_safe));
   1138		ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
   1139					 CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT);
   1140		break;
   1141	default:
   1142		dev_err(dev, "Boost type %d not supported\n", hw_cfg->bst_type);
   1143		ret = -EINVAL;
   1144		break;
   1145	}
   1146
   1147	return ret;
   1148}
   1149EXPORT_SYMBOL_GPL(cs35l41_init_boost);
   1150
   1151bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type)
   1152{
   1153	switch (b_type) {
   1154	/* There is only one laptop that doesn't have VSPK switch. */
   1155	case CS35L41_EXT_BOOST_NO_VSPK_SWITCH:
   1156		return false;
   1157	case CS35L41_EXT_BOOST:
   1158		regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001);
   1159		regmap_multi_reg_write(regmap, cs35l41_safe_to_reset,
   1160				       ARRAY_SIZE(cs35l41_safe_to_reset));
   1161		return true;
   1162	default:
   1163		return true;
   1164	}
   1165}
   1166EXPORT_SYMBOL_GPL(cs35l41_safe_reset);
   1167
   1168int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable)
   1169{
   1170	int ret;
   1171
   1172	switch (b_type) {
   1173	case CS35L41_INT_BOOST:
   1174		ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK,
   1175					 enable << CS35L41_GLOBAL_EN_SHIFT);
   1176		usleep_range(3000, 3100);
   1177		break;
   1178	case CS35L41_EXT_BOOST:
   1179	case CS35L41_EXT_BOOST_NO_VSPK_SWITCH:
   1180		if (enable)
   1181			ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active,
   1182						     ARRAY_SIZE(cs35l41_safe_to_active));
   1183		else
   1184			ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe,
   1185						     ARRAY_SIZE(cs35l41_active_to_safe));
   1186		break;
   1187	default:
   1188		ret = -EINVAL;
   1189		break;
   1190	}
   1191
   1192	return ret;
   1193}
   1194EXPORT_SYMBOL_GPL(cs35l41_global_enable);
   1195
   1196int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg)
   1197{
   1198	struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
   1199	struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
   1200	int irq_pol = IRQF_TRIGGER_NONE;
   1201
   1202	regmap_update_bits(regmap, CS35L41_GPIO1_CTRL1,
   1203			   CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK,
   1204			   gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT |
   1205			   !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT);
   1206
   1207	regmap_update_bits(regmap, CS35L41_GPIO2_CTRL1,
   1208			   CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK,
   1209			   gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT |
   1210			   !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT);
   1211
   1212	if (gpio1->valid)
   1213		regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK,
   1214				   gpio1->func << CS35L41_GPIO1_CTRL_SHIFT);
   1215
   1216	if (gpio2->valid) {
   1217		regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO2_CTRL_MASK,
   1218				   gpio2->func << CS35L41_GPIO2_CTRL_SHIFT);
   1219
   1220		switch (gpio2->func) {
   1221		case CS35L41_GPIO2_INT_PUSH_PULL_LOW:
   1222		case CS35L41_GPIO2_INT_OPEN_DRAIN:
   1223			irq_pol = IRQF_TRIGGER_LOW;
   1224			break;
   1225		case CS35L41_GPIO2_INT_PUSH_PULL_HIGH:
   1226			irq_pol = IRQF_TRIGGER_HIGH;
   1227			break;
   1228		default:
   1229			break;
   1230		}
   1231	}
   1232
   1233	return irq_pol;
   1234}
   1235EXPORT_SYMBOL_GPL(cs35l41_gpio_config);
   1236
   1237static const struct cs_dsp_region cs35l41_dsp1_regions[] = {
   1238	{ .type = WMFW_HALO_PM_PACKED,	.base = CS35L41_DSP1_PMEM_0 },
   1239	{ .type = WMFW_HALO_XM_PACKED,	.base = CS35L41_DSP1_XMEM_PACK_0 },
   1240	{ .type = WMFW_HALO_YM_PACKED,	.base = CS35L41_DSP1_YMEM_PACK_0 },
   1241	{. type = WMFW_ADSP2_XM,	.base = CS35L41_DSP1_XMEM_UNPACK24_0},
   1242	{. type = WMFW_ADSP2_YM,	.base = CS35L41_DSP1_YMEM_UNPACK24_0},
   1243};
   1244
   1245void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp)
   1246{
   1247	dsp->num = 1;
   1248	dsp->type = WMFW_HALO;
   1249	dsp->rev = 0;
   1250	dsp->dev = dev;
   1251	dsp->regmap = reg;
   1252	dsp->base = CS35L41_DSP1_CTRL_BASE;
   1253	dsp->base_sysinfo = CS35L41_DSP1_SYS_ID;
   1254	dsp->mem = cs35l41_dsp1_regions;
   1255	dsp->num_mems = ARRAY_SIZE(cs35l41_dsp1_regions);
   1256	dsp->lock_regions = 0xFFFFFFFF;
   1257}
   1258EXPORT_SYMBOL_GPL(cs35l41_configure_cs_dsp);
   1259
   1260static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd,
   1261					enum cs35l41_cspl_mbox_status sts)
   1262{
   1263	switch (cmd) {
   1264	case CSPL_MBOX_CMD_NONE:
   1265	case CSPL_MBOX_CMD_UNKNOWN_CMD:
   1266		return true;
   1267	case CSPL_MBOX_CMD_PAUSE:
   1268	case CSPL_MBOX_CMD_OUT_OF_HIBERNATE:
   1269		return (sts == CSPL_MBOX_STS_PAUSED);
   1270	case CSPL_MBOX_CMD_RESUME:
   1271		return (sts == CSPL_MBOX_STS_RUNNING);
   1272	case CSPL_MBOX_CMD_REINIT:
   1273		return (sts == CSPL_MBOX_STS_RUNNING);
   1274	case CSPL_MBOX_CMD_STOP_PRE_REINIT:
   1275		return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT);
   1276	default:
   1277		return false;
   1278	}
   1279}
   1280
   1281int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,
   1282			      enum cs35l41_cspl_mbox_cmd cmd)
   1283{
   1284	unsigned int sts = 0, i;
   1285	int ret;
   1286
   1287	// Set mailbox cmd
   1288	ret = regmap_write(regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd);
   1289	if (ret < 0) {
   1290		if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
   1291			dev_err(dev, "Failed to write MBOX: %d\n", ret);
   1292		return ret;
   1293	}
   1294
   1295	// Read mailbox status and verify it is appropriate for the given cmd
   1296	for (i = 0; i < 5; i++) {
   1297		usleep_range(1000, 1100);
   1298
   1299		ret = regmap_read(regmap, CS35L41_DSP_MBOX_2, &sts);
   1300		if (ret < 0) {
   1301			dev_err(dev, "Failed to read MBOX STS: %d\n", ret);
   1302			continue;
   1303		}
   1304
   1305		if (!cs35l41_check_cspl_mbox_sts(cmd, sts))
   1306			dev_dbg(dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts);
   1307		else
   1308			return 0;
   1309	}
   1310
   1311	dev_err(dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts);
   1312
   1313	return -ENOMSG;
   1314}
   1315EXPORT_SYMBOL_GPL(cs35l41_set_cspl_mbox_cmd);
   1316
   1317int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap)
   1318{
   1319	int ret;
   1320
   1321	ret = regmap_multi_reg_write(regmap, cs35l41_fs_errata_patch,
   1322				     ARRAY_SIZE(cs35l41_fs_errata_patch));
   1323	if (ret < 0)
   1324		dev_err(dev, "Failed to write fs errata: %d\n", ret);
   1325
   1326	return ret;
   1327}
   1328EXPORT_SYMBOL_GPL(cs35l41_write_fs_errata);
   1329
   1330MODULE_DESCRIPTION("CS35L41 library");
   1331MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
   1332MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>");
   1333MODULE_LICENSE("GPL");