cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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wm8960.h (2719B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * wm8960.h  --  WM8960 Soc Audio driver
      4 */
      5
      6#ifndef _WM8960_H
      7#define _WM8960_H
      8
      9/* WM8960 register space */
     10
     11
     12#define WM8960_CACHEREGNUM 	56
     13
     14#define WM8960_LINVOL		0x0
     15#define WM8960_RINVOL		0x1
     16#define WM8960_LOUT1		0x2
     17#define WM8960_ROUT1		0x3
     18#define WM8960_CLOCK1		0x4
     19#define WM8960_DACCTL1		0x5
     20#define WM8960_DACCTL2		0x6
     21#define WM8960_IFACE1		0x7
     22#define WM8960_CLOCK2		0x8
     23#define WM8960_IFACE2		0x9
     24#define WM8960_LDAC		0xa
     25#define WM8960_RDAC		0xb
     26
     27#define WM8960_RESET		0xf
     28#define WM8960_3D		0x10
     29#define WM8960_ALC1		0x11
     30#define WM8960_ALC2		0x12
     31#define WM8960_ALC3		0x13
     32#define WM8960_NOISEG		0x14
     33#define WM8960_LADC		0x15
     34#define WM8960_RADC		0x16
     35#define WM8960_ADDCTL1		0x17
     36#define WM8960_ADDCTL2		0x18
     37#define WM8960_POWER1		0x19
     38#define WM8960_POWER2		0x1a
     39#define WM8960_ADDCTL3		0x1b
     40#define WM8960_APOP1		0x1c
     41#define WM8960_APOP2		0x1d
     42
     43#define WM8960_LINPATH		0x20
     44#define WM8960_RINPATH		0x21
     45#define WM8960_LOUTMIX		0x22
     46
     47#define WM8960_ROUTMIX		0x25
     48#define WM8960_MONOMIX1		0x26
     49#define WM8960_MONOMIX2		0x27
     50#define WM8960_LOUT2		0x28
     51#define WM8960_ROUT2		0x29
     52#define WM8960_MONO		0x2a
     53#define WM8960_INBMIX1		0x2b
     54#define WM8960_INBMIX2		0x2c
     55#define WM8960_BYPASS1		0x2d
     56#define WM8960_BYPASS2		0x2e
     57#define WM8960_POWER3		0x2f
     58#define WM8960_ADDCTL4		0x30
     59#define WM8960_CLASSD1		0x31
     60
     61#define WM8960_CLASSD3		0x33
     62#define WM8960_PLL1		0x34
     63#define WM8960_PLL2		0x35
     64#define WM8960_PLL3		0x36
     65#define WM8960_PLL4		0x37
     66
     67
     68/*
     69 * WM8960 Clock dividers
     70 */
     71#define WM8960_SYSCLKDIV 		0
     72#define WM8960_DACDIV			1
     73#define WM8960_OPCLKDIV			2
     74#define WM8960_DCLKDIV			3
     75#define WM8960_TOCLKSEL			4
     76
     77#define WM8960_SYSCLK_DIV_1		(0 << 1)
     78#define WM8960_SYSCLK_DIV_2		(2 << 1)
     79
     80#define WM8960_SYSCLK_MCLK		(0 << 0)
     81#define WM8960_SYSCLK_PLL		(1 << 0)
     82#define WM8960_SYSCLK_AUTO		(2 << 0)
     83
     84#define WM8960_DAC_DIV_1		(0 << 3)
     85#define WM8960_DAC_DIV_1_5		(1 << 3)
     86#define WM8960_DAC_DIV_2		(2 << 3)
     87#define WM8960_DAC_DIV_3		(3 << 3)
     88#define WM8960_DAC_DIV_4		(4 << 3)
     89#define WM8960_DAC_DIV_5_5		(5 << 3)
     90#define WM8960_DAC_DIV_6		(6 << 3)
     91
     92#define WM8960_DCLK_DIV_1_5		(0 << 6)
     93#define WM8960_DCLK_DIV_2		(1 << 6)
     94#define WM8960_DCLK_DIV_3		(2 << 6)
     95#define WM8960_DCLK_DIV_4		(3 << 6)
     96#define WM8960_DCLK_DIV_6		(4 << 6)
     97#define WM8960_DCLK_DIV_8		(5 << 6)
     98#define WM8960_DCLK_DIV_12		(6 << 6)
     99#define WM8960_DCLK_DIV_16		(7 << 6)
    100
    101#define WM8960_TOCLK_F19		(0 << 1)
    102#define WM8960_TOCLK_F21		(1 << 1)
    103
    104#define WM8960_OPCLK_DIV_1		(0 << 0)
    105#define WM8960_OPCLK_DIV_2		(1 << 0)
    106#define WM8960_OPCLK_DIV_3		(2 << 0)
    107#define WM8960_OPCLK_DIV_4		(3 << 0)
    108#define WM8960_OPCLK_DIV_5_5		(4 << 0)
    109#define WM8960_OPCLK_DIV_6		(5 << 0)
    110
    111#endif