wm8961.h (46304B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * wm8961.h -- WM8961 Soc Audio driver 4 */ 5 6#ifndef _WM8961_H 7#define _WM8961_H 8 9#include <sound/soc.h> 10 11#define WM8961_BCLK 1 12#define WM8961_LRCLK 2 13 14#define WM8961_BCLK_DIV_1 0 15#define WM8961_BCLK_DIV_1_5 1 16#define WM8961_BCLK_DIV_2 2 17#define WM8961_BCLK_DIV_3 3 18#define WM8961_BCLK_DIV_4 4 19#define WM8961_BCLK_DIV_5_5 5 20#define WM8961_BCLK_DIV_6 6 21#define WM8961_BCLK_DIV_8 7 22#define WM8961_BCLK_DIV_11 8 23#define WM8961_BCLK_DIV_12 9 24#define WM8961_BCLK_DIV_16 10 25#define WM8961_BCLK_DIV_24 11 26#define WM8961_BCLK_DIV_32 13 27 28 29/* 30 * Register values. 31 */ 32#define WM8961_LEFT_INPUT_VOLUME 0x00 33#define WM8961_RIGHT_INPUT_VOLUME 0x01 34#define WM8961_LOUT1_VOLUME 0x02 35#define WM8961_ROUT1_VOLUME 0x03 36#define WM8961_CLOCKING1 0x04 37#define WM8961_ADC_DAC_CONTROL_1 0x05 38#define WM8961_ADC_DAC_CONTROL_2 0x06 39#define WM8961_AUDIO_INTERFACE_0 0x07 40#define WM8961_CLOCKING2 0x08 41#define WM8961_AUDIO_INTERFACE_1 0x09 42#define WM8961_LEFT_DAC_VOLUME 0x0A 43#define WM8961_RIGHT_DAC_VOLUME 0x0B 44#define WM8961_AUDIO_INTERFACE_2 0x0E 45#define WM8961_SOFTWARE_RESET 0x0F 46#define WM8961_ALC1 0x11 47#define WM8961_ALC2 0x12 48#define WM8961_ALC3 0x13 49#define WM8961_NOISE_GATE 0x14 50#define WM8961_LEFT_ADC_VOLUME 0x15 51#define WM8961_RIGHT_ADC_VOLUME 0x16 52#define WM8961_ADDITIONAL_CONTROL_1 0x17 53#define WM8961_ADDITIONAL_CONTROL_2 0x18 54#define WM8961_PWR_MGMT_1 0x19 55#define WM8961_PWR_MGMT_2 0x1A 56#define WM8961_ADDITIONAL_CONTROL_3 0x1B 57#define WM8961_ANTI_POP 0x1C 58#define WM8961_CLOCKING_3 0x1E 59#define WM8961_ADCL_SIGNAL_PATH 0x20 60#define WM8961_ADCR_SIGNAL_PATH 0x21 61#define WM8961_LOUT2_VOLUME 0x28 62#define WM8961_ROUT2_VOLUME 0x29 63#define WM8961_PWR_MGMT_3 0x2F 64#define WM8961_ADDITIONAL_CONTROL_4 0x30 65#define WM8961_CLASS_D_CONTROL_1 0x31 66#define WM8961_CLASS_D_CONTROL_2 0x33 67#define WM8961_CLOCKING_4 0x38 68#define WM8961_DSP_SIDETONE_0 0x39 69#define WM8961_DSP_SIDETONE_1 0x3A 70#define WM8961_DC_SERVO_0 0x3C 71#define WM8961_DC_SERVO_1 0x3D 72#define WM8961_DC_SERVO_3 0x3F 73#define WM8961_DC_SERVO_5 0x41 74#define WM8961_ANALOGUE_PGA_BIAS 0x44 75#define WM8961_ANALOGUE_HP_0 0x45 76#define WM8961_ANALOGUE_HP_2 0x47 77#define WM8961_CHARGE_PUMP_1 0x48 78#define WM8961_CHARGE_PUMP_B 0x52 79#define WM8961_WRITE_SEQUENCER_1 0x57 80#define WM8961_WRITE_SEQUENCER_2 0x58 81#define WM8961_WRITE_SEQUENCER_3 0x59 82#define WM8961_WRITE_SEQUENCER_4 0x5A 83#define WM8961_WRITE_SEQUENCER_5 0x5B 84#define WM8961_WRITE_SEQUENCER_6 0x5C 85#define WM8961_WRITE_SEQUENCER_7 0x5D 86#define WM8961_GENERAL_TEST_1 0xFC 87 88 89/* 90 * Field Definitions. 91 */ 92 93/* 94 * R0 (0x00) - Left Input volume 95 */ 96#define WM8961_IPVU 0x0100 /* IPVU */ 97#define WM8961_IPVU_MASK 0x0100 /* IPVU */ 98#define WM8961_IPVU_SHIFT 8 /* IPVU */ 99#define WM8961_IPVU_WIDTH 1 /* IPVU */ 100#define WM8961_LINMUTE 0x0080 /* LINMUTE */ 101#define WM8961_LINMUTE_MASK 0x0080 /* LINMUTE */ 102#define WM8961_LINMUTE_SHIFT 7 /* LINMUTE */ 103#define WM8961_LINMUTE_WIDTH 1 /* LINMUTE */ 104#define WM8961_LIZC 0x0040 /* LIZC */ 105#define WM8961_LIZC_MASK 0x0040 /* LIZC */ 106#define WM8961_LIZC_SHIFT 6 /* LIZC */ 107#define WM8961_LIZC_WIDTH 1 /* LIZC */ 108#define WM8961_LINVOL_MASK 0x003F /* LINVOL - [5:0] */ 109#define WM8961_LINVOL_SHIFT 0 /* LINVOL - [5:0] */ 110#define WM8961_LINVOL_WIDTH 6 /* LINVOL - [5:0] */ 111 112/* 113 * R1 (0x01) - Right Input volume 114 */ 115#define WM8961_DEVICE_ID_MASK 0xF000 /* DEVICE_ID - [15:12] */ 116#define WM8961_DEVICE_ID_SHIFT 12 /* DEVICE_ID - [15:12] */ 117#define WM8961_DEVICE_ID_WIDTH 4 /* DEVICE_ID - [15:12] */ 118#define WM8961_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */ 119#define WM8961_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */ 120#define WM8961_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */ 121#define WM8961_IPVU 0x0100 /* IPVU */ 122#define WM8961_IPVU_MASK 0x0100 /* IPVU */ 123#define WM8961_IPVU_SHIFT 8 /* IPVU */ 124#define WM8961_IPVU_WIDTH 1 /* IPVU */ 125#define WM8961_RINMUTE 0x0080 /* RINMUTE */ 126#define WM8961_RINMUTE_MASK 0x0080 /* RINMUTE */ 127#define WM8961_RINMUTE_SHIFT 7 /* RINMUTE */ 128#define WM8961_RINMUTE_WIDTH 1 /* RINMUTE */ 129#define WM8961_RIZC 0x0040 /* RIZC */ 130#define WM8961_RIZC_MASK 0x0040 /* RIZC */ 131#define WM8961_RIZC_SHIFT 6 /* RIZC */ 132#define WM8961_RIZC_WIDTH 1 /* RIZC */ 133#define WM8961_RINVOL_MASK 0x003F /* RINVOL - [5:0] */ 134#define WM8961_RINVOL_SHIFT 0 /* RINVOL - [5:0] */ 135#define WM8961_RINVOL_WIDTH 6 /* RINVOL - [5:0] */ 136 137/* 138 * R2 (0x02) - LOUT1 volume 139 */ 140#define WM8961_OUT1VU 0x0100 /* OUT1VU */ 141#define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ 142#define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ 143#define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ 144#define WM8961_LO1ZC 0x0080 /* LO1ZC */ 145#define WM8961_LO1ZC_MASK 0x0080 /* LO1ZC */ 146#define WM8961_LO1ZC_SHIFT 7 /* LO1ZC */ 147#define WM8961_LO1ZC_WIDTH 1 /* LO1ZC */ 148#define WM8961_LOUT1VOL_MASK 0x007F /* LOUT1VOL - [6:0] */ 149#define WM8961_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [6:0] */ 150#define WM8961_LOUT1VOL_WIDTH 7 /* LOUT1VOL - [6:0] */ 151 152/* 153 * R3 (0x03) - ROUT1 volume 154 */ 155#define WM8961_OUT1VU 0x0100 /* OUT1VU */ 156#define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ 157#define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ 158#define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ 159#define WM8961_RO1ZC 0x0080 /* RO1ZC */ 160#define WM8961_RO1ZC_MASK 0x0080 /* RO1ZC */ 161#define WM8961_RO1ZC_SHIFT 7 /* RO1ZC */ 162#define WM8961_RO1ZC_WIDTH 1 /* RO1ZC */ 163#define WM8961_ROUT1VOL_MASK 0x007F /* ROUT1VOL - [6:0] */ 164#define WM8961_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [6:0] */ 165#define WM8961_ROUT1VOL_WIDTH 7 /* ROUT1VOL - [6:0] */ 166 167/* 168 * R4 (0x04) - Clocking1 169 */ 170#define WM8961_ADCDIV_MASK 0x01C0 /* ADCDIV - [8:6] */ 171#define WM8961_ADCDIV_SHIFT 6 /* ADCDIV - [8:6] */ 172#define WM8961_ADCDIV_WIDTH 3 /* ADCDIV - [8:6] */ 173#define WM8961_DACDIV_MASK 0x0038 /* DACDIV - [5:3] */ 174#define WM8961_DACDIV_SHIFT 3 /* DACDIV - [5:3] */ 175#define WM8961_DACDIV_WIDTH 3 /* DACDIV - [5:3] */ 176#define WM8961_MCLKDIV 0x0004 /* MCLKDIV */ 177#define WM8961_MCLKDIV_MASK 0x0004 /* MCLKDIV */ 178#define WM8961_MCLKDIV_SHIFT 2 /* MCLKDIV */ 179#define WM8961_MCLKDIV_WIDTH 1 /* MCLKDIV */ 180 181/* 182 * R5 (0x05) - ADC & DAC Control 1 183 */ 184#define WM8961_ADCPOL_MASK 0x0060 /* ADCPOL - [6:5] */ 185#define WM8961_ADCPOL_SHIFT 5 /* ADCPOL - [6:5] */ 186#define WM8961_ADCPOL_WIDTH 2 /* ADCPOL - [6:5] */ 187#define WM8961_DACMU 0x0008 /* DACMU */ 188#define WM8961_DACMU_MASK 0x0008 /* DACMU */ 189#define WM8961_DACMU_SHIFT 3 /* DACMU */ 190#define WM8961_DACMU_WIDTH 1 /* DACMU */ 191#define WM8961_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 192#define WM8961_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 193#define WM8961_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 194#define WM8961_ADCHPD 0x0001 /* ADCHPD */ 195#define WM8961_ADCHPD_MASK 0x0001 /* ADCHPD */ 196#define WM8961_ADCHPD_SHIFT 0 /* ADCHPD */ 197#define WM8961_ADCHPD_WIDTH 1 /* ADCHPD */ 198 199/* 200 * R6 (0x06) - ADC & DAC Control 2 201 */ 202#define WM8961_ADC_HPF_CUT_MASK 0x0180 /* ADC_HPF_CUT - [8:7] */ 203#define WM8961_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [8:7] */ 204#define WM8961_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [8:7] */ 205#define WM8961_DACPOL_MASK 0x0060 /* DACPOL - [6:5] */ 206#define WM8961_DACPOL_SHIFT 5 /* DACPOL - [6:5] */ 207#define WM8961_DACPOL_WIDTH 2 /* DACPOL - [6:5] */ 208#define WM8961_DACSMM 0x0008 /* DACSMM */ 209#define WM8961_DACSMM_MASK 0x0008 /* DACSMM */ 210#define WM8961_DACSMM_SHIFT 3 /* DACSMM */ 211#define WM8961_DACSMM_WIDTH 1 /* DACSMM */ 212#define WM8961_DACMR 0x0004 /* DACMR */ 213#define WM8961_DACMR_MASK 0x0004 /* DACMR */ 214#define WM8961_DACMR_SHIFT 2 /* DACMR */ 215#define WM8961_DACMR_WIDTH 1 /* DACMR */ 216#define WM8961_DACSLOPE 0x0002 /* DACSLOPE */ 217#define WM8961_DACSLOPE_MASK 0x0002 /* DACSLOPE */ 218#define WM8961_DACSLOPE_SHIFT 1 /* DACSLOPE */ 219#define WM8961_DACSLOPE_WIDTH 1 /* DACSLOPE */ 220#define WM8961_DAC_OSR128 0x0001 /* DAC_OSR128 */ 221#define WM8961_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 222#define WM8961_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 223#define WM8961_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 224 225/* 226 * R7 (0x07) - Audio Interface 0 227 */ 228#define WM8961_ALRSWAP 0x0100 /* ALRSWAP */ 229#define WM8961_ALRSWAP_MASK 0x0100 /* ALRSWAP */ 230#define WM8961_ALRSWAP_SHIFT 8 /* ALRSWAP */ 231#define WM8961_ALRSWAP_WIDTH 1 /* ALRSWAP */ 232#define WM8961_BCLKINV 0x0080 /* BCLKINV */ 233#define WM8961_BCLKINV_MASK 0x0080 /* BCLKINV */ 234#define WM8961_BCLKINV_SHIFT 7 /* BCLKINV */ 235#define WM8961_BCLKINV_WIDTH 1 /* BCLKINV */ 236#define WM8961_MS 0x0040 /* MS */ 237#define WM8961_MS_MASK 0x0040 /* MS */ 238#define WM8961_MS_SHIFT 6 /* MS */ 239#define WM8961_MS_WIDTH 1 /* MS */ 240#define WM8961_DLRSWAP 0x0020 /* DLRSWAP */ 241#define WM8961_DLRSWAP_MASK 0x0020 /* DLRSWAP */ 242#define WM8961_DLRSWAP_SHIFT 5 /* DLRSWAP */ 243#define WM8961_DLRSWAP_WIDTH 1 /* DLRSWAP */ 244#define WM8961_LRP 0x0010 /* LRP */ 245#define WM8961_LRP_MASK 0x0010 /* LRP */ 246#define WM8961_LRP_SHIFT 4 /* LRP */ 247#define WM8961_LRP_WIDTH 1 /* LRP */ 248#define WM8961_WL_MASK 0x000C /* WL - [3:2] */ 249#define WM8961_WL_SHIFT 2 /* WL - [3:2] */ 250#define WM8961_WL_WIDTH 2 /* WL - [3:2] */ 251#define WM8961_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ 252#define WM8961_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ 253#define WM8961_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ 254 255/* 256 * R8 (0x08) - Clocking2 257 */ 258#define WM8961_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ 259#define WM8961_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */ 260#define WM8961_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */ 261#define WM8961_CLK_SYS_ENA 0x0020 /* CLK_SYS_ENA */ 262#define WM8961_CLK_SYS_ENA_MASK 0x0020 /* CLK_SYS_ENA */ 263#define WM8961_CLK_SYS_ENA_SHIFT 5 /* CLK_SYS_ENA */ 264#define WM8961_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 265#define WM8961_CLK_DSP_ENA 0x0010 /* CLK_DSP_ENA */ 266#define WM8961_CLK_DSP_ENA_MASK 0x0010 /* CLK_DSP_ENA */ 267#define WM8961_CLK_DSP_ENA_SHIFT 4 /* CLK_DSP_ENA */ 268#define WM8961_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 269#define WM8961_BCLKDIV_MASK 0x000F /* BCLKDIV - [3:0] */ 270#define WM8961_BCLKDIV_SHIFT 0 /* BCLKDIV - [3:0] */ 271#define WM8961_BCLKDIV_WIDTH 4 /* BCLKDIV - [3:0] */ 272 273/* 274 * R9 (0x09) - Audio Interface 1 275 */ 276#define WM8961_DACCOMP_MASK 0x0018 /* DACCOMP - [4:3] */ 277#define WM8961_DACCOMP_SHIFT 3 /* DACCOMP - [4:3] */ 278#define WM8961_DACCOMP_WIDTH 2 /* DACCOMP - [4:3] */ 279#define WM8961_ADCCOMP_MASK 0x0006 /* ADCCOMP - [2:1] */ 280#define WM8961_ADCCOMP_SHIFT 1 /* ADCCOMP - [2:1] */ 281#define WM8961_ADCCOMP_WIDTH 2 /* ADCCOMP - [2:1] */ 282#define WM8961_LOOPBACK 0x0001 /* LOOPBACK */ 283#define WM8961_LOOPBACK_MASK 0x0001 /* LOOPBACK */ 284#define WM8961_LOOPBACK_SHIFT 0 /* LOOPBACK */ 285#define WM8961_LOOPBACK_WIDTH 1 /* LOOPBACK */ 286 287/* 288 * R10 (0x0A) - Left DAC volume 289 */ 290#define WM8961_DACVU 0x0100 /* DACVU */ 291#define WM8961_DACVU_MASK 0x0100 /* DACVU */ 292#define WM8961_DACVU_SHIFT 8 /* DACVU */ 293#define WM8961_DACVU_WIDTH 1 /* DACVU */ 294#define WM8961_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */ 295#define WM8961_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */ 296#define WM8961_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */ 297 298/* 299 * R11 (0x0B) - Right DAC volume 300 */ 301#define WM8961_DACVU 0x0100 /* DACVU */ 302#define WM8961_DACVU_MASK 0x0100 /* DACVU */ 303#define WM8961_DACVU_SHIFT 8 /* DACVU */ 304#define WM8961_DACVU_WIDTH 1 /* DACVU */ 305#define WM8961_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */ 306#define WM8961_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */ 307#define WM8961_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */ 308 309/* 310 * R14 (0x0E) - Audio Interface 2 311 */ 312#define WM8961_LRCLK_RATE_MASK 0x01FF /* LRCLK_RATE - [8:0] */ 313#define WM8961_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [8:0] */ 314#define WM8961_LRCLK_RATE_WIDTH 9 /* LRCLK_RATE - [8:0] */ 315 316/* 317 * R15 (0x0F) - Software Reset 318 */ 319#define WM8961_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 320#define WM8961_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 321#define WM8961_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 322 323/* 324 * R17 (0x11) - ALC1 325 */ 326#define WM8961_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ 327#define WM8961_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ 328#define WM8961_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ 329#define WM8961_MAXGAIN_MASK 0x0070 /* MAXGAIN - [6:4] */ 330#define WM8961_MAXGAIN_SHIFT 4 /* MAXGAIN - [6:4] */ 331#define WM8961_MAXGAIN_WIDTH 3 /* MAXGAIN - [6:4] */ 332#define WM8961_ALCL_MASK 0x000F /* ALCL - [3:0] */ 333#define WM8961_ALCL_SHIFT 0 /* ALCL - [3:0] */ 334#define WM8961_ALCL_WIDTH 4 /* ALCL - [3:0] */ 335 336/* 337 * R18 (0x12) - ALC2 338 */ 339#define WM8961_ALCZC 0x0080 /* ALCZC */ 340#define WM8961_ALCZC_MASK 0x0080 /* ALCZC */ 341#define WM8961_ALCZC_SHIFT 7 /* ALCZC */ 342#define WM8961_ALCZC_WIDTH 1 /* ALCZC */ 343#define WM8961_MINGAIN_MASK 0x0070 /* MINGAIN - [6:4] */ 344#define WM8961_MINGAIN_SHIFT 4 /* MINGAIN - [6:4] */ 345#define WM8961_MINGAIN_WIDTH 3 /* MINGAIN - [6:4] */ 346#define WM8961_HLD_MASK 0x000F /* HLD - [3:0] */ 347#define WM8961_HLD_SHIFT 0 /* HLD - [3:0] */ 348#define WM8961_HLD_WIDTH 4 /* HLD - [3:0] */ 349 350/* 351 * R19 (0x13) - ALC3 352 */ 353#define WM8961_ALCMODE 0x0100 /* ALCMODE */ 354#define WM8961_ALCMODE_MASK 0x0100 /* ALCMODE */ 355#define WM8961_ALCMODE_SHIFT 8 /* ALCMODE */ 356#define WM8961_ALCMODE_WIDTH 1 /* ALCMODE */ 357#define WM8961_DCY_MASK 0x00F0 /* DCY - [7:4] */ 358#define WM8961_DCY_SHIFT 4 /* DCY - [7:4] */ 359#define WM8961_DCY_WIDTH 4 /* DCY - [7:4] */ 360#define WM8961_ATK_MASK 0x000F /* ATK - [3:0] */ 361#define WM8961_ATK_SHIFT 0 /* ATK - [3:0] */ 362#define WM8961_ATK_WIDTH 4 /* ATK - [3:0] */ 363 364/* 365 * R20 (0x14) - Noise Gate 366 */ 367#define WM8961_NGTH_MASK 0x00F8 /* NGTH - [7:3] */ 368#define WM8961_NGTH_SHIFT 3 /* NGTH - [7:3] */ 369#define WM8961_NGTH_WIDTH 5 /* NGTH - [7:3] */ 370#define WM8961_NGG 0x0002 /* NGG */ 371#define WM8961_NGG_MASK 0x0002 /* NGG */ 372#define WM8961_NGG_SHIFT 1 /* NGG */ 373#define WM8961_NGG_WIDTH 1 /* NGG */ 374#define WM8961_NGAT 0x0001 /* NGAT */ 375#define WM8961_NGAT_MASK 0x0001 /* NGAT */ 376#define WM8961_NGAT_SHIFT 0 /* NGAT */ 377#define WM8961_NGAT_WIDTH 1 /* NGAT */ 378 379/* 380 * R21 (0x15) - Left ADC volume 381 */ 382#define WM8961_ADCVU 0x0100 /* ADCVU */ 383#define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ 384#define WM8961_ADCVU_SHIFT 8 /* ADCVU */ 385#define WM8961_ADCVU_WIDTH 1 /* ADCVU */ 386#define WM8961_LADCVOL_MASK 0x00FF /* LADCVOL - [7:0] */ 387#define WM8961_LADCVOL_SHIFT 0 /* LADCVOL - [7:0] */ 388#define WM8961_LADCVOL_WIDTH 8 /* LADCVOL - [7:0] */ 389 390/* 391 * R22 (0x16) - Right ADC volume 392 */ 393#define WM8961_ADCVU 0x0100 /* ADCVU */ 394#define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ 395#define WM8961_ADCVU_SHIFT 8 /* ADCVU */ 396#define WM8961_ADCVU_WIDTH 1 /* ADCVU */ 397#define WM8961_RADCVOL_MASK 0x00FF /* RADCVOL - [7:0] */ 398#define WM8961_RADCVOL_SHIFT 0 /* RADCVOL - [7:0] */ 399#define WM8961_RADCVOL_WIDTH 8 /* RADCVOL - [7:0] */ 400 401/* 402 * R23 (0x17) - Additional control(1) 403 */ 404#define WM8961_TSDEN 0x0100 /* TSDEN */ 405#define WM8961_TSDEN_MASK 0x0100 /* TSDEN */ 406#define WM8961_TSDEN_SHIFT 8 /* TSDEN */ 407#define WM8961_TSDEN_WIDTH 1 /* TSDEN */ 408#define WM8961_DMONOMIX 0x0010 /* DMONOMIX */ 409#define WM8961_DMONOMIX_MASK 0x0010 /* DMONOMIX */ 410#define WM8961_DMONOMIX_SHIFT 4 /* DMONOMIX */ 411#define WM8961_DMONOMIX_WIDTH 1 /* DMONOMIX */ 412#define WM8961_TOEN 0x0001 /* TOEN */ 413#define WM8961_TOEN_MASK 0x0001 /* TOEN */ 414#define WM8961_TOEN_SHIFT 0 /* TOEN */ 415#define WM8961_TOEN_WIDTH 1 /* TOEN */ 416 417/* 418 * R24 (0x18) - Additional control(2) 419 */ 420#define WM8961_TRIS 0x0008 /* TRIS */ 421#define WM8961_TRIS_MASK 0x0008 /* TRIS */ 422#define WM8961_TRIS_SHIFT 3 /* TRIS */ 423#define WM8961_TRIS_WIDTH 1 /* TRIS */ 424 425/* 426 * R25 (0x19) - Pwr Mgmt (1) 427 */ 428#define WM8961_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */ 429#define WM8961_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */ 430#define WM8961_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */ 431#define WM8961_VREF 0x0040 /* VREF */ 432#define WM8961_VREF_MASK 0x0040 /* VREF */ 433#define WM8961_VREF_SHIFT 6 /* VREF */ 434#define WM8961_VREF_WIDTH 1 /* VREF */ 435#define WM8961_AINL 0x0020 /* AINL */ 436#define WM8961_AINL_MASK 0x0020 /* AINL */ 437#define WM8961_AINL_SHIFT 5 /* AINL */ 438#define WM8961_AINL_WIDTH 1 /* AINL */ 439#define WM8961_AINR 0x0010 /* AINR */ 440#define WM8961_AINR_MASK 0x0010 /* AINR */ 441#define WM8961_AINR_SHIFT 4 /* AINR */ 442#define WM8961_AINR_WIDTH 1 /* AINR */ 443#define WM8961_ADCL 0x0008 /* ADCL */ 444#define WM8961_ADCL_MASK 0x0008 /* ADCL */ 445#define WM8961_ADCL_SHIFT 3 /* ADCL */ 446#define WM8961_ADCL_WIDTH 1 /* ADCL */ 447#define WM8961_ADCR 0x0004 /* ADCR */ 448#define WM8961_ADCR_MASK 0x0004 /* ADCR */ 449#define WM8961_ADCR_SHIFT 2 /* ADCR */ 450#define WM8961_ADCR_WIDTH 1 /* ADCR */ 451#define WM8961_MICB 0x0002 /* MICB */ 452#define WM8961_MICB_MASK 0x0002 /* MICB */ 453#define WM8961_MICB_SHIFT 1 /* MICB */ 454#define WM8961_MICB_WIDTH 1 /* MICB */ 455 456/* 457 * R26 (0x1A) - Pwr Mgmt (2) 458 */ 459#define WM8961_DACL 0x0100 /* DACL */ 460#define WM8961_DACL_MASK 0x0100 /* DACL */ 461#define WM8961_DACL_SHIFT 8 /* DACL */ 462#define WM8961_DACL_WIDTH 1 /* DACL */ 463#define WM8961_DACR 0x0080 /* DACR */ 464#define WM8961_DACR_MASK 0x0080 /* DACR */ 465#define WM8961_DACR_SHIFT 7 /* DACR */ 466#define WM8961_DACR_WIDTH 1 /* DACR */ 467#define WM8961_LOUT1_PGA 0x0040 /* LOUT1_PGA */ 468#define WM8961_LOUT1_PGA_MASK 0x0040 /* LOUT1_PGA */ 469#define WM8961_LOUT1_PGA_SHIFT 6 /* LOUT1_PGA */ 470#define WM8961_LOUT1_PGA_WIDTH 1 /* LOUT1_PGA */ 471#define WM8961_ROUT1_PGA 0x0020 /* ROUT1_PGA */ 472#define WM8961_ROUT1_PGA_MASK 0x0020 /* ROUT1_PGA */ 473#define WM8961_ROUT1_PGA_SHIFT 5 /* ROUT1_PGA */ 474#define WM8961_ROUT1_PGA_WIDTH 1 /* ROUT1_PGA */ 475#define WM8961_SPKL_PGA 0x0010 /* SPKL_PGA */ 476#define WM8961_SPKL_PGA_MASK 0x0010 /* SPKL_PGA */ 477#define WM8961_SPKL_PGA_SHIFT 4 /* SPKL_PGA */ 478#define WM8961_SPKL_PGA_WIDTH 1 /* SPKL_PGA */ 479#define WM8961_SPKR_PGA 0x0008 /* SPKR_PGA */ 480#define WM8961_SPKR_PGA_MASK 0x0008 /* SPKR_PGA */ 481#define WM8961_SPKR_PGA_SHIFT 3 /* SPKR_PGA */ 482#define WM8961_SPKR_PGA_WIDTH 1 /* SPKR_PGA */ 483 484/* 485 * R27 (0x1B) - Additional Control (3) 486 */ 487#define WM8961_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ 488#define WM8961_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ 489#define WM8961_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ 490 491/* 492 * R28 (0x1C) - Anti-pop 493 */ 494#define WM8961_BUFDCOPEN 0x0010 /* BUFDCOPEN */ 495#define WM8961_BUFDCOPEN_MASK 0x0010 /* BUFDCOPEN */ 496#define WM8961_BUFDCOPEN_SHIFT 4 /* BUFDCOPEN */ 497#define WM8961_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */ 498#define WM8961_BUFIOEN 0x0008 /* BUFIOEN */ 499#define WM8961_BUFIOEN_MASK 0x0008 /* BUFIOEN */ 500#define WM8961_BUFIOEN_SHIFT 3 /* BUFIOEN */ 501#define WM8961_BUFIOEN_WIDTH 1 /* BUFIOEN */ 502#define WM8961_SOFT_ST 0x0004 /* SOFT_ST */ 503#define WM8961_SOFT_ST_MASK 0x0004 /* SOFT_ST */ 504#define WM8961_SOFT_ST_SHIFT 2 /* SOFT_ST */ 505#define WM8961_SOFT_ST_WIDTH 1 /* SOFT_ST */ 506 507/* 508 * R30 (0x1E) - Clocking 3 509 */ 510#define WM8961_CLK_TO_DIV_MASK 0x0180 /* CLK_TO_DIV - [8:7] */ 511#define WM8961_CLK_TO_DIV_SHIFT 7 /* CLK_TO_DIV - [8:7] */ 512#define WM8961_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [8:7] */ 513#define WM8961_CLK_256K_DIV_MASK 0x007E /* CLK_256K_DIV - [6:1] */ 514#define WM8961_CLK_256K_DIV_SHIFT 1 /* CLK_256K_DIV - [6:1] */ 515#define WM8961_CLK_256K_DIV_WIDTH 6 /* CLK_256K_DIV - [6:1] */ 516#define WM8961_MANUAL_MODE 0x0001 /* MANUAL_MODE */ 517#define WM8961_MANUAL_MODE_MASK 0x0001 /* MANUAL_MODE */ 518#define WM8961_MANUAL_MODE_SHIFT 0 /* MANUAL_MODE */ 519#define WM8961_MANUAL_MODE_WIDTH 1 /* MANUAL_MODE */ 520 521/* 522 * R32 (0x20) - ADCL signal path 523 */ 524#define WM8961_LMICBOOST_MASK 0x0030 /* LMICBOOST - [5:4] */ 525#define WM8961_LMICBOOST_SHIFT 4 /* LMICBOOST - [5:4] */ 526#define WM8961_LMICBOOST_WIDTH 2 /* LMICBOOST - [5:4] */ 527 528/* 529 * R33 (0x21) - ADCR signal path 530 */ 531#define WM8961_RMICBOOST_MASK 0x0030 /* RMICBOOST - [5:4] */ 532#define WM8961_RMICBOOST_SHIFT 4 /* RMICBOOST - [5:4] */ 533#define WM8961_RMICBOOST_WIDTH 2 /* RMICBOOST - [5:4] */ 534 535/* 536 * R40 (0x28) - LOUT2 volume 537 */ 538#define WM8961_SPKVU 0x0100 /* SPKVU */ 539#define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ 540#define WM8961_SPKVU_SHIFT 8 /* SPKVU */ 541#define WM8961_SPKVU_WIDTH 1 /* SPKVU */ 542#define WM8961_SPKLZC 0x0080 /* SPKLZC */ 543#define WM8961_SPKLZC_MASK 0x0080 /* SPKLZC */ 544#define WM8961_SPKLZC_SHIFT 7 /* SPKLZC */ 545#define WM8961_SPKLZC_WIDTH 1 /* SPKLZC */ 546#define WM8961_SPKLVOL_MASK 0x007F /* SPKLVOL - [6:0] */ 547#define WM8961_SPKLVOL_SHIFT 0 /* SPKLVOL - [6:0] */ 548#define WM8961_SPKLVOL_WIDTH 7 /* SPKLVOL - [6:0] */ 549 550/* 551 * R41 (0x29) - ROUT2 volume 552 */ 553#define WM8961_SPKVU 0x0100 /* SPKVU */ 554#define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ 555#define WM8961_SPKVU_SHIFT 8 /* SPKVU */ 556#define WM8961_SPKVU_WIDTH 1 /* SPKVU */ 557#define WM8961_SPKRZC 0x0080 /* SPKRZC */ 558#define WM8961_SPKRZC_MASK 0x0080 /* SPKRZC */ 559#define WM8961_SPKRZC_SHIFT 7 /* SPKRZC */ 560#define WM8961_SPKRZC_WIDTH 1 /* SPKRZC */ 561#define WM8961_SPKRVOL_MASK 0x007F /* SPKRVOL - [6:0] */ 562#define WM8961_SPKRVOL_SHIFT 0 /* SPKRVOL - [6:0] */ 563#define WM8961_SPKRVOL_WIDTH 7 /* SPKRVOL - [6:0] */ 564 565/* 566 * R47 (0x2F) - Pwr Mgmt (3) 567 */ 568#define WM8961_TEMP_SHUT 0x0002 /* TEMP_SHUT */ 569#define WM8961_TEMP_SHUT_MASK 0x0002 /* TEMP_SHUT */ 570#define WM8961_TEMP_SHUT_SHIFT 1 /* TEMP_SHUT */ 571#define WM8961_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */ 572#define WM8961_TEMP_WARN 0x0001 /* TEMP_WARN */ 573#define WM8961_TEMP_WARN_MASK 0x0001 /* TEMP_WARN */ 574#define WM8961_TEMP_WARN_SHIFT 0 /* TEMP_WARN */ 575#define WM8961_TEMP_WARN_WIDTH 1 /* TEMP_WARN */ 576 577/* 578 * R48 (0x30) - Additional Control (4) 579 */ 580#define WM8961_TSENSEN 0x0002 /* TSENSEN */ 581#define WM8961_TSENSEN_MASK 0x0002 /* TSENSEN */ 582#define WM8961_TSENSEN_SHIFT 1 /* TSENSEN */ 583#define WM8961_TSENSEN_WIDTH 1 /* TSENSEN */ 584#define WM8961_MBSEL 0x0001 /* MBSEL */ 585#define WM8961_MBSEL_MASK 0x0001 /* MBSEL */ 586#define WM8961_MBSEL_SHIFT 0 /* MBSEL */ 587#define WM8961_MBSEL_WIDTH 1 /* MBSEL */ 588 589/* 590 * R49 (0x31) - Class D Control 1 591 */ 592#define WM8961_SPKR_ENA 0x0080 /* SPKR_ENA */ 593#define WM8961_SPKR_ENA_MASK 0x0080 /* SPKR_ENA */ 594#define WM8961_SPKR_ENA_SHIFT 7 /* SPKR_ENA */ 595#define WM8961_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 596#define WM8961_SPKL_ENA 0x0040 /* SPKL_ENA */ 597#define WM8961_SPKL_ENA_MASK 0x0040 /* SPKL_ENA */ 598#define WM8961_SPKL_ENA_SHIFT 6 /* SPKL_ENA */ 599#define WM8961_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 600 601/* 602 * R51 (0x33) - Class D Control 2 603 */ 604#define WM8961_CLASSD_ACGAIN_MASK 0x0007 /* CLASSD_ACGAIN - [2:0] */ 605#define WM8961_CLASSD_ACGAIN_SHIFT 0 /* CLASSD_ACGAIN - [2:0] */ 606#define WM8961_CLASSD_ACGAIN_WIDTH 3 /* CLASSD_ACGAIN - [2:0] */ 607 608/* 609 * R56 (0x38) - Clocking 4 610 */ 611#define WM8961_CLK_DCS_DIV_MASK 0x01E0 /* CLK_DCS_DIV - [8:5] */ 612#define WM8961_CLK_DCS_DIV_SHIFT 5 /* CLK_DCS_DIV - [8:5] */ 613#define WM8961_CLK_DCS_DIV_WIDTH 4 /* CLK_DCS_DIV - [8:5] */ 614#define WM8961_CLK_SYS_RATE_MASK 0x001E /* CLK_SYS_RATE - [4:1] */ 615#define WM8961_CLK_SYS_RATE_SHIFT 1 /* CLK_SYS_RATE - [4:1] */ 616#define WM8961_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [4:1] */ 617 618/* 619 * R57 (0x39) - DSP Sidetone 0 620 */ 621#define WM8961_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 622#define WM8961_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 623#define WM8961_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 624#define WM8961_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */ 625#define WM8961_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */ 626#define WM8961_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */ 627 628/* 629 * R58 (0x3A) - DSP Sidetone 1 630 */ 631#define WM8961_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */ 632#define WM8961_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */ 633#define WM8961_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */ 634#define WM8961_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 635#define WM8961_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 636#define WM8961_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 637 638/* 639 * R60 (0x3C) - DC Servo 0 640 */ 641#define WM8961_DCS_ENA_CHAN_INL 0x0080 /* DCS_ENA_CHAN_INL */ 642#define WM8961_DCS_ENA_CHAN_INL_MASK 0x0080 /* DCS_ENA_CHAN_INL */ 643#define WM8961_DCS_ENA_CHAN_INL_SHIFT 7 /* DCS_ENA_CHAN_INL */ 644#define WM8961_DCS_ENA_CHAN_INL_WIDTH 1 /* DCS_ENA_CHAN_INL */ 645#define WM8961_DCS_TRIG_STARTUP_INL 0x0040 /* DCS_TRIG_STARTUP_INL */ 646#define WM8961_DCS_TRIG_STARTUP_INL_MASK 0x0040 /* DCS_TRIG_STARTUP_INL */ 647#define WM8961_DCS_TRIG_STARTUP_INL_SHIFT 6 /* DCS_TRIG_STARTUP_INL */ 648#define WM8961_DCS_TRIG_STARTUP_INL_WIDTH 1 /* DCS_TRIG_STARTUP_INL */ 649#define WM8961_DCS_TRIG_SERIES_INL 0x0010 /* DCS_TRIG_SERIES_INL */ 650#define WM8961_DCS_TRIG_SERIES_INL_MASK 0x0010 /* DCS_TRIG_SERIES_INL */ 651#define WM8961_DCS_TRIG_SERIES_INL_SHIFT 4 /* DCS_TRIG_SERIES_INL */ 652#define WM8961_DCS_TRIG_SERIES_INL_WIDTH 1 /* DCS_TRIG_SERIES_INL */ 653#define WM8961_DCS_ENA_CHAN_INR 0x0008 /* DCS_ENA_CHAN_INR */ 654#define WM8961_DCS_ENA_CHAN_INR_MASK 0x0008 /* DCS_ENA_CHAN_INR */ 655#define WM8961_DCS_ENA_CHAN_INR_SHIFT 3 /* DCS_ENA_CHAN_INR */ 656#define WM8961_DCS_ENA_CHAN_INR_WIDTH 1 /* DCS_ENA_CHAN_INR */ 657#define WM8961_DCS_TRIG_STARTUP_INR 0x0004 /* DCS_TRIG_STARTUP_INR */ 658#define WM8961_DCS_TRIG_STARTUP_INR_MASK 0x0004 /* DCS_TRIG_STARTUP_INR */ 659#define WM8961_DCS_TRIG_STARTUP_INR_SHIFT 2 /* DCS_TRIG_STARTUP_INR */ 660#define WM8961_DCS_TRIG_STARTUP_INR_WIDTH 1 /* DCS_TRIG_STARTUP_INR */ 661#define WM8961_DCS_TRIG_SERIES_INR 0x0001 /* DCS_TRIG_SERIES_INR */ 662#define WM8961_DCS_TRIG_SERIES_INR_MASK 0x0001 /* DCS_TRIG_SERIES_INR */ 663#define WM8961_DCS_TRIG_SERIES_INR_SHIFT 0 /* DCS_TRIG_SERIES_INR */ 664#define WM8961_DCS_TRIG_SERIES_INR_WIDTH 1 /* DCS_TRIG_SERIES_INR */ 665 666/* 667 * R61 (0x3D) - DC Servo 1 668 */ 669#define WM8961_DCS_ENA_CHAN_HPL 0x0080 /* DCS_ENA_CHAN_HPL */ 670#define WM8961_DCS_ENA_CHAN_HPL_MASK 0x0080 /* DCS_ENA_CHAN_HPL */ 671#define WM8961_DCS_ENA_CHAN_HPL_SHIFT 7 /* DCS_ENA_CHAN_HPL */ 672#define WM8961_DCS_ENA_CHAN_HPL_WIDTH 1 /* DCS_ENA_CHAN_HPL */ 673#define WM8961_DCS_TRIG_STARTUP_HPL 0x0040 /* DCS_TRIG_STARTUP_HPL */ 674#define WM8961_DCS_TRIG_STARTUP_HPL_MASK 0x0040 /* DCS_TRIG_STARTUP_HPL */ 675#define WM8961_DCS_TRIG_STARTUP_HPL_SHIFT 6 /* DCS_TRIG_STARTUP_HPL */ 676#define WM8961_DCS_TRIG_STARTUP_HPL_WIDTH 1 /* DCS_TRIG_STARTUP_HPL */ 677#define WM8961_DCS_TRIG_SERIES_HPL 0x0010 /* DCS_TRIG_SERIES_HPL */ 678#define WM8961_DCS_TRIG_SERIES_HPL_MASK 0x0010 /* DCS_TRIG_SERIES_HPL */ 679#define WM8961_DCS_TRIG_SERIES_HPL_SHIFT 4 /* DCS_TRIG_SERIES_HPL */ 680#define WM8961_DCS_TRIG_SERIES_HPL_WIDTH 1 /* DCS_TRIG_SERIES_HPL */ 681#define WM8961_DCS_ENA_CHAN_HPR 0x0008 /* DCS_ENA_CHAN_HPR */ 682#define WM8961_DCS_ENA_CHAN_HPR_MASK 0x0008 /* DCS_ENA_CHAN_HPR */ 683#define WM8961_DCS_ENA_CHAN_HPR_SHIFT 3 /* DCS_ENA_CHAN_HPR */ 684#define WM8961_DCS_ENA_CHAN_HPR_WIDTH 1 /* DCS_ENA_CHAN_HPR */ 685#define WM8961_DCS_TRIG_STARTUP_HPR 0x0004 /* DCS_TRIG_STARTUP_HPR */ 686#define WM8961_DCS_TRIG_STARTUP_HPR_MASK 0x0004 /* DCS_TRIG_STARTUP_HPR */ 687#define WM8961_DCS_TRIG_STARTUP_HPR_SHIFT 2 /* DCS_TRIG_STARTUP_HPR */ 688#define WM8961_DCS_TRIG_STARTUP_HPR_WIDTH 1 /* DCS_TRIG_STARTUP_HPR */ 689#define WM8961_DCS_TRIG_SERIES_HPR 0x0001 /* DCS_TRIG_SERIES_HPR */ 690#define WM8961_DCS_TRIG_SERIES_HPR_MASK 0x0001 /* DCS_TRIG_SERIES_HPR */ 691#define WM8961_DCS_TRIG_SERIES_HPR_SHIFT 0 /* DCS_TRIG_SERIES_HPR */ 692#define WM8961_DCS_TRIG_SERIES_HPR_WIDTH 1 /* DCS_TRIG_SERIES_HPR */ 693 694/* 695 * R63 (0x3F) - DC Servo 3 696 */ 697#define WM8961_DCS_FILT_BW_SERIES_MASK 0x0030 /* DCS_FILT_BW_SERIES - [5:4] */ 698#define WM8961_DCS_FILT_BW_SERIES_SHIFT 4 /* DCS_FILT_BW_SERIES - [5:4] */ 699#define WM8961_DCS_FILT_BW_SERIES_WIDTH 2 /* DCS_FILT_BW_SERIES - [5:4] */ 700 701/* 702 * R65 (0x41) - DC Servo 5 703 */ 704#define WM8961_DCS_SERIES_NO_HP_MASK 0x007F /* DCS_SERIES_NO_HP - [6:0] */ 705#define WM8961_DCS_SERIES_NO_HP_SHIFT 0 /* DCS_SERIES_NO_HP - [6:0] */ 706#define WM8961_DCS_SERIES_NO_HP_WIDTH 7 /* DCS_SERIES_NO_HP - [6:0] */ 707 708/* 709 * R68 (0x44) - Analogue PGA Bias 710 */ 711#define WM8961_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */ 712#define WM8961_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */ 713#define WM8961_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */ 714 715/* 716 * R69 (0x45) - Analogue HP 0 717 */ 718#define WM8961_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 719#define WM8961_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 720#define WM8961_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 721#define WM8961_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 722#define WM8961_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 723#define WM8961_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 724#define WM8961_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 725#define WM8961_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 726#define WM8961_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 727#define WM8961_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 728#define WM8961_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 729#define WM8961_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 730#define WM8961_HPL_ENA 0x0010 /* HPL_ENA */ 731#define WM8961_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 732#define WM8961_HPL_ENA_SHIFT 4 /* HPL_ENA */ 733#define WM8961_HPL_ENA_WIDTH 1 /* HPL_ENA */ 734#define WM8961_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 735#define WM8961_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 736#define WM8961_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 737#define WM8961_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 738#define WM8961_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 739#define WM8961_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 740#define WM8961_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 741#define WM8961_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 742#define WM8961_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 743#define WM8961_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 744#define WM8961_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 745#define WM8961_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 746#define WM8961_HPR_ENA 0x0001 /* HPR_ENA */ 747#define WM8961_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 748#define WM8961_HPR_ENA_SHIFT 0 /* HPR_ENA */ 749#define WM8961_HPR_ENA_WIDTH 1 /* HPR_ENA */ 750 751/* 752 * R71 (0x47) - Analogue HP 2 753 */ 754#define WM8961_HPL_VOL_MASK 0x01C0 /* HPL_VOL - [8:6] */ 755#define WM8961_HPL_VOL_SHIFT 6 /* HPL_VOL - [8:6] */ 756#define WM8961_HPL_VOL_WIDTH 3 /* HPL_VOL - [8:6] */ 757#define WM8961_HPR_VOL_MASK 0x0038 /* HPR_VOL - [5:3] */ 758#define WM8961_HPR_VOL_SHIFT 3 /* HPR_VOL - [5:3] */ 759#define WM8961_HPR_VOL_WIDTH 3 /* HPR_VOL - [5:3] */ 760#define WM8961_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */ 761#define WM8961_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */ 762#define WM8961_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */ 763 764/* 765 * R72 (0x48) - Charge Pump 1 766 */ 767#define WM8961_CP_ENA 0x0001 /* CP_ENA */ 768#define WM8961_CP_ENA_MASK 0x0001 /* CP_ENA */ 769#define WM8961_CP_ENA_SHIFT 0 /* CP_ENA */ 770#define WM8961_CP_ENA_WIDTH 1 /* CP_ENA */ 771 772/* 773 * R82 (0x52) - Charge Pump B 774 */ 775#define WM8961_CP_DYN_PWR_MASK 0x0003 /* CP_DYN_PWR - [1:0] */ 776#define WM8961_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR - [1:0] */ 777#define WM8961_CP_DYN_PWR_WIDTH 2 /* CP_DYN_PWR - [1:0] */ 778 779/* 780 * R87 (0x57) - Write Sequencer 1 781 */ 782#define WM8961_WSEQ_ENA 0x0020 /* WSEQ_ENA */ 783#define WM8961_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */ 784#define WM8961_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */ 785#define WM8961_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 786#define WM8961_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 787#define WM8961_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 788#define WM8961_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 789 790/* 791 * R88 (0x58) - Write Sequencer 2 792 */ 793#define WM8961_WSEQ_EOS 0x0100 /* WSEQ_EOS */ 794#define WM8961_WSEQ_EOS_MASK 0x0100 /* WSEQ_EOS */ 795#define WM8961_WSEQ_EOS_SHIFT 8 /* WSEQ_EOS */ 796#define WM8961_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 797#define WM8961_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 798#define WM8961_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 799#define WM8961_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 800 801/* 802 * R89 (0x59) - Write Sequencer 3 803 */ 804#define WM8961_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 805#define WM8961_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 806#define WM8961_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 807 808/* 809 * R90 (0x5A) - Write Sequencer 4 810 */ 811#define WM8961_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */ 812#define WM8961_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */ 813#define WM8961_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */ 814#define WM8961_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 815#define WM8961_WSEQ_START 0x0080 /* WSEQ_START */ 816#define WM8961_WSEQ_START_MASK 0x0080 /* WSEQ_START */ 817#define WM8961_WSEQ_START_SHIFT 7 /* WSEQ_START */ 818#define WM8961_WSEQ_START_WIDTH 1 /* WSEQ_START */ 819#define WM8961_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 820#define WM8961_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 821#define WM8961_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 822 823/* 824 * R91 (0x5B) - Write Sequencer 5 825 */ 826#define WM8961_WSEQ_DATA_WIDTH_MASK 0x0070 /* WSEQ_DATA_WIDTH - [6:4] */ 827#define WM8961_WSEQ_DATA_WIDTH_SHIFT 4 /* WSEQ_DATA_WIDTH - [6:4] */ 828#define WM8961_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [6:4] */ 829#define WM8961_WSEQ_DATA_START_MASK 0x000F /* WSEQ_DATA_START - [3:0] */ 830#define WM8961_WSEQ_DATA_START_SHIFT 0 /* WSEQ_DATA_START - [3:0] */ 831#define WM8961_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [3:0] */ 832 833/* 834 * R92 (0x5C) - Write Sequencer 6 835 */ 836#define WM8961_WSEQ_DELAY_MASK 0x000F /* WSEQ_DELAY - [3:0] */ 837#define WM8961_WSEQ_DELAY_SHIFT 0 /* WSEQ_DELAY - [3:0] */ 838#define WM8961_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [3:0] */ 839 840/* 841 * R93 (0x5D) - Write Sequencer 7 842 */ 843#define WM8961_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 844#define WM8961_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 845#define WM8961_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 846#define WM8961_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 847 848/* 849 * R252 (0xFC) - General test 1 850 */ 851#define WM8961_ARA_ENA 0x0002 /* ARA_ENA */ 852#define WM8961_ARA_ENA_MASK 0x0002 /* ARA_ENA */ 853#define WM8961_ARA_ENA_SHIFT 1 /* ARA_ENA */ 854#define WM8961_ARA_ENA_WIDTH 1 /* ARA_ENA */ 855#define WM8961_AUTO_INC 0x0001 /* AUTO_INC */ 856#define WM8961_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 857#define WM8961_AUTO_INC_SHIFT 0 /* AUTO_INC */ 858#define WM8961_AUTO_INC_WIDTH 1 /* AUTO_INC */ 859 860#endif