wm8995.h (251957B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * wm8995.h -- WM8995 ALSA SoC Audio driver 4 * 5 * Copyright 2010 Wolfson Microelectronics plc 6 * 7 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8 */ 9 10#ifndef _WM8995_H 11#define _WM8995_H 12 13#include <asm/types.h> 14 15/* 16 * Register values. 17 */ 18#define WM8995_SOFTWARE_RESET 0x00 19#define WM8995_POWER_MANAGEMENT_1 0x01 20#define WM8995_POWER_MANAGEMENT_2 0x02 21#define WM8995_POWER_MANAGEMENT_3 0x03 22#define WM8995_POWER_MANAGEMENT_4 0x04 23#define WM8995_POWER_MANAGEMENT_5 0x05 24#define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10 25#define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11 26#define WM8995_LEFT_LINE_INPUT_CONTROL 0x12 27#define WM8995_DAC1_LEFT_VOLUME 0x18 28#define WM8995_DAC1_RIGHT_VOLUME 0x19 29#define WM8995_DAC2_LEFT_VOLUME 0x1A 30#define WM8995_DAC2_RIGHT_VOLUME 0x1B 31#define WM8995_OUTPUT_VOLUME_ZC_1 0x1C 32#define WM8995_MICBIAS_1 0x20 33#define WM8995_MICBIAS_2 0x21 34#define WM8995_LDO_1 0x28 35#define WM8995_LDO_2 0x29 36#define WM8995_ACCESSORY_DETECT_MODE1 0x30 37#define WM8995_ACCESSORY_DETECT_MODE2 0x31 38#define WM8995_HEADPHONE_DETECT1 0x34 39#define WM8995_HEADPHONE_DETECT2 0x35 40#define WM8995_MIC_DETECT_1 0x38 41#define WM8995_MIC_DETECT_2 0x39 42#define WM8995_CHARGE_PUMP_1 0x40 43#define WM8995_CLASS_W_1 0x45 44#define WM8995_DC_SERVO_1 0x50 45#define WM8995_DC_SERVO_2 0x51 46#define WM8995_DC_SERVO_3 0x52 47#define WM8995_DC_SERVO_5 0x54 48#define WM8995_DC_SERVO_6 0x55 49#define WM8995_DC_SERVO_7 0x56 50#define WM8995_DC_SERVO_READBACK_0 0x57 51#define WM8995_ANALOGUE_HP_1 0x60 52#define WM8995_ANALOGUE_HP_2 0x61 53#define WM8995_CHIP_REVISION 0x100 54#define WM8995_CONTROL_INTERFACE_1 0x101 55#define WM8995_CONTROL_INTERFACE_2 0x102 56#define WM8995_WRITE_SEQUENCER_CTRL_1 0x110 57#define WM8995_WRITE_SEQUENCER_CTRL_2 0x111 58#define WM8995_AIF1_CLOCKING_1 0x200 59#define WM8995_AIF1_CLOCKING_2 0x201 60#define WM8995_AIF2_CLOCKING_1 0x204 61#define WM8995_AIF2_CLOCKING_2 0x205 62#define WM8995_CLOCKING_1 0x208 63#define WM8995_CLOCKING_2 0x209 64#define WM8995_AIF1_RATE 0x210 65#define WM8995_AIF2_RATE 0x211 66#define WM8995_RATE_STATUS 0x212 67#define WM8995_FLL1_CONTROL_1 0x220 68#define WM8995_FLL1_CONTROL_2 0x221 69#define WM8995_FLL1_CONTROL_3 0x222 70#define WM8995_FLL1_CONTROL_4 0x223 71#define WM8995_FLL1_CONTROL_5 0x224 72#define WM8995_FLL2_CONTROL_1 0x240 73#define WM8995_FLL2_CONTROL_2 0x241 74#define WM8995_FLL2_CONTROL_3 0x242 75#define WM8995_FLL2_CONTROL_4 0x243 76#define WM8995_FLL2_CONTROL_5 0x244 77#define WM8995_AIF1_CONTROL_1 0x300 78#define WM8995_AIF1_CONTROL_2 0x301 79#define WM8995_AIF1_MASTER_SLAVE 0x302 80#define WM8995_AIF1_BCLK 0x303 81#define WM8995_AIF1ADC_LRCLK 0x304 82#define WM8995_AIF1DAC_LRCLK 0x305 83#define WM8995_AIF1DAC_DATA 0x306 84#define WM8995_AIF1ADC_DATA 0x307 85#define WM8995_AIF2_CONTROL_1 0x310 86#define WM8995_AIF2_CONTROL_2 0x311 87#define WM8995_AIF2_MASTER_SLAVE 0x312 88#define WM8995_AIF2_BCLK 0x313 89#define WM8995_AIF2ADC_LRCLK 0x314 90#define WM8995_AIF2DAC_LRCLK 0x315 91#define WM8995_AIF2DAC_DATA 0x316 92#define WM8995_AIF2ADC_DATA 0x317 93#define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400 94#define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401 95#define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402 96#define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403 97#define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404 98#define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405 99#define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406 100#define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407 101#define WM8995_AIF1_ADC1_FILTERS 0x410 102#define WM8995_AIF1_ADC2_FILTERS 0x411 103#define WM8995_AIF1_DAC1_FILTERS_1 0x420 104#define WM8995_AIF1_DAC1_FILTERS_2 0x421 105#define WM8995_AIF1_DAC2_FILTERS_1 0x422 106#define WM8995_AIF1_DAC2_FILTERS_2 0x423 107#define WM8995_AIF1_DRC1_1 0x440 108#define WM8995_AIF1_DRC1_2 0x441 109#define WM8995_AIF1_DRC1_3 0x442 110#define WM8995_AIF1_DRC1_4 0x443 111#define WM8995_AIF1_DRC1_5 0x444 112#define WM8995_AIF1_DRC2_1 0x450 113#define WM8995_AIF1_DRC2_2 0x451 114#define WM8995_AIF1_DRC2_3 0x452 115#define WM8995_AIF1_DRC2_4 0x453 116#define WM8995_AIF1_DRC2_5 0x454 117#define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480 118#define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481 119#define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482 120#define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483 121#define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484 122#define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485 123#define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486 124#define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487 125#define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488 126#define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489 127#define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A 128#define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B 129#define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C 130#define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D 131#define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E 132#define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F 133#define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490 134#define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491 135#define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492 136#define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493 137#define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0 138#define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1 139#define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2 140#define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3 141#define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 142#define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5 143#define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6 144#define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7 145#define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 146#define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9 147#define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA 148#define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB 149#define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC 150#define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD 151#define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE 152#define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF 153#define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 154#define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1 155#define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2 156#define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 157#define WM8995_AIF2_ADC_LEFT_VOLUME 0x500 158#define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501 159#define WM8995_AIF2_DAC_LEFT_VOLUME 0x502 160#define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503 161#define WM8995_AIF2_ADC_FILTERS 0x510 162#define WM8995_AIF2_DAC_FILTERS_1 0x520 163#define WM8995_AIF2_DAC_FILTERS_2 0x521 164#define WM8995_AIF2_DRC_1 0x540 165#define WM8995_AIF2_DRC_2 0x541 166#define WM8995_AIF2_DRC_3 0x542 167#define WM8995_AIF2_DRC_4 0x543 168#define WM8995_AIF2_DRC_5 0x544 169#define WM8995_AIF2_EQ_GAINS_1 0x580 170#define WM8995_AIF2_EQ_GAINS_2 0x581 171#define WM8995_AIF2_EQ_BAND_1_A 0x582 172#define WM8995_AIF2_EQ_BAND_1_B 0x583 173#define WM8995_AIF2_EQ_BAND_1_PG 0x584 174#define WM8995_AIF2_EQ_BAND_2_A 0x585 175#define WM8995_AIF2_EQ_BAND_2_B 0x586 176#define WM8995_AIF2_EQ_BAND_2_C 0x587 177#define WM8995_AIF2_EQ_BAND_2_PG 0x588 178#define WM8995_AIF2_EQ_BAND_3_A 0x589 179#define WM8995_AIF2_EQ_BAND_3_B 0x58A 180#define WM8995_AIF2_EQ_BAND_3_C 0x58B 181#define WM8995_AIF2_EQ_BAND_3_PG 0x58C 182#define WM8995_AIF2_EQ_BAND_4_A 0x58D 183#define WM8995_AIF2_EQ_BAND_4_B 0x58E 184#define WM8995_AIF2_EQ_BAND_4_C 0x58F 185#define WM8995_AIF2_EQ_BAND_4_PG 0x590 186#define WM8995_AIF2_EQ_BAND_5_A 0x591 187#define WM8995_AIF2_EQ_BAND_5_B 0x592 188#define WM8995_AIF2_EQ_BAND_5_PG 0x593 189#define WM8995_DAC1_MIXER_VOLUMES 0x600 190#define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601 191#define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602 192#define WM8995_DAC2_MIXER_VOLUMES 0x603 193#define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604 194#define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605 195#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 196#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 197#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 198#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 199#define WM8995_DAC_SOFTMUTE 0x610 200#define WM8995_OVERSAMPLING 0x620 201#define WM8995_SIDETONE 0x621 202#define WM8995_GPIO_1 0x700 203#define WM8995_GPIO_2 0x701 204#define WM8995_GPIO_3 0x702 205#define WM8995_GPIO_4 0x703 206#define WM8995_GPIO_5 0x704 207#define WM8995_GPIO_6 0x705 208#define WM8995_GPIO_7 0x706 209#define WM8995_GPIO_8 0x707 210#define WM8995_GPIO_9 0x708 211#define WM8995_GPIO_10 0x709 212#define WM8995_GPIO_11 0x70A 213#define WM8995_GPIO_12 0x70B 214#define WM8995_GPIO_13 0x70C 215#define WM8995_GPIO_14 0x70D 216#define WM8995_PULL_CONTROL_1 0x720 217#define WM8995_PULL_CONTROL_2 0x721 218#define WM8995_INTERRUPT_STATUS_1 0x730 219#define WM8995_INTERRUPT_STATUS_2 0x731 220#define WM8995_INTERRUPT_RAW_STATUS_2 0x732 221#define WM8995_INTERRUPT_STATUS_1_MASK 0x738 222#define WM8995_INTERRUPT_STATUS_2_MASK 0x739 223#define WM8995_INTERRUPT_CONTROL 0x740 224#define WM8995_LEFT_PDM_SPEAKER_1 0x800 225#define WM8995_RIGHT_PDM_SPEAKER_1 0x801 226#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802 227#define WM8995_LEFT_PDM_SPEAKER_2 0x808 228#define WM8995_RIGHT_PDM_SPEAKER_2 0x809 229#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A 230#define WM8995_WRITE_SEQUENCER_0 0x3000 231#define WM8995_WRITE_SEQUENCER_1 0x3001 232#define WM8995_WRITE_SEQUENCER_2 0x3002 233#define WM8995_WRITE_SEQUENCER_3 0x3003 234#define WM8995_WRITE_SEQUENCER_4 0x3004 235#define WM8995_WRITE_SEQUENCER_5 0x3005 236#define WM8995_WRITE_SEQUENCER_6 0x3006 237#define WM8995_WRITE_SEQUENCER_7 0x3007 238#define WM8995_WRITE_SEQUENCER_8 0x3008 239#define WM8995_WRITE_SEQUENCER_9 0x3009 240#define WM8995_WRITE_SEQUENCER_10 0x300A 241#define WM8995_WRITE_SEQUENCER_11 0x300B 242#define WM8995_WRITE_SEQUENCER_12 0x300C 243#define WM8995_WRITE_SEQUENCER_13 0x300D 244#define WM8995_WRITE_SEQUENCER_14 0x300E 245#define WM8995_WRITE_SEQUENCER_15 0x300F 246#define WM8995_WRITE_SEQUENCER_16 0x3010 247#define WM8995_WRITE_SEQUENCER_17 0x3011 248#define WM8995_WRITE_SEQUENCER_18 0x3012 249#define WM8995_WRITE_SEQUENCER_19 0x3013 250#define WM8995_WRITE_SEQUENCER_20 0x3014 251#define WM8995_WRITE_SEQUENCER_21 0x3015 252#define WM8995_WRITE_SEQUENCER_22 0x3016 253#define WM8995_WRITE_SEQUENCER_23 0x3017 254#define WM8995_WRITE_SEQUENCER_24 0x3018 255#define WM8995_WRITE_SEQUENCER_25 0x3019 256#define WM8995_WRITE_SEQUENCER_26 0x301A 257#define WM8995_WRITE_SEQUENCER_27 0x301B 258#define WM8995_WRITE_SEQUENCER_28 0x301C 259#define WM8995_WRITE_SEQUENCER_29 0x301D 260#define WM8995_WRITE_SEQUENCER_30 0x301E 261#define WM8995_WRITE_SEQUENCER_31 0x301F 262#define WM8995_WRITE_SEQUENCER_32 0x3020 263#define WM8995_WRITE_SEQUENCER_33 0x3021 264#define WM8995_WRITE_SEQUENCER_34 0x3022 265#define WM8995_WRITE_SEQUENCER_35 0x3023 266#define WM8995_WRITE_SEQUENCER_36 0x3024 267#define WM8995_WRITE_SEQUENCER_37 0x3025 268#define WM8995_WRITE_SEQUENCER_38 0x3026 269#define WM8995_WRITE_SEQUENCER_39 0x3027 270#define WM8995_WRITE_SEQUENCER_40 0x3028 271#define WM8995_WRITE_SEQUENCER_41 0x3029 272#define WM8995_WRITE_SEQUENCER_42 0x302A 273#define WM8995_WRITE_SEQUENCER_43 0x302B 274#define WM8995_WRITE_SEQUENCER_44 0x302C 275#define WM8995_WRITE_SEQUENCER_45 0x302D 276#define WM8995_WRITE_SEQUENCER_46 0x302E 277#define WM8995_WRITE_SEQUENCER_47 0x302F 278#define WM8995_WRITE_SEQUENCER_48 0x3030 279#define WM8995_WRITE_SEQUENCER_49 0x3031 280#define WM8995_WRITE_SEQUENCER_50 0x3032 281#define WM8995_WRITE_SEQUENCER_51 0x3033 282#define WM8995_WRITE_SEQUENCER_52 0x3034 283#define WM8995_WRITE_SEQUENCER_53 0x3035 284#define WM8995_WRITE_SEQUENCER_54 0x3036 285#define WM8995_WRITE_SEQUENCER_55 0x3037 286#define WM8995_WRITE_SEQUENCER_56 0x3038 287#define WM8995_WRITE_SEQUENCER_57 0x3039 288#define WM8995_WRITE_SEQUENCER_58 0x303A 289#define WM8995_WRITE_SEQUENCER_59 0x303B 290#define WM8995_WRITE_SEQUENCER_60 0x303C 291#define WM8995_WRITE_SEQUENCER_61 0x303D 292#define WM8995_WRITE_SEQUENCER_62 0x303E 293#define WM8995_WRITE_SEQUENCER_63 0x303F 294#define WM8995_WRITE_SEQUENCER_64 0x3040 295#define WM8995_WRITE_SEQUENCER_65 0x3041 296#define WM8995_WRITE_SEQUENCER_66 0x3042 297#define WM8995_WRITE_SEQUENCER_67 0x3043 298#define WM8995_WRITE_SEQUENCER_68 0x3044 299#define WM8995_WRITE_SEQUENCER_69 0x3045 300#define WM8995_WRITE_SEQUENCER_70 0x3046 301#define WM8995_WRITE_SEQUENCER_71 0x3047 302#define WM8995_WRITE_SEQUENCER_72 0x3048 303#define WM8995_WRITE_SEQUENCER_73 0x3049 304#define WM8995_WRITE_SEQUENCER_74 0x304A 305#define WM8995_WRITE_SEQUENCER_75 0x304B 306#define WM8995_WRITE_SEQUENCER_76 0x304C 307#define WM8995_WRITE_SEQUENCER_77 0x304D 308#define WM8995_WRITE_SEQUENCER_78 0x304E 309#define WM8995_WRITE_SEQUENCER_79 0x304F 310#define WM8995_WRITE_SEQUENCER_80 0x3050 311#define WM8995_WRITE_SEQUENCER_81 0x3051 312#define WM8995_WRITE_SEQUENCER_82 0x3052 313#define WM8995_WRITE_SEQUENCER_83 0x3053 314#define WM8995_WRITE_SEQUENCER_84 0x3054 315#define WM8995_WRITE_SEQUENCER_85 0x3055 316#define WM8995_WRITE_SEQUENCER_86 0x3056 317#define WM8995_WRITE_SEQUENCER_87 0x3057 318#define WM8995_WRITE_SEQUENCER_88 0x3058 319#define WM8995_WRITE_SEQUENCER_89 0x3059 320#define WM8995_WRITE_SEQUENCER_90 0x305A 321#define WM8995_WRITE_SEQUENCER_91 0x305B 322#define WM8995_WRITE_SEQUENCER_92 0x305C 323#define WM8995_WRITE_SEQUENCER_93 0x305D 324#define WM8995_WRITE_SEQUENCER_94 0x305E 325#define WM8995_WRITE_SEQUENCER_95 0x305F 326#define WM8995_WRITE_SEQUENCER_96 0x3060 327#define WM8995_WRITE_SEQUENCER_97 0x3061 328#define WM8995_WRITE_SEQUENCER_98 0x3062 329#define WM8995_WRITE_SEQUENCER_99 0x3063 330#define WM8995_WRITE_SEQUENCER_100 0x3064 331#define WM8995_WRITE_SEQUENCER_101 0x3065 332#define WM8995_WRITE_SEQUENCER_102 0x3066 333#define WM8995_WRITE_SEQUENCER_103 0x3067 334#define WM8995_WRITE_SEQUENCER_104 0x3068 335#define WM8995_WRITE_SEQUENCER_105 0x3069 336#define WM8995_WRITE_SEQUENCER_106 0x306A 337#define WM8995_WRITE_SEQUENCER_107 0x306B 338#define WM8995_WRITE_SEQUENCER_108 0x306C 339#define WM8995_WRITE_SEQUENCER_109 0x306D 340#define WM8995_WRITE_SEQUENCER_110 0x306E 341#define WM8995_WRITE_SEQUENCER_111 0x306F 342#define WM8995_WRITE_SEQUENCER_112 0x3070 343#define WM8995_WRITE_SEQUENCER_113 0x3071 344#define WM8995_WRITE_SEQUENCER_114 0x3072 345#define WM8995_WRITE_SEQUENCER_115 0x3073 346#define WM8995_WRITE_SEQUENCER_116 0x3074 347#define WM8995_WRITE_SEQUENCER_117 0x3075 348#define WM8995_WRITE_SEQUENCER_118 0x3076 349#define WM8995_WRITE_SEQUENCER_119 0x3077 350#define WM8995_WRITE_SEQUENCER_120 0x3078 351#define WM8995_WRITE_SEQUENCER_121 0x3079 352#define WM8995_WRITE_SEQUENCER_122 0x307A 353#define WM8995_WRITE_SEQUENCER_123 0x307B 354#define WM8995_WRITE_SEQUENCER_124 0x307C 355#define WM8995_WRITE_SEQUENCER_125 0x307D 356#define WM8995_WRITE_SEQUENCER_126 0x307E 357#define WM8995_WRITE_SEQUENCER_127 0x307F 358#define WM8995_WRITE_SEQUENCER_128 0x3080 359#define WM8995_WRITE_SEQUENCER_129 0x3081 360#define WM8995_WRITE_SEQUENCER_130 0x3082 361#define WM8995_WRITE_SEQUENCER_131 0x3083 362#define WM8995_WRITE_SEQUENCER_132 0x3084 363#define WM8995_WRITE_SEQUENCER_133 0x3085 364#define WM8995_WRITE_SEQUENCER_134 0x3086 365#define WM8995_WRITE_SEQUENCER_135 0x3087 366#define WM8995_WRITE_SEQUENCER_136 0x3088 367#define WM8995_WRITE_SEQUENCER_137 0x3089 368#define WM8995_WRITE_SEQUENCER_138 0x308A 369#define WM8995_WRITE_SEQUENCER_139 0x308B 370#define WM8995_WRITE_SEQUENCER_140 0x308C 371#define WM8995_WRITE_SEQUENCER_141 0x308D 372#define WM8995_WRITE_SEQUENCER_142 0x308E 373#define WM8995_WRITE_SEQUENCER_143 0x308F 374#define WM8995_WRITE_SEQUENCER_144 0x3090 375#define WM8995_WRITE_SEQUENCER_145 0x3091 376#define WM8995_WRITE_SEQUENCER_146 0x3092 377#define WM8995_WRITE_SEQUENCER_147 0x3093 378#define WM8995_WRITE_SEQUENCER_148 0x3094 379#define WM8995_WRITE_SEQUENCER_149 0x3095 380#define WM8995_WRITE_SEQUENCER_150 0x3096 381#define WM8995_WRITE_SEQUENCER_151 0x3097 382#define WM8995_WRITE_SEQUENCER_152 0x3098 383#define WM8995_WRITE_SEQUENCER_153 0x3099 384#define WM8995_WRITE_SEQUENCER_154 0x309A 385#define WM8995_WRITE_SEQUENCER_155 0x309B 386#define WM8995_WRITE_SEQUENCER_156 0x309C 387#define WM8995_WRITE_SEQUENCER_157 0x309D 388#define WM8995_WRITE_SEQUENCER_158 0x309E 389#define WM8995_WRITE_SEQUENCER_159 0x309F 390#define WM8995_WRITE_SEQUENCER_160 0x30A0 391#define WM8995_WRITE_SEQUENCER_161 0x30A1 392#define WM8995_WRITE_SEQUENCER_162 0x30A2 393#define WM8995_WRITE_SEQUENCER_163 0x30A3 394#define WM8995_WRITE_SEQUENCER_164 0x30A4 395#define WM8995_WRITE_SEQUENCER_165 0x30A5 396#define WM8995_WRITE_SEQUENCER_166 0x30A6 397#define WM8995_WRITE_SEQUENCER_167 0x30A7 398#define WM8995_WRITE_SEQUENCER_168 0x30A8 399#define WM8995_WRITE_SEQUENCER_169 0x30A9 400#define WM8995_WRITE_SEQUENCER_170 0x30AA 401#define WM8995_WRITE_SEQUENCER_171 0x30AB 402#define WM8995_WRITE_SEQUENCER_172 0x30AC 403#define WM8995_WRITE_SEQUENCER_173 0x30AD 404#define WM8995_WRITE_SEQUENCER_174 0x30AE 405#define WM8995_WRITE_SEQUENCER_175 0x30AF 406#define WM8995_WRITE_SEQUENCER_176 0x30B0 407#define WM8995_WRITE_SEQUENCER_177 0x30B1 408#define WM8995_WRITE_SEQUENCER_178 0x30B2 409#define WM8995_WRITE_SEQUENCER_179 0x30B3 410#define WM8995_WRITE_SEQUENCER_180 0x30B4 411#define WM8995_WRITE_SEQUENCER_181 0x30B5 412#define WM8995_WRITE_SEQUENCER_182 0x30B6 413#define WM8995_WRITE_SEQUENCER_183 0x30B7 414#define WM8995_WRITE_SEQUENCER_184 0x30B8 415#define WM8995_WRITE_SEQUENCER_185 0x30B9 416#define WM8995_WRITE_SEQUENCER_186 0x30BA 417#define WM8995_WRITE_SEQUENCER_187 0x30BB 418#define WM8995_WRITE_SEQUENCER_188 0x30BC 419#define WM8995_WRITE_SEQUENCER_189 0x30BD 420#define WM8995_WRITE_SEQUENCER_190 0x30BE 421#define WM8995_WRITE_SEQUENCER_191 0x30BF 422#define WM8995_WRITE_SEQUENCER_192 0x30C0 423#define WM8995_WRITE_SEQUENCER_193 0x30C1 424#define WM8995_WRITE_SEQUENCER_194 0x30C2 425#define WM8995_WRITE_SEQUENCER_195 0x30C3 426#define WM8995_WRITE_SEQUENCER_196 0x30C4 427#define WM8995_WRITE_SEQUENCER_197 0x30C5 428#define WM8995_WRITE_SEQUENCER_198 0x30C6 429#define WM8995_WRITE_SEQUENCER_199 0x30C7 430#define WM8995_WRITE_SEQUENCER_200 0x30C8 431#define WM8995_WRITE_SEQUENCER_201 0x30C9 432#define WM8995_WRITE_SEQUENCER_202 0x30CA 433#define WM8995_WRITE_SEQUENCER_203 0x30CB 434#define WM8995_WRITE_SEQUENCER_204 0x30CC 435#define WM8995_WRITE_SEQUENCER_205 0x30CD 436#define WM8995_WRITE_SEQUENCER_206 0x30CE 437#define WM8995_WRITE_SEQUENCER_207 0x30CF 438#define WM8995_WRITE_SEQUENCER_208 0x30D0 439#define WM8995_WRITE_SEQUENCER_209 0x30D1 440#define WM8995_WRITE_SEQUENCER_210 0x30D2 441#define WM8995_WRITE_SEQUENCER_211 0x30D3 442#define WM8995_WRITE_SEQUENCER_212 0x30D4 443#define WM8995_WRITE_SEQUENCER_213 0x30D5 444#define WM8995_WRITE_SEQUENCER_214 0x30D6 445#define WM8995_WRITE_SEQUENCER_215 0x30D7 446#define WM8995_WRITE_SEQUENCER_216 0x30D8 447#define WM8995_WRITE_SEQUENCER_217 0x30D9 448#define WM8995_WRITE_SEQUENCER_218 0x30DA 449#define WM8995_WRITE_SEQUENCER_219 0x30DB 450#define WM8995_WRITE_SEQUENCER_220 0x30DC 451#define WM8995_WRITE_SEQUENCER_221 0x30DD 452#define WM8995_WRITE_SEQUENCER_222 0x30DE 453#define WM8995_WRITE_SEQUENCER_223 0x30DF 454#define WM8995_WRITE_SEQUENCER_224 0x30E0 455#define WM8995_WRITE_SEQUENCER_225 0x30E1 456#define WM8995_WRITE_SEQUENCER_226 0x30E2 457#define WM8995_WRITE_SEQUENCER_227 0x30E3 458#define WM8995_WRITE_SEQUENCER_228 0x30E4 459#define WM8995_WRITE_SEQUENCER_229 0x30E5 460#define WM8995_WRITE_SEQUENCER_230 0x30E6 461#define WM8995_WRITE_SEQUENCER_231 0x30E7 462#define WM8995_WRITE_SEQUENCER_232 0x30E8 463#define WM8995_WRITE_SEQUENCER_233 0x30E9 464#define WM8995_WRITE_SEQUENCER_234 0x30EA 465#define WM8995_WRITE_SEQUENCER_235 0x30EB 466#define WM8995_WRITE_SEQUENCER_236 0x30EC 467#define WM8995_WRITE_SEQUENCER_237 0x30ED 468#define WM8995_WRITE_SEQUENCER_238 0x30EE 469#define WM8995_WRITE_SEQUENCER_239 0x30EF 470#define WM8995_WRITE_SEQUENCER_240 0x30F0 471#define WM8995_WRITE_SEQUENCER_241 0x30F1 472#define WM8995_WRITE_SEQUENCER_242 0x30F2 473#define WM8995_WRITE_SEQUENCER_243 0x30F3 474#define WM8995_WRITE_SEQUENCER_244 0x30F4 475#define WM8995_WRITE_SEQUENCER_245 0x30F5 476#define WM8995_WRITE_SEQUENCER_246 0x30F6 477#define WM8995_WRITE_SEQUENCER_247 0x30F7 478#define WM8995_WRITE_SEQUENCER_248 0x30F8 479#define WM8995_WRITE_SEQUENCER_249 0x30F9 480#define WM8995_WRITE_SEQUENCER_250 0x30FA 481#define WM8995_WRITE_SEQUENCER_251 0x30FB 482#define WM8995_WRITE_SEQUENCER_252 0x30FC 483#define WM8995_WRITE_SEQUENCER_253 0x30FD 484#define WM8995_WRITE_SEQUENCER_254 0x30FE 485#define WM8995_WRITE_SEQUENCER_255 0x30FF 486#define WM8995_WRITE_SEQUENCER_256 0x3100 487#define WM8995_WRITE_SEQUENCER_257 0x3101 488#define WM8995_WRITE_SEQUENCER_258 0x3102 489#define WM8995_WRITE_SEQUENCER_259 0x3103 490#define WM8995_WRITE_SEQUENCER_260 0x3104 491#define WM8995_WRITE_SEQUENCER_261 0x3105 492#define WM8995_WRITE_SEQUENCER_262 0x3106 493#define WM8995_WRITE_SEQUENCER_263 0x3107 494#define WM8995_WRITE_SEQUENCER_264 0x3108 495#define WM8995_WRITE_SEQUENCER_265 0x3109 496#define WM8995_WRITE_SEQUENCER_266 0x310A 497#define WM8995_WRITE_SEQUENCER_267 0x310B 498#define WM8995_WRITE_SEQUENCER_268 0x310C 499#define WM8995_WRITE_SEQUENCER_269 0x310D 500#define WM8995_WRITE_SEQUENCER_270 0x310E 501#define WM8995_WRITE_SEQUENCER_271 0x310F 502#define WM8995_WRITE_SEQUENCER_272 0x3110 503#define WM8995_WRITE_SEQUENCER_273 0x3111 504#define WM8995_WRITE_SEQUENCER_274 0x3112 505#define WM8995_WRITE_SEQUENCER_275 0x3113 506#define WM8995_WRITE_SEQUENCER_276 0x3114 507#define WM8995_WRITE_SEQUENCER_277 0x3115 508#define WM8995_WRITE_SEQUENCER_278 0x3116 509#define WM8995_WRITE_SEQUENCER_279 0x3117 510#define WM8995_WRITE_SEQUENCER_280 0x3118 511#define WM8995_WRITE_SEQUENCER_281 0x3119 512#define WM8995_WRITE_SEQUENCER_282 0x311A 513#define WM8995_WRITE_SEQUENCER_283 0x311B 514#define WM8995_WRITE_SEQUENCER_284 0x311C 515#define WM8995_WRITE_SEQUENCER_285 0x311D 516#define WM8995_WRITE_SEQUENCER_286 0x311E 517#define WM8995_WRITE_SEQUENCER_287 0x311F 518#define WM8995_WRITE_SEQUENCER_288 0x3120 519#define WM8995_WRITE_SEQUENCER_289 0x3121 520#define WM8995_WRITE_SEQUENCER_290 0x3122 521#define WM8995_WRITE_SEQUENCER_291 0x3123 522#define WM8995_WRITE_SEQUENCER_292 0x3124 523#define WM8995_WRITE_SEQUENCER_293 0x3125 524#define WM8995_WRITE_SEQUENCER_294 0x3126 525#define WM8995_WRITE_SEQUENCER_295 0x3127 526#define WM8995_WRITE_SEQUENCER_296 0x3128 527#define WM8995_WRITE_SEQUENCER_297 0x3129 528#define WM8995_WRITE_SEQUENCER_298 0x312A 529#define WM8995_WRITE_SEQUENCER_299 0x312B 530#define WM8995_WRITE_SEQUENCER_300 0x312C 531#define WM8995_WRITE_SEQUENCER_301 0x312D 532#define WM8995_WRITE_SEQUENCER_302 0x312E 533#define WM8995_WRITE_SEQUENCER_303 0x312F 534#define WM8995_WRITE_SEQUENCER_304 0x3130 535#define WM8995_WRITE_SEQUENCER_305 0x3131 536#define WM8995_WRITE_SEQUENCER_306 0x3132 537#define WM8995_WRITE_SEQUENCER_307 0x3133 538#define WM8995_WRITE_SEQUENCER_308 0x3134 539#define WM8995_WRITE_SEQUENCER_309 0x3135 540#define WM8995_WRITE_SEQUENCER_310 0x3136 541#define WM8995_WRITE_SEQUENCER_311 0x3137 542#define WM8995_WRITE_SEQUENCER_312 0x3138 543#define WM8995_WRITE_SEQUENCER_313 0x3139 544#define WM8995_WRITE_SEQUENCER_314 0x313A 545#define WM8995_WRITE_SEQUENCER_315 0x313B 546#define WM8995_WRITE_SEQUENCER_316 0x313C 547#define WM8995_WRITE_SEQUENCER_317 0x313D 548#define WM8995_WRITE_SEQUENCER_318 0x313E 549#define WM8995_WRITE_SEQUENCER_319 0x313F 550#define WM8995_WRITE_SEQUENCER_320 0x3140 551#define WM8995_WRITE_SEQUENCER_321 0x3141 552#define WM8995_WRITE_SEQUENCER_322 0x3142 553#define WM8995_WRITE_SEQUENCER_323 0x3143 554#define WM8995_WRITE_SEQUENCER_324 0x3144 555#define WM8995_WRITE_SEQUENCER_325 0x3145 556#define WM8995_WRITE_SEQUENCER_326 0x3146 557#define WM8995_WRITE_SEQUENCER_327 0x3147 558#define WM8995_WRITE_SEQUENCER_328 0x3148 559#define WM8995_WRITE_SEQUENCER_329 0x3149 560#define WM8995_WRITE_SEQUENCER_330 0x314A 561#define WM8995_WRITE_SEQUENCER_331 0x314B 562#define WM8995_WRITE_SEQUENCER_332 0x314C 563#define WM8995_WRITE_SEQUENCER_333 0x314D 564#define WM8995_WRITE_SEQUENCER_334 0x314E 565#define WM8995_WRITE_SEQUENCER_335 0x314F 566#define WM8995_WRITE_SEQUENCER_336 0x3150 567#define WM8995_WRITE_SEQUENCER_337 0x3151 568#define WM8995_WRITE_SEQUENCER_338 0x3152 569#define WM8995_WRITE_SEQUENCER_339 0x3153 570#define WM8995_WRITE_SEQUENCER_340 0x3154 571#define WM8995_WRITE_SEQUENCER_341 0x3155 572#define WM8995_WRITE_SEQUENCER_342 0x3156 573#define WM8995_WRITE_SEQUENCER_343 0x3157 574#define WM8995_WRITE_SEQUENCER_344 0x3158 575#define WM8995_WRITE_SEQUENCER_345 0x3159 576#define WM8995_WRITE_SEQUENCER_346 0x315A 577#define WM8995_WRITE_SEQUENCER_347 0x315B 578#define WM8995_WRITE_SEQUENCER_348 0x315C 579#define WM8995_WRITE_SEQUENCER_349 0x315D 580#define WM8995_WRITE_SEQUENCER_350 0x315E 581#define WM8995_WRITE_SEQUENCER_351 0x315F 582#define WM8995_WRITE_SEQUENCER_352 0x3160 583#define WM8995_WRITE_SEQUENCER_353 0x3161 584#define WM8995_WRITE_SEQUENCER_354 0x3162 585#define WM8995_WRITE_SEQUENCER_355 0x3163 586#define WM8995_WRITE_SEQUENCER_356 0x3164 587#define WM8995_WRITE_SEQUENCER_357 0x3165 588#define WM8995_WRITE_SEQUENCER_358 0x3166 589#define WM8995_WRITE_SEQUENCER_359 0x3167 590#define WM8995_WRITE_SEQUENCER_360 0x3168 591#define WM8995_WRITE_SEQUENCER_361 0x3169 592#define WM8995_WRITE_SEQUENCER_362 0x316A 593#define WM8995_WRITE_SEQUENCER_363 0x316B 594#define WM8995_WRITE_SEQUENCER_364 0x316C 595#define WM8995_WRITE_SEQUENCER_365 0x316D 596#define WM8995_WRITE_SEQUENCER_366 0x316E 597#define WM8995_WRITE_SEQUENCER_367 0x316F 598#define WM8995_WRITE_SEQUENCER_368 0x3170 599#define WM8995_WRITE_SEQUENCER_369 0x3171 600#define WM8995_WRITE_SEQUENCER_370 0x3172 601#define WM8995_WRITE_SEQUENCER_371 0x3173 602#define WM8995_WRITE_SEQUENCER_372 0x3174 603#define WM8995_WRITE_SEQUENCER_373 0x3175 604#define WM8995_WRITE_SEQUENCER_374 0x3176 605#define WM8995_WRITE_SEQUENCER_375 0x3177 606#define WM8995_WRITE_SEQUENCER_376 0x3178 607#define WM8995_WRITE_SEQUENCER_377 0x3179 608#define WM8995_WRITE_SEQUENCER_378 0x317A 609#define WM8995_WRITE_SEQUENCER_379 0x317B 610#define WM8995_WRITE_SEQUENCER_380 0x317C 611#define WM8995_WRITE_SEQUENCER_381 0x317D 612#define WM8995_WRITE_SEQUENCER_382 0x317E 613#define WM8995_WRITE_SEQUENCER_383 0x317F 614#define WM8995_WRITE_SEQUENCER_384 0x3180 615#define WM8995_WRITE_SEQUENCER_385 0x3181 616#define WM8995_WRITE_SEQUENCER_386 0x3182 617#define WM8995_WRITE_SEQUENCER_387 0x3183 618#define WM8995_WRITE_SEQUENCER_388 0x3184 619#define WM8995_WRITE_SEQUENCER_389 0x3185 620#define WM8995_WRITE_SEQUENCER_390 0x3186 621#define WM8995_WRITE_SEQUENCER_391 0x3187 622#define WM8995_WRITE_SEQUENCER_392 0x3188 623#define WM8995_WRITE_SEQUENCER_393 0x3189 624#define WM8995_WRITE_SEQUENCER_394 0x318A 625#define WM8995_WRITE_SEQUENCER_395 0x318B 626#define WM8995_WRITE_SEQUENCER_396 0x318C 627#define WM8995_WRITE_SEQUENCER_397 0x318D 628#define WM8995_WRITE_SEQUENCER_398 0x318E 629#define WM8995_WRITE_SEQUENCER_399 0x318F 630#define WM8995_WRITE_SEQUENCER_400 0x3190 631#define WM8995_WRITE_SEQUENCER_401 0x3191 632#define WM8995_WRITE_SEQUENCER_402 0x3192 633#define WM8995_WRITE_SEQUENCER_403 0x3193 634#define WM8995_WRITE_SEQUENCER_404 0x3194 635#define WM8995_WRITE_SEQUENCER_405 0x3195 636#define WM8995_WRITE_SEQUENCER_406 0x3196 637#define WM8995_WRITE_SEQUENCER_407 0x3197 638#define WM8995_WRITE_SEQUENCER_408 0x3198 639#define WM8995_WRITE_SEQUENCER_409 0x3199 640#define WM8995_WRITE_SEQUENCER_410 0x319A 641#define WM8995_WRITE_SEQUENCER_411 0x319B 642#define WM8995_WRITE_SEQUENCER_412 0x319C 643#define WM8995_WRITE_SEQUENCER_413 0x319D 644#define WM8995_WRITE_SEQUENCER_414 0x319E 645#define WM8995_WRITE_SEQUENCER_415 0x319F 646#define WM8995_WRITE_SEQUENCER_416 0x31A0 647#define WM8995_WRITE_SEQUENCER_417 0x31A1 648#define WM8995_WRITE_SEQUENCER_418 0x31A2 649#define WM8995_WRITE_SEQUENCER_419 0x31A3 650#define WM8995_WRITE_SEQUENCER_420 0x31A4 651#define WM8995_WRITE_SEQUENCER_421 0x31A5 652#define WM8995_WRITE_SEQUENCER_422 0x31A6 653#define WM8995_WRITE_SEQUENCER_423 0x31A7 654#define WM8995_WRITE_SEQUENCER_424 0x31A8 655#define WM8995_WRITE_SEQUENCER_425 0x31A9 656#define WM8995_WRITE_SEQUENCER_426 0x31AA 657#define WM8995_WRITE_SEQUENCER_427 0x31AB 658#define WM8995_WRITE_SEQUENCER_428 0x31AC 659#define WM8995_WRITE_SEQUENCER_429 0x31AD 660#define WM8995_WRITE_SEQUENCER_430 0x31AE 661#define WM8995_WRITE_SEQUENCER_431 0x31AF 662#define WM8995_WRITE_SEQUENCER_432 0x31B0 663#define WM8995_WRITE_SEQUENCER_433 0x31B1 664#define WM8995_WRITE_SEQUENCER_434 0x31B2 665#define WM8995_WRITE_SEQUENCER_435 0x31B3 666#define WM8995_WRITE_SEQUENCER_436 0x31B4 667#define WM8995_WRITE_SEQUENCER_437 0x31B5 668#define WM8995_WRITE_SEQUENCER_438 0x31B6 669#define WM8995_WRITE_SEQUENCER_439 0x31B7 670#define WM8995_WRITE_SEQUENCER_440 0x31B8 671#define WM8995_WRITE_SEQUENCER_441 0x31B9 672#define WM8995_WRITE_SEQUENCER_442 0x31BA 673#define WM8995_WRITE_SEQUENCER_443 0x31BB 674#define WM8995_WRITE_SEQUENCER_444 0x31BC 675#define WM8995_WRITE_SEQUENCER_445 0x31BD 676#define WM8995_WRITE_SEQUENCER_446 0x31BE 677#define WM8995_WRITE_SEQUENCER_447 0x31BF 678#define WM8995_WRITE_SEQUENCER_448 0x31C0 679#define WM8995_WRITE_SEQUENCER_449 0x31C1 680#define WM8995_WRITE_SEQUENCER_450 0x31C2 681#define WM8995_WRITE_SEQUENCER_451 0x31C3 682#define WM8995_WRITE_SEQUENCER_452 0x31C4 683#define WM8995_WRITE_SEQUENCER_453 0x31C5 684#define WM8995_WRITE_SEQUENCER_454 0x31C6 685#define WM8995_WRITE_SEQUENCER_455 0x31C7 686#define WM8995_WRITE_SEQUENCER_456 0x31C8 687#define WM8995_WRITE_SEQUENCER_457 0x31C9 688#define WM8995_WRITE_SEQUENCER_458 0x31CA 689#define WM8995_WRITE_SEQUENCER_459 0x31CB 690#define WM8995_WRITE_SEQUENCER_460 0x31CC 691#define WM8995_WRITE_SEQUENCER_461 0x31CD 692#define WM8995_WRITE_SEQUENCER_462 0x31CE 693#define WM8995_WRITE_SEQUENCER_463 0x31CF 694#define WM8995_WRITE_SEQUENCER_464 0x31D0 695#define WM8995_WRITE_SEQUENCER_465 0x31D1 696#define WM8995_WRITE_SEQUENCER_466 0x31D2 697#define WM8995_WRITE_SEQUENCER_467 0x31D3 698#define WM8995_WRITE_SEQUENCER_468 0x31D4 699#define WM8995_WRITE_SEQUENCER_469 0x31D5 700#define WM8995_WRITE_SEQUENCER_470 0x31D6 701#define WM8995_WRITE_SEQUENCER_471 0x31D7 702#define WM8995_WRITE_SEQUENCER_472 0x31D8 703#define WM8995_WRITE_SEQUENCER_473 0x31D9 704#define WM8995_WRITE_SEQUENCER_474 0x31DA 705#define WM8995_WRITE_SEQUENCER_475 0x31DB 706#define WM8995_WRITE_SEQUENCER_476 0x31DC 707#define WM8995_WRITE_SEQUENCER_477 0x31DD 708#define WM8995_WRITE_SEQUENCER_478 0x31DE 709#define WM8995_WRITE_SEQUENCER_479 0x31DF 710#define WM8995_WRITE_SEQUENCER_480 0x31E0 711#define WM8995_WRITE_SEQUENCER_481 0x31E1 712#define WM8995_WRITE_SEQUENCER_482 0x31E2 713#define WM8995_WRITE_SEQUENCER_483 0x31E3 714#define WM8995_WRITE_SEQUENCER_484 0x31E4 715#define WM8995_WRITE_SEQUENCER_485 0x31E5 716#define WM8995_WRITE_SEQUENCER_486 0x31E6 717#define WM8995_WRITE_SEQUENCER_487 0x31E7 718#define WM8995_WRITE_SEQUENCER_488 0x31E8 719#define WM8995_WRITE_SEQUENCER_489 0x31E9 720#define WM8995_WRITE_SEQUENCER_490 0x31EA 721#define WM8995_WRITE_SEQUENCER_491 0x31EB 722#define WM8995_WRITE_SEQUENCER_492 0x31EC 723#define WM8995_WRITE_SEQUENCER_493 0x31ED 724#define WM8995_WRITE_SEQUENCER_494 0x31EE 725#define WM8995_WRITE_SEQUENCER_495 0x31EF 726#define WM8995_WRITE_SEQUENCER_496 0x31F0 727#define WM8995_WRITE_SEQUENCER_497 0x31F1 728#define WM8995_WRITE_SEQUENCER_498 0x31F2 729#define WM8995_WRITE_SEQUENCER_499 0x31F3 730#define WM8995_WRITE_SEQUENCER_500 0x31F4 731#define WM8995_WRITE_SEQUENCER_501 0x31F5 732#define WM8995_WRITE_SEQUENCER_502 0x31F6 733#define WM8995_WRITE_SEQUENCER_503 0x31F7 734#define WM8995_WRITE_SEQUENCER_504 0x31F8 735#define WM8995_WRITE_SEQUENCER_505 0x31F9 736#define WM8995_WRITE_SEQUENCER_506 0x31FA 737#define WM8995_WRITE_SEQUENCER_507 0x31FB 738#define WM8995_WRITE_SEQUENCER_508 0x31FC 739#define WM8995_WRITE_SEQUENCER_509 0x31FD 740#define WM8995_WRITE_SEQUENCER_510 0x31FE 741#define WM8995_WRITE_SEQUENCER_511 0x31FF 742 743#define WM8995_REGISTER_COUNT 725 744#define WM8995_MAX_REGISTER 0x31FF 745 746#define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER 747 748/* 749 * Field Definitions. 750 */ 751 752/* 753 * R0 (0x00) - Software Reset 754 */ 755#define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 756#define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 757#define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 758 759/* 760 * R1 (0x01) - Power Management (1) 761 */ 762#define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */ 763#define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ 764#define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ 765#define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 766#define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */ 767#define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ 768#define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ 769#define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 770#define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ 771#define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ 772#define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ 773#define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ 774#define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ 775#define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ 776#define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ 777#define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ 778#define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ 779#define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ 780#define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ 781#define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 782#define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ 783#define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ 784#define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ 785#define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 786#define WM8995_BG_ENA 0x0001 /* BG_ENA */ 787#define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */ 788#define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */ 789#define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */ 790 791/* 792 * R2 (0x02) - Power Management (2) 793 */ 794#define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 795#define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 796#define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 797#define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 798#define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */ 799#define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */ 800#define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */ 801#define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 802#define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */ 803#define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ 804#define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ 805#define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 806#define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */ 807#define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ 808#define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ 809#define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 810 811/* 812 * R3 (0x03) - Power Management (3) 813 */ 814#define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ 815#define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ 816#define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ 817#define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ 818#define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ 819#define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ 820#define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ 821#define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ 822#define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ 823#define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ 824#define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ 825#define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ 826#define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ 827#define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ 828#define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ 829#define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ 830#define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ 831#define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ 832#define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ 833#define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ 834#define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ 835#define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ 836#define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ 837#define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ 838#define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */ 839#define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */ 840#define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */ 841#define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */ 842#define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */ 843#define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */ 844#define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */ 845#define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */ 846#define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 847#define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 848#define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 849#define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 850#define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 851#define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 852#define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 853#define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 854#define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 855#define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 856#define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 857#define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 858#define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 859#define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 860#define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 861#define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 862#define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */ 863#define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 864#define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 865#define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 866#define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */ 867#define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 868#define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 869#define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 870 871/* 872 * R4 (0x04) - Power Management (4) 873 */ 874#define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ 875#define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ 876#define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ 877#define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ 878#define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ 879#define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ 880#define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ 881#define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ 882#define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ 883#define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ 884#define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ 885#define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ 886#define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ 887#define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ 888#define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ 889#define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ 890#define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ 891#define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ 892#define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ 893#define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ 894#define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ 895#define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ 896#define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ 897#define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ 898#define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 899#define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 900#define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 901#define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 902#define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 903#define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 904#define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 905#define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 906#define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 907#define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 908#define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 909#define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 910#define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 911#define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 912#define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 913#define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 914 915/* 916 * R5 (0x05) - Power Management (5) 917 */ 918#define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */ 919#define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */ 920#define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */ 921#define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */ 922#define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */ 923#define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */ 924#define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */ 925#define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 926#define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 927#define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 928#define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ 929#define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ 930#define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ 931#define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ 932#define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ 933#define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ 934#define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ 935#define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ 936#define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ 937#define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ 938#define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ 939#define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ 940#define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ 941#define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ 942#define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ 943 944/* 945 * R16 (0x10) - Left Line Input 1 Volume 946 */ 947#define WM8995_IN1_VU 0x0080 /* IN1_VU */ 948#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ 949#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ 950#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ 951#define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */ 952#define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ 953#define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ 954#define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 955#define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 956#define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 957#define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 958 959/* 960 * R17 (0x11) - Right Line Input 1 Volume 961 */ 962#define WM8995_IN1_VU 0x0080 /* IN1_VU */ 963#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ 964#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ 965#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ 966#define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */ 967#define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ 968#define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ 969#define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 970#define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 971#define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 972#define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 973 974/* 975 * R18 (0x12) - Left Line Input Control 976 */ 977#define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */ 978#define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */ 979#define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */ 980#define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */ 981#define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */ 982#define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */ 983#define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */ 984#define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */ 985#define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */ 986 987/* 988 * R24 (0x18) - DAC1 Left Volume 989 */ 990#define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 991#define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 992#define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 993#define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 994#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ 995#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 996#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ 997#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ 998#define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 999#define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 1000#define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 1001 1002/* 1003 * R25 (0x19) - DAC1 Right Volume 1004 */ 1005#define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 1006#define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 1007#define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 1008#define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 1009#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ 1010#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1011#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1012#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1013#define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 1014#define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 1015#define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 1016 1017/* 1018 * R26 (0x1A) - DAC2 Left Volume 1019 */ 1020#define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 1021#define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 1022#define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 1023#define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 1024#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ 1025#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1026#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1027#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1028#define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 1029#define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 1030#define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 1031 1032/* 1033 * R27 (0x1B) - DAC2 Right Volume 1034 */ 1035#define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 1036#define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 1037#define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 1038#define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 1039#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ 1040#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1041#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1042#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1043#define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 1044#define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 1045#define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 1046 1047/* 1048 * R28 (0x1C) - Output Volume ZC (1) 1049 */ 1050#define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */ 1051#define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */ 1052#define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */ 1053#define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ 1054#define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */ 1055#define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */ 1056#define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */ 1057#define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ 1058#define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */ 1059#define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */ 1060#define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */ 1061#define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1062#define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */ 1063#define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */ 1064#define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */ 1065#define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1066 1067/* 1068 * R32 (0x20) - MICBIAS (1) 1069 */ 1070#define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */ 1071#define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */ 1072#define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */ 1073#define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 1074#define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */ 1075#define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */ 1076#define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */ 1077#define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */ 1078#define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ 1079#define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ 1080#define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1081 1082/* 1083 * R33 (0x21) - MICBIAS (2) 1084 */ 1085#define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */ 1086#define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */ 1087#define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */ 1088#define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 1089#define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */ 1090#define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */ 1091#define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */ 1092#define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */ 1093#define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ 1094#define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ 1095#define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1096 1097/* 1098 * R40 (0x28) - LDO 1 1099 */ 1100#define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */ 1101#define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ 1102#define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ 1103#define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ 1104#define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ 1105#define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ 1106#define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ 1107#define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1108#define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1109#define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1110#define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1111 1112/* 1113 * R41 (0x29) - LDO 2 1114 */ 1115#define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */ 1116#define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ 1117#define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ 1118#define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ 1119#define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ 1120#define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ 1121#define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ 1122#define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1123#define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1124#define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1125#define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1126 1127/* 1128 * R48 (0x30) - Accessory Detect Mode1 1129 */ 1130#define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ 1131#define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ 1132#define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ 1133 1134/* 1135 * R49 (0x31) - Accessory Detect Mode2 1136 */ 1137#define WM8995_VID_ENA 0x0001 /* VID_ENA */ 1138#define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */ 1139#define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */ 1140#define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */ 1141 1142/* 1143 * R52 (0x34) - Headphone Detect1 1144 */ 1145#define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */ 1146#define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */ 1147#define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */ 1148#define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */ 1149#define WM8995_HP_POLL 0x0001 /* HP_POLL */ 1150#define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */ 1151#define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */ 1152#define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */ 1153 1154/* 1155 * R53 (0x35) - Headphone Detect2 1156 */ 1157#define WM8995_HP_DONE 0x0080 /* HP_DONE */ 1158#define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */ 1159#define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */ 1160#define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */ 1161#define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1162#define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1163#define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1164 1165/* 1166 * R56 (0x38) - Mic Detect (1) 1167 */ 1168#define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */ 1169#define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */ 1170#define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */ 1171#define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */ 1172#define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */ 1173#define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */ 1174#define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 1175#define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 1176#define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 1177#define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 1178#define WM8995_MICD_ENA 0x0001 /* MICD_ENA */ 1179#define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 1180#define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */ 1181#define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1182 1183/* 1184 * R57 (0x39) - Mic Detect (2) 1185 */ 1186#define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */ 1187#define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */ 1188#define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */ 1189#define WM8995_MICD_VALID 0x0002 /* MICD_VALID */ 1190#define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 1191#define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */ 1192#define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */ 1193#define WM8995_MICD_STS 0x0001 /* MICD_STS */ 1194#define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */ 1195#define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */ 1196#define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */ 1197 1198/* 1199 * R64 (0x40) - Charge Pump (1) 1200 */ 1201#define WM8995_CP_ENA 0x8000 /* CP_ENA */ 1202#define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */ 1203#define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */ 1204#define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */ 1205 1206/* 1207 * R69 (0x45) - Class W (1) 1208 */ 1209#define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 1210#define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ 1211#define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ 1212#define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 1213#define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 1214#define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 1215#define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 1216 1217/* 1218 * R80 (0x50) - DC Servo (1) 1219 */ 1220#define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 1221#define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 1222#define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 1223#define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 1224#define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 1225#define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 1226#define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 1227#define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 1228#define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 1229#define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 1230#define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 1231#define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 1232#define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 1233#define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 1234#define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 1235#define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 1236 1237/* 1238 * R81 (0x51) - DC Servo (2) 1239 */ 1240#define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 1241#define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 1242#define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 1243#define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 1244#define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 1245#define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 1246#define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 1247#define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 1248#define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 1249#define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 1250#define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 1251#define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 1252#define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 1253#define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 1254#define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 1255#define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 1256#define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 1257#define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 1258#define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 1259#define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 1260#define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 1261#define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 1262#define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 1263#define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 1264#define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 1265#define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 1266#define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 1267#define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 1268#define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 1269#define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 1270#define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 1271#define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 1272#define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 1273#define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 1274#define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 1275#define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 1276#define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 1277#define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 1278#define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 1279#define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 1280#define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 1281#define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 1282#define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 1283#define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 1284#define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 1285#define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 1286#define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 1287#define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 1288#define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1289#define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1290#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 1291#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 1292#define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1293#define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1294#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 1295#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 1296#define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1297#define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1298#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 1299#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 1300#define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1301#define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1302#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 1303#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 1304 1305/* 1306 * R82 (0x52) - DC Servo (3) 1307 */ 1308#define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1309#define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1310#define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1311#define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 1312#define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1313#define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1314 1315/* 1316 * R84 (0x54) - DC Servo (5) 1317 */ 1318#define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ 1319#define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ 1320#define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ 1321#define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 1322#define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 1323#define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 1324 1325/* 1326 * R85 (0x55) - DC Servo (6) 1327 */ 1328#define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1329#define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1330#define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1331#define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 1332#define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1333#define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1334 1335/* 1336 * R86 (0x56) - DC Servo (7) 1337 */ 1338#define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1339#define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1340#define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1341#define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 1342#define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1343#define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1344 1345/* 1346 * R87 (0x57) - DC Servo Readback 0 1347 */ 1348#define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 1349#define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 1350#define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 1351#define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1352#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1353#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1354#define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 1355#define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 1356#define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 1357 1358/* 1359 * R96 (0x60) - Analogue HP (1) 1360 */ 1361#define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 1362#define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 1363#define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 1364#define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 1365#define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 1366#define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 1367#define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 1368#define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 1369#define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 1370#define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 1371#define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 1372#define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 1373#define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 1374#define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 1375#define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 1376#define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 1377#define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 1378#define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 1379#define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 1380#define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 1381#define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 1382#define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 1383#define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 1384#define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 1385 1386/* 1387 * R97 (0x61) - Analogue HP (2) 1388 */ 1389#define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ 1390#define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ 1391#define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ 1392#define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ 1393#define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ 1394#define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ 1395#define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ 1396#define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ 1397#define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ 1398#define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ 1399#define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ 1400#define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ 1401#define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ 1402#define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ 1403#define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ 1404#define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ 1405#define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ 1406#define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ 1407#define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ 1408#define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ 1409#define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ 1410#define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ 1411#define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ 1412#define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ 1413 1414/* 1415 * R256 (0x100) - Chip Revision 1416 */ 1417#define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 1418#define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 1419#define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 1420 1421/* 1422 * R257 (0x101) - Control Interface (1) 1423 */ 1424#define WM8995_REG_SYNC 0x8000 /* REG_SYNC */ 1425#define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */ 1426#define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */ 1427#define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */ 1428#define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 1429#define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 1430#define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 1431#define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 1432#define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 1433#define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 1434#define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 1435#define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 1436#define WM8995_SPI_CFG 0x0010 /* SPI_CFG */ 1437#define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 1438#define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */ 1439#define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */ 1440#define WM8995_AUTO_INC 0x0004 /* AUTO_INC */ 1441#define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 1442#define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */ 1443#define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */ 1444 1445/* 1446 * R258 (0x102) - Control Interface (2) 1447 */ 1448#define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */ 1449#define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */ 1450#define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */ 1451#define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */ 1452 1453/* 1454 * R272 (0x110) - Write Sequencer Ctrl (1) 1455 */ 1456#define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 1457#define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 1458#define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 1459#define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1460#define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1461#define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1462#define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1463#define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1464#define WM8995_WSEQ_START 0x0100 /* WSEQ_START */ 1465#define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1466#define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1467#define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1468#define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 1469#define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 1470#define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 1471 1472/* 1473 * R273 (0x111) - Write Sequencer Ctrl (2) 1474 */ 1475#define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 1476#define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 1477#define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 1478#define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1479#define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 1480#define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 1481#define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 1482 1483/* 1484 * R512 (0x200) - AIF1 Clocking (1) 1485 */ 1486#define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ 1487#define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ 1488#define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ 1489#define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ 1490#define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ 1491#define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ 1492#define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ 1493#define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ 1494#define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ 1495#define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ 1496#define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ 1497#define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ 1498#define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ 1499#define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ 1500#define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ 1501 1502/* 1503 * R513 (0x201) - AIF1 Clocking (2) 1504 */ 1505#define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ 1506#define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ 1507#define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ 1508#define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ 1509#define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ 1510#define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ 1511 1512/* 1513 * R516 (0x204) - AIF2 Clocking (1) 1514 */ 1515#define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ 1516#define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ 1517#define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ 1518#define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ 1519#define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ 1520#define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ 1521#define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ 1522#define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ 1523#define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ 1524#define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ 1525#define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ 1526#define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ 1527#define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ 1528#define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ 1529#define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ 1530 1531/* 1532 * R517 (0x205) - AIF2 Clocking (2) 1533 */ 1534#define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ 1535#define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ 1536#define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ 1537#define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ 1538#define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ 1539#define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ 1540 1541/* 1542 * R520 (0x208) - Clocking (1) 1543 */ 1544#define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */ 1545#define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ 1546#define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ 1547#define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ 1548#define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 1549#define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 1550#define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 1551#define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 1552#define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ 1553#define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ 1554#define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ 1555#define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ 1556#define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ 1557#define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ 1558#define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ 1559#define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ 1560#define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 1561#define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 1562#define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 1563#define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 1564#define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ 1565#define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ 1566#define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ 1567#define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 1568 1569/* 1570 * R521 (0x209) - Clocking (2) 1571 */ 1572#define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 1573#define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 1574#define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 1575#define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ 1576#define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ 1577#define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ 1578#define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 1579#define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 1580#define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 1581 1582/* 1583 * R528 (0x210) - AIF1 Rate 1584 */ 1585#define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ 1586#define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ 1587#define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ 1588#define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ 1589#define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ 1590#define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ 1591 1592/* 1593 * R529 (0x211) - AIF2 Rate 1594 */ 1595#define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ 1596#define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ 1597#define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ 1598#define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ 1599#define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ 1600#define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ 1601 1602/* 1603 * R530 (0x212) - Rate Status 1604 */ 1605#define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ 1606#define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ 1607#define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ 1608 1609/* 1610 * R544 (0x220) - FLL1 Control (1) 1611 */ 1612#define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ 1613#define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ 1614#define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ 1615#define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ 1616#define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */ 1617#define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1618#define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1619#define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1620 1621/* 1622 * R545 (0x221) - FLL1 Control (2) 1623 */ 1624#define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 1625#define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 1626#define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 1627#define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ 1628#define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ 1629#define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ 1630#define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 1631#define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 1632#define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 1633 1634/* 1635 * R546 (0x222) - FLL1 Control (3) 1636 */ 1637#define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ 1638#define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ 1639#define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ 1640 1641/* 1642 * R547 (0x223) - FLL1 Control (4) 1643 */ 1644#define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ 1645#define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ 1646#define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ 1647#define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ 1648#define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ 1649#define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ 1650 1651/* 1652 * R548 (0x224) - FLL1 Control (5) 1653 */ 1654#define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 1655#define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 1656#define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 1657#define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ 1658#define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ 1659#define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ 1660#define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ 1661#define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ 1662#define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ 1663#define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ 1664#define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ 1665#define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ 1666#define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 1667 1668/* 1669 * R576 (0x240) - FLL2 Control (1) 1670 */ 1671#define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ 1672#define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ 1673#define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ 1674#define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ 1675#define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */ 1676#define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1677#define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1678#define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1679 1680/* 1681 * R577 (0x241) - FLL2 Control (2) 1682 */ 1683#define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 1684#define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 1685#define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 1686#define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ 1687#define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ 1688#define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ 1689#define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 1690#define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 1691#define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 1692 1693/* 1694 * R578 (0x242) - FLL2 Control (3) 1695 */ 1696#define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ 1697#define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ 1698#define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ 1699 1700/* 1701 * R579 (0x243) - FLL2 Control (4) 1702 */ 1703#define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ 1704#define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ 1705#define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ 1706#define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ 1707#define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ 1708#define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ 1709 1710/* 1711 * R580 (0x244) - FLL2 Control (5) 1712 */ 1713#define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 1714#define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 1715#define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 1716#define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ 1717#define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ 1718#define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ 1719#define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ 1720#define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ 1721#define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ 1722#define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ 1723#define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ 1724#define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ 1725#define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 1726 1727/* 1728 * R768 (0x300) - AIF1 Control (1) 1729 */ 1730#define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 1731#define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ 1732#define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ 1733#define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ 1734#define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ 1735#define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ 1736#define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ 1737#define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ 1738#define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ 1739#define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ 1740#define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ 1741#define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ 1742#define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ 1743#define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ 1744#define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ 1745#define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 1746#define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ 1747#define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ 1748#define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ 1749#define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 1750#define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ 1751#define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ 1752#define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ 1753#define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ 1754#define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ 1755#define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ 1756 1757/* 1758 * R769 (0x301) - AIF1 Control (2) 1759 */ 1760#define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ 1761#define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ 1762#define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ 1763#define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ 1764#define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ 1765#define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ 1766#define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ 1767#define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ 1768#define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ 1769#define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ 1770#define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ 1771#define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ 1772#define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ 1773#define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ 1774#define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ 1775#define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ 1776#define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ 1777#define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ 1778#define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ 1779#define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ 1780#define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ 1781#define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ 1782#define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ 1783#define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ 1784#define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ 1785#define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ 1786#define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ 1787#define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ 1788#define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ 1789#define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ 1790#define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ 1791 1792/* 1793 * R770 (0x302) - AIF1 Master/Slave 1794 */ 1795#define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */ 1796#define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ 1797#define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ 1798#define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 1799#define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */ 1800#define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ 1801#define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ 1802#define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ 1803#define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ 1804#define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ 1805#define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ 1806#define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ 1807#define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ 1808#define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ 1809#define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ 1810#define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ 1811 1812/* 1813 * R771 (0x303) - AIF1 BCLK 1814 */ 1815#define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */ 1816#define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */ 1817#define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */ 1818 1819/* 1820 * R772 (0x304) - AIF1ADC LRCLK 1821 */ 1822#define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 1823#define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 1824#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 1825#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ 1826#define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ 1827#define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ 1828#define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ 1829 1830/* 1831 * R773 (0x305) - AIF1DAC LRCLK 1832 */ 1833#define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 1834#define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 1835#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 1836#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ 1837#define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ 1838#define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ 1839#define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ 1840 1841/* 1842 * R774 (0x306) - AIF1DAC Data 1843 */ 1844#define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ 1845#define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ 1846#define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ 1847#define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ 1848#define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ 1849#define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ 1850#define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ 1851#define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ 1852 1853/* 1854 * R775 (0x307) - AIF1ADC Data 1855 */ 1856#define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ 1857#define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ 1858#define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ 1859#define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ 1860#define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ 1861#define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ 1862#define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ 1863#define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ 1864 1865/* 1866 * R784 (0x310) - AIF2 Control (1) 1867 */ 1868#define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ 1869#define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ 1870#define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ 1871#define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ 1872#define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ 1873#define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ 1874#define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ 1875#define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ 1876#define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ 1877#define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ 1878#define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ 1879#define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ 1880#define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ 1881#define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ 1882#define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ 1883#define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ 1884#define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ 1885#define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ 1886#define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ 1887#define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 1888#define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ 1889#define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ 1890#define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ 1891#define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ 1892#define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ 1893#define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ 1894#define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ 1895#define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ 1896#define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ 1897#define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ 1898 1899/* 1900 * R785 (0x311) - AIF2 Control (2) 1901 */ 1902#define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ 1903#define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ 1904#define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ 1905#define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ 1906#define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ 1907#define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ 1908#define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ 1909#define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ 1910#define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ 1911#define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ 1912#define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ 1913#define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ 1914#define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ 1915#define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ 1916#define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ 1917#define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ 1918#define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ 1919#define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ 1920#define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ 1921#define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ 1922#define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ 1923#define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ 1924#define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ 1925#define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ 1926#define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ 1927#define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ 1928#define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ 1929#define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ 1930#define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ 1931#define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ 1932#define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ 1933#define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ 1934#define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ 1935#define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ 1936#define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ 1937#define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ 1938#define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ 1939#define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ 1940#define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ 1941 1942/* 1943 * R786 (0x312) - AIF2 Master/Slave 1944 */ 1945#define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */ 1946#define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ 1947#define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ 1948#define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 1949#define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */ 1950#define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ 1951#define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ 1952#define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ 1953#define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ 1954#define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ 1955#define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ 1956#define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ 1957#define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ 1958#define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ 1959#define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ 1960#define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ 1961 1962/* 1963 * R787 (0x313) - AIF2 BCLK 1964 */ 1965#define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */ 1966#define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */ 1967#define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */ 1968 1969/* 1970 * R788 (0x314) - AIF2ADC LRCLK 1971 */ 1972#define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ 1973#define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ 1974#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ 1975#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ 1976#define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ 1977#define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ 1978#define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ 1979 1980/* 1981 * R789 (0x315) - AIF2DAC LRCLK 1982 */ 1983#define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ 1984#define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ 1985#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ 1986#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ 1987#define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ 1988#define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ 1989#define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ 1990 1991/* 1992 * R790 (0x316) - AIF2DAC Data 1993 */ 1994#define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ 1995#define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ 1996#define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ 1997#define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ 1998#define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ 1999#define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ 2000#define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ 2001#define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ 2002 2003/* 2004 * R791 (0x317) - AIF2ADC Data 2005 */ 2006#define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ 2007#define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ 2008#define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ 2009#define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ 2010#define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ 2011#define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ 2012#define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ 2013#define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 2014 2015/* 2016 * R1024 (0x400) - AIF1 ADC1 Left Volume 2017 */ 2018#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2019#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2020#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2021#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2022#define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ 2023#define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ 2024#define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ 2025 2026/* 2027 * R1025 (0x401) - AIF1 ADC1 Right Volume 2028 */ 2029#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2030#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2031#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2032#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2033#define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ 2034#define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ 2035#define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ 2036 2037/* 2038 * R1026 (0x402) - AIF1 DAC1 Left Volume 2039 */ 2040#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2041#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2042#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2043#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2044#define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ 2045#define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ 2046#define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ 2047 2048/* 2049 * R1027 (0x403) - AIF1 DAC1 Right Volume 2050 */ 2051#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2052#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2053#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2054#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2055#define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ 2056#define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ 2057#define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ 2058 2059/* 2060 * R1028 (0x404) - AIF1 ADC2 Left Volume 2061 */ 2062#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2063#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2064#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2065#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2066#define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ 2067#define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ 2068#define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ 2069 2070/* 2071 * R1029 (0x405) - AIF1 ADC2 Right Volume 2072 */ 2073#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2074#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2075#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2076#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2077#define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ 2078#define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ 2079#define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ 2080 2081/* 2082 * R1030 (0x406) - AIF1 DAC2 Left Volume 2083 */ 2084#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2085#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2086#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2087#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2088#define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ 2089#define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ 2090#define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ 2091 2092/* 2093 * R1031 (0x407) - AIF1 DAC2 Right Volume 2094 */ 2095#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2096#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2097#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2098#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2099#define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ 2100#define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ 2101#define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ 2102 2103/* 2104 * R1040 (0x410) - AIF1 ADC1 Filters 2105 */ 2106#define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ 2107#define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ 2108#define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ 2109#define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ 2110#define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ 2111#define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ 2112#define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ 2113#define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ 2114#define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ 2115#define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ 2116#define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ 2117#define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ 2118#define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */ 2119#define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */ 2120#define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */ 2121#define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */ 2122#define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */ 2123#define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */ 2124#define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */ 2125 2126/* 2127 * R1041 (0x411) - AIF1 ADC2 Filters 2128 */ 2129#define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ 2130#define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ 2131#define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ 2132#define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ 2133#define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ 2134#define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ 2135#define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ 2136#define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ 2137#define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */ 2138#define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */ 2139#define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */ 2140#define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */ 2141#define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */ 2142#define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */ 2143#define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */ 2144 2145/* 2146 * R1056 (0x420) - AIF1 DAC1 Filters (1) 2147 */ 2148#define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ 2149#define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ 2150#define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ 2151#define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ 2152#define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ 2153#define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ 2154#define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ 2155#define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ 2156#define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ 2157#define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ 2158#define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ 2159#define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ 2160#define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2161#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2162#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ 2163#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ 2164#define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ 2165#define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ 2166#define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ 2167 2168/* 2169 * R1057 (0x421) - AIF1 DAC1 Filters (2) 2170 */ 2171#define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ 2172#define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ 2173#define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ 2174#define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ 2175#define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ 2176#define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ 2177#define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ 2178 2179/* 2180 * R1058 (0x422) - AIF1 DAC2 Filters (1) 2181 */ 2182#define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ 2183#define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ 2184#define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ 2185#define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ 2186#define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ 2187#define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ 2188#define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ 2189#define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ 2190#define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ 2191#define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ 2192#define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ 2193#define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ 2194#define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2195#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2196#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ 2197#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ 2198#define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ 2199#define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ 2200#define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ 2201 2202/* 2203 * R1059 (0x423) - AIF1 DAC2 Filters (2) 2204 */ 2205#define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ 2206#define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ 2207#define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ 2208#define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ 2209#define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ 2210#define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ 2211#define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ 2212 2213/* 2214 * R1088 (0x440) - AIF1 DRC1 (1) 2215 */ 2216#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2217#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2218#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2219#define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2220#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2221#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2222#define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ 2223#define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ 2224#define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ 2225#define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ 2226#define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2227#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2228#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ 2229#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ 2230#define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ 2231#define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ 2232#define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ 2233#define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ 2234#define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2235#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2236#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ 2237#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ 2238#define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ 2239#define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ 2240#define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ 2241#define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ 2242#define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ 2243#define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ 2244#define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ 2245#define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ 2246#define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ 2247#define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ 2248#define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ 2249#define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ 2250#define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ 2251#define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ 2252#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ 2253#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ 2254#define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ 2255#define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ 2256#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ 2257#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ 2258 2259/* 2260 * R1089 (0x441) - AIF1 DRC1 (2) 2261 */ 2262#define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ 2263#define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ 2264#define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ 2265#define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ 2266#define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ 2267#define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ 2268#define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ 2269#define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ 2270#define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ 2271#define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ 2272#define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ 2273#define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ 2274 2275/* 2276 * R1090 (0x442) - AIF1 DRC1 (3) 2277 */ 2278#define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2279#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2280#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2281#define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ 2282#define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ 2283#define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ 2284#define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ 2285#define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ 2286#define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ 2287#define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ 2288#define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ 2289#define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ 2290#define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ 2291#define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ 2292#define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ 2293#define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ 2294#define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ 2295#define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ 2296 2297/* 2298 * R1091 (0x443) - AIF1 DRC1 (4) 2299 */ 2300#define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ 2301#define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ 2302#define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ 2303#define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ 2304#define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ 2305#define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ 2306 2307/* 2308 * R1092 (0x444) - AIF1 DRC1 (5) 2309 */ 2310#define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2311#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2312#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2313#define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ 2314#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ 2315#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ 2316 2317/* 2318 * R1104 (0x450) - AIF1 DRC2 (1) 2319 */ 2320#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2321#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2322#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2323#define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2324#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2325#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2326#define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ 2327#define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ 2328#define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ 2329#define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ 2330#define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 2331#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 2332#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ 2333#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ 2334#define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ 2335#define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ 2336#define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ 2337#define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ 2338#define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 2339#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 2340#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ 2341#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ 2342#define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ 2343#define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ 2344#define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ 2345#define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ 2346#define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ 2347#define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ 2348#define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ 2349#define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ 2350#define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ 2351#define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ 2352#define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ 2353#define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ 2354#define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ 2355#define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ 2356#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ 2357#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ 2358#define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ 2359#define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ 2360#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ 2361#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ 2362 2363/* 2364 * R1105 (0x451) - AIF1 DRC2 (2) 2365 */ 2366#define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ 2367#define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ 2368#define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ 2369#define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ 2370#define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ 2371#define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ 2372#define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ 2373#define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ 2374#define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ 2375#define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ 2376#define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ 2377#define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ 2378 2379/* 2380 * R1106 (0x452) - AIF1 DRC2 (3) 2381 */ 2382#define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2383#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2384#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2385#define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ 2386#define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ 2387#define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ 2388#define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ 2389#define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ 2390#define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ 2391#define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ 2392#define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ 2393#define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ 2394#define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ 2395#define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ 2396#define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ 2397#define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ 2398#define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ 2399#define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ 2400 2401/* 2402 * R1107 (0x453) - AIF1 DRC2 (4) 2403 */ 2404#define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ 2405#define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ 2406#define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ 2407#define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ 2408#define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ 2409#define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ 2410 2411/* 2412 * R1108 (0x454) - AIF1 DRC2 (5) 2413 */ 2414#define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2415#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2416#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2417#define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ 2418#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ 2419#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ 2420 2421/* 2422 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) 2423 */ 2424#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2425#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2426#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2427#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2428#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2429#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2430#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2431#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2432#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2433#define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ 2434#define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ 2435#define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ 2436#define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ 2437 2438/* 2439 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) 2440 */ 2441#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2442#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2443#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2444#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2445#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2446#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2447 2448/* 2449 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A 2450 */ 2451#define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ 2452#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ 2453#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ 2454 2455/* 2456 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B 2457 */ 2458#define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ 2459#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ 2460#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ 2461 2462/* 2463 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG 2464 */ 2465#define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2466#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2467#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2468 2469/* 2470 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A 2471 */ 2472#define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ 2473#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ 2474#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ 2475 2476/* 2477 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B 2478 */ 2479#define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ 2480#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ 2481#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ 2482 2483/* 2484 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C 2485 */ 2486#define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ 2487#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ 2488#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ 2489 2490/* 2491 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG 2492 */ 2493#define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ 2494#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 2495#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 2496 2497/* 2498 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A 2499 */ 2500#define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ 2501#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ 2502#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ 2503 2504/* 2505 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B 2506 */ 2507#define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ 2508#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ 2509#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ 2510 2511/* 2512 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C 2513 */ 2514#define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ 2515#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ 2516#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ 2517 2518/* 2519 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG 2520 */ 2521#define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ 2522#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 2523#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 2524 2525/* 2526 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A 2527 */ 2528#define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ 2529#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ 2530#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ 2531 2532/* 2533 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B 2534 */ 2535#define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ 2536#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ 2537#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ 2538 2539/* 2540 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C 2541 */ 2542#define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ 2543#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ 2544#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ 2545 2546/* 2547 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG 2548 */ 2549#define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ 2550#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 2551#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 2552 2553/* 2554 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A 2555 */ 2556#define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ 2557#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ 2558#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ 2559 2560/* 2561 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B 2562 */ 2563#define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ 2564#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ 2565#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ 2566 2567/* 2568 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG 2569 */ 2570#define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ 2571#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 2572#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 2573 2574/* 2575 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) 2576 */ 2577#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 2578#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 2579#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 2580#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 2581#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 2582#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 2583#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 2584#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 2585#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 2586#define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ 2587#define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ 2588#define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ 2589#define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ 2590 2591/* 2592 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) 2593 */ 2594#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 2595#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 2596#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 2597#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 2598#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 2599#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 2600 2601/* 2602 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A 2603 */ 2604#define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ 2605#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ 2606#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ 2607 2608/* 2609 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B 2610 */ 2611#define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ 2612#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ 2613#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ 2614 2615/* 2616 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG 2617 */ 2618#define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ 2619#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 2620#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 2621 2622/* 2623 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A 2624 */ 2625#define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ 2626#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ 2627#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ 2628 2629/* 2630 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B 2631 */ 2632#define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ 2633#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ 2634#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ 2635 2636/* 2637 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C 2638 */ 2639#define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ 2640#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ 2641#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ 2642 2643/* 2644 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG 2645 */ 2646#define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ 2647#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 2648#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 2649 2650/* 2651 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A 2652 */ 2653#define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ 2654#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ 2655#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ 2656 2657/* 2658 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B 2659 */ 2660#define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ 2661#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ 2662#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ 2663 2664/* 2665 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C 2666 */ 2667#define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ 2668#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ 2669#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ 2670 2671/* 2672 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG 2673 */ 2674#define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ 2675#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 2676#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 2677 2678/* 2679 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A 2680 */ 2681#define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ 2682#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ 2683#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ 2684 2685/* 2686 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B 2687 */ 2688#define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ 2689#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ 2690#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ 2691 2692/* 2693 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C 2694 */ 2695#define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ 2696#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ 2697#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ 2698 2699/* 2700 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG 2701 */ 2702#define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ 2703#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 2704#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 2705 2706/* 2707 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A 2708 */ 2709#define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ 2710#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ 2711#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ 2712 2713/* 2714 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B 2715 */ 2716#define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ 2717#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ 2718#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ 2719 2720/* 2721 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG 2722 */ 2723#define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ 2724#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 2725#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 2726 2727/* 2728 * R1280 (0x500) - AIF2 ADC Left Volume 2729 */ 2730#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 2731#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 2732#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 2733#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 2734#define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ 2735#define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ 2736#define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ 2737 2738/* 2739 * R1281 (0x501) - AIF2 ADC Right Volume 2740 */ 2741#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 2742#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 2743#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 2744#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 2745#define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ 2746#define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ 2747#define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ 2748 2749/* 2750 * R1282 (0x502) - AIF2 DAC Left Volume 2751 */ 2752#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 2753#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 2754#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 2755#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 2756#define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ 2757#define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ 2758#define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ 2759 2760/* 2761 * R1283 (0x503) - AIF2 DAC Right Volume 2762 */ 2763#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 2764#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 2765#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 2766#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 2767#define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ 2768#define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ 2769#define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ 2770 2771/* 2772 * R1296 (0x510) - AIF2 ADC Filters 2773 */ 2774#define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ 2775#define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ 2776#define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ 2777#define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ 2778#define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ 2779#define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ 2780#define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ 2781#define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ 2782#define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ 2783#define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ 2784#define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ 2785#define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ 2786#define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */ 2787#define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */ 2788#define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */ 2789#define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */ 2790#define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */ 2791#define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */ 2792#define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */ 2793 2794/* 2795 * R1312 (0x520) - AIF2 DAC Filters (1) 2796 */ 2797#define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ 2798#define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ 2799#define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ 2800#define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ 2801#define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ 2802#define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ 2803#define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ 2804#define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ 2805#define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ 2806#define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ 2807#define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ 2808#define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ 2809#define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 2810#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 2811#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ 2812#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ 2813#define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ 2814#define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ 2815#define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ 2816 2817/* 2818 * R1313 (0x521) - AIF2 DAC Filters (2) 2819 */ 2820#define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ 2821#define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ 2822#define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ 2823#define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ 2824#define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ 2825#define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ 2826#define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ 2827 2828/* 2829 * R1344 (0x540) - AIF2 DRC (1) 2830 */ 2831#define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 2832#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 2833#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 2834#define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ 2835#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ 2836#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ 2837#define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ 2838#define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ 2839#define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ 2840#define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ 2841#define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ 2842#define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ 2843#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ 2844#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ 2845#define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ 2846#define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ 2847#define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ 2848#define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ 2849#define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 2850#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 2851#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ 2852#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ 2853#define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ 2854#define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ 2855#define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ 2856#define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ 2857#define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ 2858#define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ 2859#define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ 2860#define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ 2861#define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ 2862#define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ 2863#define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ 2864#define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ 2865#define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ 2866#define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ 2867#define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ 2868#define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ 2869#define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ 2870#define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ 2871#define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ 2872#define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ 2873 2874/* 2875 * R1345 (0x541) - AIF2 DRC (2) 2876 */ 2877#define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ 2878#define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ 2879#define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ 2880#define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ 2881#define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ 2882#define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ 2883#define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ 2884#define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ 2885#define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ 2886#define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ 2887#define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ 2888#define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ 2889 2890/* 2891 * R1346 (0x542) - AIF2 DRC (3) 2892 */ 2893#define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ 2894#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ 2895#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ 2896#define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ 2897#define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ 2898#define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ 2899#define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ 2900#define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ 2901#define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ 2902#define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ 2903#define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ 2904#define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ 2905#define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ 2906#define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ 2907#define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ 2908#define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ 2909#define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ 2910#define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ 2911 2912/* 2913 * R1347 (0x543) - AIF2 DRC (4) 2914 */ 2915#define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ 2916#define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ 2917#define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ 2918#define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ 2919#define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ 2920#define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ 2921 2922/* 2923 * R1348 (0x544) - AIF2 DRC (5) 2924 */ 2925#define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ 2926#define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 2927#define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 2928#define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ 2929#define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ 2930#define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ 2931 2932/* 2933 * R1408 (0x580) - AIF2 EQ Gains (1) 2934 */ 2935#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 2936#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 2937#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 2938#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 2939#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 2940#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 2941#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 2942#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 2943#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 2944#define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ 2945#define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ 2946#define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ 2947#define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ 2948 2949/* 2950 * R1409 (0x581) - AIF2 EQ Gains (2) 2951 */ 2952#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 2953#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 2954#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 2955#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 2956#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 2957#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 2958 2959/* 2960 * R1410 (0x582) - AIF2 EQ Band 1 A 2961 */ 2962#define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ 2963#define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ 2964#define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ 2965 2966/* 2967 * R1411 (0x583) - AIF2 EQ Band 1 B 2968 */ 2969#define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ 2970#define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ 2971#define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ 2972 2973/* 2974 * R1412 (0x584) - AIF2 EQ Band 1 PG 2975 */ 2976#define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ 2977#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ 2978#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ 2979 2980/* 2981 * R1413 (0x585) - AIF2 EQ Band 2 A 2982 */ 2983#define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ 2984#define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ 2985#define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ 2986 2987/* 2988 * R1414 (0x586) - AIF2 EQ Band 2 B 2989 */ 2990#define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ 2991#define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ 2992#define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ 2993 2994/* 2995 * R1415 (0x587) - AIF2 EQ Band 2 C 2996 */ 2997#define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ 2998#define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ 2999#define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ 3000 3001/* 3002 * R1416 (0x588) - AIF2 EQ Band 2 PG 3003 */ 3004#define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ 3005#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3006#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3007 3008/* 3009 * R1417 (0x589) - AIF2 EQ Band 3 A 3010 */ 3011#define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ 3012#define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ 3013#define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ 3014 3015/* 3016 * R1418 (0x58A) - AIF2 EQ Band 3 B 3017 */ 3018#define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ 3019#define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ 3020#define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ 3021 3022/* 3023 * R1419 (0x58B) - AIF2 EQ Band 3 C 3024 */ 3025#define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ 3026#define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ 3027#define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ 3028 3029/* 3030 * R1420 (0x58C) - AIF2 EQ Band 3 PG 3031 */ 3032#define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ 3033#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3034#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3035 3036/* 3037 * R1421 (0x58D) - AIF2 EQ Band 4 A 3038 */ 3039#define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ 3040#define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ 3041#define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ 3042 3043/* 3044 * R1422 (0x58E) - AIF2 EQ Band 4 B 3045 */ 3046#define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ 3047#define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ 3048#define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ 3049 3050/* 3051 * R1423 (0x58F) - AIF2 EQ Band 4 C 3052 */ 3053#define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ 3054#define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ 3055#define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ 3056 3057/* 3058 * R1424 (0x590) - AIF2 EQ Band 4 PG 3059 */ 3060#define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ 3061#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3062#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3063 3064/* 3065 * R1425 (0x591) - AIF2 EQ Band 5 A 3066 */ 3067#define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ 3068#define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ 3069#define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ 3070 3071/* 3072 * R1426 (0x592) - AIF2 EQ Band 5 B 3073 */ 3074#define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ 3075#define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ 3076#define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ 3077 3078/* 3079 * R1427 (0x593) - AIF2 EQ Band 5 PG 3080 */ 3081#define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ 3082#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3083#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3084 3085/* 3086 * R1536 (0x600) - DAC1 Mixer Volumes 3087 */ 3088#define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ 3089#define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ 3090#define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ 3091#define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ 3092#define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ 3093#define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ 3094 3095/* 3096 * R1537 (0x601) - DAC1 Left Mixer Routing 3097 */ 3098#define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 3099#define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 3100#define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 3101#define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 3102#define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 3103#define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 3104#define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 3105#define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 3106#define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ 3107#define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ 3108#define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ 3109#define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ 3110#define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3111#define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3112#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ 3113#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ 3114#define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3115#define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3116#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ 3117#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ 3118 3119/* 3120 * R1538 (0x602) - DAC1 Right Mixer Routing 3121 */ 3122#define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 3123#define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 3124#define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 3125#define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 3126#define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 3127#define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 3128#define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 3129#define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 3130#define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ 3131#define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ 3132#define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ 3133#define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ 3134#define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3135#define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3136#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ 3137#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ 3138#define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3139#define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3140#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ 3141#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ 3142 3143/* 3144 * R1539 (0x603) - DAC2 Mixer Volumes 3145 */ 3146#define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ 3147#define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ 3148#define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ 3149#define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ 3150#define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ 3151#define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ 3152 3153/* 3154 * R1540 (0x604) - DAC2 Left Mixer Routing 3155 */ 3156#define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 3157#define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 3158#define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 3159#define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 3160#define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 3161#define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 3162#define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 3163#define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 3164#define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ 3165#define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ 3166#define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ 3167#define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ 3168#define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3169#define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3170#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ 3171#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ 3172#define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3173#define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3174#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ 3175#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ 3176 3177/* 3178 * R1541 (0x605) - DAC2 Right Mixer Routing 3179 */ 3180#define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 3181#define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 3182#define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 3183#define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 3184#define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 3185#define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 3186#define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 3187#define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 3188#define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ 3189#define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ 3190#define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ 3191#define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ 3192#define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3193#define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3194#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ 3195#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ 3196#define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3197#define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3198#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ 3199#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ 3200 3201/* 3202 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing 3203 */ 3204#define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3205#define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3206#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ 3207#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ 3208#define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3209#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3210#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ 3211#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ 3212 3213/* 3214 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing 3215 */ 3216#define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3217#define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3218#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ 3219#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ 3220#define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3221#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3222#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ 3223#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ 3224 3225/* 3226 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing 3227 */ 3228#define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3229#define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3230#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ 3231#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ 3232#define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3233#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3234#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ 3235#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ 3236 3237/* 3238 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing 3239 */ 3240#define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3241#define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3242#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ 3243#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ 3244#define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3245#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3246#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ 3247#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ 3248 3249/* 3250 * R1552 (0x610) - DAC Softmute 3251 */ 3252#define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 3253#define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 3254#define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 3255#define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 3256#define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 3257#define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 3258#define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 3259#define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 3260 3261/* 3262 * R1568 (0x620) - Oversampling 3263 */ 3264#define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */ 3265#define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 3266#define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 3267#define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 3268#define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */ 3269#define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 3270#define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 3271#define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 3272 3273/* 3274 * R1569 (0x621) - Sidetone 3275 */ 3276#define WM8995_ST_LPF 0x1000 /* ST_LPF */ 3277#define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */ 3278#define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */ 3279#define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */ 3280#define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 3281#define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 3282#define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 3283#define WM8995_ST_HPF 0x0040 /* ST_HPF */ 3284#define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */ 3285#define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */ 3286#define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */ 3287#define WM8995_STR_SEL 0x0002 /* STR_SEL */ 3288#define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */ 3289#define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */ 3290#define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */ 3291#define WM8995_STL_SEL 0x0001 /* STL_SEL */ 3292#define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */ 3293#define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */ 3294#define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */ 3295 3296/* 3297 * R1792 (0x700) - GPIO 1 3298 */ 3299#define WM8995_GP1_DIR 0x8000 /* GP1_DIR */ 3300#define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 3301#define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */ 3302#define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */ 3303#define WM8995_GP1_PU 0x4000 /* GP1_PU */ 3304#define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */ 3305#define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */ 3306#define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */ 3307#define WM8995_GP1_PD 0x2000 /* GP1_PD */ 3308#define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */ 3309#define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */ 3310#define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */ 3311#define WM8995_GP1_POL 0x0400 /* GP1_POL */ 3312#define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */ 3313#define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */ 3314#define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */ 3315#define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 3316#define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 3317#define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 3318#define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 3319#define WM8995_GP1_DB 0x0100 /* GP1_DB */ 3320#define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */ 3321#define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */ 3322#define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */ 3323#define WM8995_GP1_LVL 0x0040 /* GP1_LVL */ 3324#define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 3325#define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */ 3326#define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */ 3327#define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */ 3328#define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */ 3329#define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */ 3330 3331/* 3332 * R1793 (0x701) - GPIO 2 3333 */ 3334#define WM8995_GP2_DIR 0x8000 /* GP2_DIR */ 3335#define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 3336#define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */ 3337#define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */ 3338#define WM8995_GP2_PU 0x4000 /* GP2_PU */ 3339#define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */ 3340#define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */ 3341#define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */ 3342#define WM8995_GP2_PD 0x2000 /* GP2_PD */ 3343#define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */ 3344#define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */ 3345#define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */ 3346#define WM8995_GP2_POL 0x0400 /* GP2_POL */ 3347#define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */ 3348#define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */ 3349#define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */ 3350#define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 3351#define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 3352#define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 3353#define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 3354#define WM8995_GP2_DB 0x0100 /* GP2_DB */ 3355#define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */ 3356#define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */ 3357#define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */ 3358#define WM8995_GP2_LVL 0x0040 /* GP2_LVL */ 3359#define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3360#define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3361#define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3362#define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ 3363#define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ 3364#define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ 3365 3366/* 3367 * R1794 (0x702) - GPIO 3 3368 */ 3369#define WM8995_GP3_DIR 0x8000 /* GP3_DIR */ 3370#define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 3371#define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */ 3372#define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */ 3373#define WM8995_GP3_PU 0x4000 /* GP3_PU */ 3374#define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */ 3375#define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */ 3376#define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */ 3377#define WM8995_GP3_PD 0x2000 /* GP3_PD */ 3378#define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */ 3379#define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */ 3380#define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */ 3381#define WM8995_GP3_POL 0x0400 /* GP3_POL */ 3382#define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */ 3383#define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */ 3384#define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */ 3385#define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3386#define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3387#define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3388#define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3389#define WM8995_GP3_DB 0x0100 /* GP3_DB */ 3390#define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */ 3391#define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */ 3392#define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */ 3393#define WM8995_GP3_LVL 0x0040 /* GP3_LVL */ 3394#define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3395#define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3396#define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3397#define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ 3398#define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ 3399#define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ 3400 3401/* 3402 * R1795 (0x703) - GPIO 4 3403 */ 3404#define WM8995_GP4_DIR 0x8000 /* GP4_DIR */ 3405#define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3406#define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3407#define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3408#define WM8995_GP4_PU 0x4000 /* GP4_PU */ 3409#define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */ 3410#define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */ 3411#define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */ 3412#define WM8995_GP4_PD 0x2000 /* GP4_PD */ 3413#define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */ 3414#define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */ 3415#define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */ 3416#define WM8995_GP4_POL 0x0400 /* GP4_POL */ 3417#define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */ 3418#define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */ 3419#define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */ 3420#define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3421#define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3422#define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3423#define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3424#define WM8995_GP4_DB 0x0100 /* GP4_DB */ 3425#define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */ 3426#define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */ 3427#define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */ 3428#define WM8995_GP4_LVL 0x0040 /* GP4_LVL */ 3429#define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3430#define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3431#define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3432#define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */ 3433#define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */ 3434#define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */ 3435 3436/* 3437 * R1796 (0x704) - GPIO 5 3438 */ 3439#define WM8995_GP5_DIR 0x8000 /* GP5_DIR */ 3440#define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3441#define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3442#define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3443#define WM8995_GP5_PU 0x4000 /* GP5_PU */ 3444#define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */ 3445#define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */ 3446#define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */ 3447#define WM8995_GP5_PD 0x2000 /* GP5_PD */ 3448#define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */ 3449#define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */ 3450#define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */ 3451#define WM8995_GP5_POL 0x0400 /* GP5_POL */ 3452#define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */ 3453#define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */ 3454#define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */ 3455#define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3456#define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3457#define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3458#define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3459#define WM8995_GP5_DB 0x0100 /* GP5_DB */ 3460#define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */ 3461#define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */ 3462#define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */ 3463#define WM8995_GP5_LVL 0x0040 /* GP5_LVL */ 3464#define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3465#define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3466#define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3467#define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ 3468#define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ 3469#define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ 3470 3471/* 3472 * R1797 (0x705) - GPIO 6 3473 */ 3474#define WM8995_GP6_DIR 0x8000 /* GP6_DIR */ 3475#define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3476#define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3477#define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3478#define WM8995_GP6_PU 0x4000 /* GP6_PU */ 3479#define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */ 3480#define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */ 3481#define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */ 3482#define WM8995_GP6_PD 0x2000 /* GP6_PD */ 3483#define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */ 3484#define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */ 3485#define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */ 3486#define WM8995_GP6_POL 0x0400 /* GP6_POL */ 3487#define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */ 3488#define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */ 3489#define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */ 3490#define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3491#define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3492#define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3493#define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3494#define WM8995_GP6_DB 0x0100 /* GP6_DB */ 3495#define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */ 3496#define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */ 3497#define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */ 3498#define WM8995_GP6_LVL 0x0040 /* GP6_LVL */ 3499#define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3500#define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3501#define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3502#define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ 3503#define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ 3504#define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ 3505 3506/* 3507 * R1798 (0x706) - GPIO 7 3508 */ 3509#define WM8995_GP7_DIR 0x8000 /* GP7_DIR */ 3510#define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */ 3511#define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */ 3512#define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */ 3513#define WM8995_GP7_PU 0x4000 /* GP7_PU */ 3514#define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */ 3515#define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */ 3516#define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */ 3517#define WM8995_GP7_PD 0x2000 /* GP7_PD */ 3518#define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */ 3519#define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */ 3520#define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */ 3521#define WM8995_GP7_POL 0x0400 /* GP7_POL */ 3522#define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */ 3523#define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */ 3524#define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */ 3525#define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */ 3526#define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */ 3527#define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */ 3528#define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */ 3529#define WM8995_GP7_DB 0x0100 /* GP7_DB */ 3530#define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */ 3531#define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */ 3532#define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */ 3533#define WM8995_GP7_LVL 0x0040 /* GP7_LVL */ 3534#define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */ 3535#define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */ 3536#define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */ 3537#define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */ 3538#define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */ 3539#define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */ 3540 3541/* 3542 * R1799 (0x707) - GPIO 8 3543 */ 3544#define WM8995_GP8_DIR 0x8000 /* GP8_DIR */ 3545#define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */ 3546#define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */ 3547#define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */ 3548#define WM8995_GP8_PU 0x4000 /* GP8_PU */ 3549#define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */ 3550#define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */ 3551#define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */ 3552#define WM8995_GP8_PD 0x2000 /* GP8_PD */ 3553#define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */ 3554#define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */ 3555#define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */ 3556#define WM8995_GP8_POL 0x0400 /* GP8_POL */ 3557#define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */ 3558#define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */ 3559#define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */ 3560#define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */ 3561#define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */ 3562#define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */ 3563#define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */ 3564#define WM8995_GP8_DB 0x0100 /* GP8_DB */ 3565#define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */ 3566#define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */ 3567#define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */ 3568#define WM8995_GP8_LVL 0x0040 /* GP8_LVL */ 3569#define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */ 3570#define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */ 3571#define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */ 3572#define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */ 3573#define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */ 3574#define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */ 3575 3576/* 3577 * R1800 (0x708) - GPIO 9 3578 */ 3579#define WM8995_GP9_DIR 0x8000 /* GP9_DIR */ 3580#define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */ 3581#define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */ 3582#define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */ 3583#define WM8995_GP9_PU 0x4000 /* GP9_PU */ 3584#define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */ 3585#define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */ 3586#define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */ 3587#define WM8995_GP9_PD 0x2000 /* GP9_PD */ 3588#define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */ 3589#define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */ 3590#define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */ 3591#define WM8995_GP9_POL 0x0400 /* GP9_POL */ 3592#define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */ 3593#define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */ 3594#define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */ 3595#define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */ 3596#define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */ 3597#define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */ 3598#define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */ 3599#define WM8995_GP9_DB 0x0100 /* GP9_DB */ 3600#define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */ 3601#define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */ 3602#define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */ 3603#define WM8995_GP9_LVL 0x0040 /* GP9_LVL */ 3604#define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */ 3605#define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */ 3606#define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */ 3607#define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */ 3608#define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */ 3609#define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */ 3610 3611/* 3612 * R1801 (0x709) - GPIO 10 3613 */ 3614#define WM8995_GP10_DIR 0x8000 /* GP10_DIR */ 3615#define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */ 3616#define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */ 3617#define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */ 3618#define WM8995_GP10_PU 0x4000 /* GP10_PU */ 3619#define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */ 3620#define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */ 3621#define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */ 3622#define WM8995_GP10_PD 0x2000 /* GP10_PD */ 3623#define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */ 3624#define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */ 3625#define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */ 3626#define WM8995_GP10_POL 0x0400 /* GP10_POL */ 3627#define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */ 3628#define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */ 3629#define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */ 3630#define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */ 3631#define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */ 3632#define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */ 3633#define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */ 3634#define WM8995_GP10_DB 0x0100 /* GP10_DB */ 3635#define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */ 3636#define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */ 3637#define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */ 3638#define WM8995_GP10_LVL 0x0040 /* GP10_LVL */ 3639#define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */ 3640#define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */ 3641#define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */ 3642#define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */ 3643#define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */ 3644#define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */ 3645 3646/* 3647 * R1802 (0x70A) - GPIO 11 3648 */ 3649#define WM8995_GP11_DIR 0x8000 /* GP11_DIR */ 3650#define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */ 3651#define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */ 3652#define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */ 3653#define WM8995_GP11_PU 0x4000 /* GP11_PU */ 3654#define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */ 3655#define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */ 3656#define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */ 3657#define WM8995_GP11_PD 0x2000 /* GP11_PD */ 3658#define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */ 3659#define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */ 3660#define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */ 3661#define WM8995_GP11_POL 0x0400 /* GP11_POL */ 3662#define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */ 3663#define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */ 3664#define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */ 3665#define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */ 3666#define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */ 3667#define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */ 3668#define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */ 3669#define WM8995_GP11_DB 0x0100 /* GP11_DB */ 3670#define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */ 3671#define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */ 3672#define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */ 3673#define WM8995_GP11_LVL 0x0040 /* GP11_LVL */ 3674#define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */ 3675#define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */ 3676#define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */ 3677#define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */ 3678#define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */ 3679#define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */ 3680 3681/* 3682 * R1803 (0x70B) - GPIO 12 3683 */ 3684#define WM8995_GP12_DIR 0x8000 /* GP12_DIR */ 3685#define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */ 3686#define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */ 3687#define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */ 3688#define WM8995_GP12_PU 0x4000 /* GP12_PU */ 3689#define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */ 3690#define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */ 3691#define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */ 3692#define WM8995_GP12_PD 0x2000 /* GP12_PD */ 3693#define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */ 3694#define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */ 3695#define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */ 3696#define WM8995_GP12_POL 0x0400 /* GP12_POL */ 3697#define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */ 3698#define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */ 3699#define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */ 3700#define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */ 3701#define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */ 3702#define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */ 3703#define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */ 3704#define WM8995_GP12_DB 0x0100 /* GP12_DB */ 3705#define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */ 3706#define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */ 3707#define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */ 3708#define WM8995_GP12_LVL 0x0040 /* GP12_LVL */ 3709#define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */ 3710#define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */ 3711#define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */ 3712#define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */ 3713#define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */ 3714#define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */ 3715 3716/* 3717 * R1804 (0x70C) - GPIO 13 3718 */ 3719#define WM8995_GP13_DIR 0x8000 /* GP13_DIR */ 3720#define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */ 3721#define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */ 3722#define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */ 3723#define WM8995_GP13_PU 0x4000 /* GP13_PU */ 3724#define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */ 3725#define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */ 3726#define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */ 3727#define WM8995_GP13_PD 0x2000 /* GP13_PD */ 3728#define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */ 3729#define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */ 3730#define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */ 3731#define WM8995_GP13_POL 0x0400 /* GP13_POL */ 3732#define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */ 3733#define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */ 3734#define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */ 3735#define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */ 3736#define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */ 3737#define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */ 3738#define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */ 3739#define WM8995_GP13_DB 0x0100 /* GP13_DB */ 3740#define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */ 3741#define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */ 3742#define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */ 3743#define WM8995_GP13_LVL 0x0040 /* GP13_LVL */ 3744#define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */ 3745#define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */ 3746#define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */ 3747#define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */ 3748#define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */ 3749#define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */ 3750 3751/* 3752 * R1805 (0x70D) - GPIO 14 3753 */ 3754#define WM8995_GP14_DIR 0x8000 /* GP14_DIR */ 3755#define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */ 3756#define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */ 3757#define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */ 3758#define WM8995_GP14_PU 0x4000 /* GP14_PU */ 3759#define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */ 3760#define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */ 3761#define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */ 3762#define WM8995_GP14_PD 0x2000 /* GP14_PD */ 3763#define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */ 3764#define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */ 3765#define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */ 3766#define WM8995_GP14_POL 0x0400 /* GP14_POL */ 3767#define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */ 3768#define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */ 3769#define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */ 3770#define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */ 3771#define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */ 3772#define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */ 3773#define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */ 3774#define WM8995_GP14_DB 0x0100 /* GP14_DB */ 3775#define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */ 3776#define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */ 3777#define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */ 3778#define WM8995_GP14_LVL 0x0040 /* GP14_LVL */ 3779#define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */ 3780#define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */ 3781#define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */ 3782#define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */ 3783#define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */ 3784#define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */ 3785 3786/* 3787 * R1824 (0x720) - Pull Control (1) 3788 */ 3789#define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */ 3790#define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */ 3791#define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */ 3792#define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 3793#define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ 3794#define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ 3795#define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ 3796#define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3797#define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ 3798#define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ 3799#define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ 3800#define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3801#define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */ 3802#define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ 3803#define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ 3804#define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ 3805#define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */ 3806#define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ 3807#define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ 3808#define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3809#define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */ 3810#define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 3811#define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 3812#define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 3813#define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */ 3814#define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 3815#define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 3816#define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3817#define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 3818#define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 3819#define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 3820#define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 3821#define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 3822#define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 3823#define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 3824#define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 3825#define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 3826#define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 3827#define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 3828#define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 3829#define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 3830#define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 3831#define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 3832#define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 3833#define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */ 3834#define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 3835#define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 3836#define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 3837#define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */ 3838#define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 3839#define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 3840#define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 3841 3842/* 3843 * R1825 (0x721) - Pull Control (2) 3844 */ 3845#define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ 3846#define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ 3847#define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ 3848#define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3849#define WM8995_MODE_PD 0x0004 /* MODE_PD */ 3850#define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */ 3851#define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */ 3852#define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */ 3853#define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */ 3854#define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */ 3855#define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */ 3856#define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ 3857 3858/* 3859 * R1840 (0x730) - Interrupt Status 1 3860 */ 3861#define WM8995_GP14_EINT 0x2000 /* GP14_EINT */ 3862#define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */ 3863#define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */ 3864#define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */ 3865#define WM8995_GP13_EINT 0x1000 /* GP13_EINT */ 3866#define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */ 3867#define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */ 3868#define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */ 3869#define WM8995_GP12_EINT 0x0800 /* GP12_EINT */ 3870#define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */ 3871#define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */ 3872#define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */ 3873#define WM8995_GP11_EINT 0x0400 /* GP11_EINT */ 3874#define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 3875#define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */ 3876#define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */ 3877#define WM8995_GP10_EINT 0x0200 /* GP10_EINT */ 3878#define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 3879#define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */ 3880#define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */ 3881#define WM8995_GP9_EINT 0x0100 /* GP9_EINT */ 3882#define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 3883#define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */ 3884#define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */ 3885#define WM8995_GP8_EINT 0x0080 /* GP8_EINT */ 3886#define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 3887#define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */ 3888#define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */ 3889#define WM8995_GP7_EINT 0x0040 /* GP7_EINT */ 3890#define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 3891#define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */ 3892#define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */ 3893#define WM8995_GP6_EINT 0x0020 /* GP6_EINT */ 3894#define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3895#define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3896#define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3897#define WM8995_GP5_EINT 0x0010 /* GP5_EINT */ 3898#define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3899#define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3900#define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3901#define WM8995_GP4_EINT 0x0008 /* GP4_EINT */ 3902#define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3903#define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3904#define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3905#define WM8995_GP3_EINT 0x0004 /* GP3_EINT */ 3906#define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3907#define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3908#define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3909#define WM8995_GP2_EINT 0x0002 /* GP2_EINT */ 3910#define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3911#define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3912#define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3913#define WM8995_GP1_EINT 0x0001 /* GP1_EINT */ 3914#define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3915#define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3916#define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3917 3918/* 3919 * R1841 (0x731) - Interrupt Status 2 3920 */ 3921#define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ 3922#define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ 3923#define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ 3924#define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ 3925#define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ 3926#define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ 3927#define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ 3928#define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ 3929#define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ 3930#define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ 3931#define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ 3932#define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 3933#define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ 3934#define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ 3935#define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ 3936#define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 3937#define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */ 3938#define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */ 3939#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */ 3940#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ 3941#define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */ 3942#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */ 3943#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */ 3944#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ 3945#define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */ 3946#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */ 3947#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */ 3948#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ 3949#define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */ 3950#define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */ 3951#define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */ 3952#define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ 3953#define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */ 3954#define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */ 3955#define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */ 3956#define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ 3957#define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 3958#define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 3959#define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 3960#define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 3961#define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 3962#define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 3963#define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 3964#define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 3965#define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ 3966#define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ 3967#define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ 3968#define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ 3969#define WM8995_MICD_EINT 0x0001 /* MICD_EINT */ 3970#define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */ 3971#define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */ 3972#define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */ 3973 3974/* 3975 * R1842 (0x732) - Interrupt Raw Status 2 3976 */ 3977#define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ 3978#define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ 3979#define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ 3980#define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ 3981#define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ 3982#define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ 3983#define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ 3984#define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ 3985#define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ 3986#define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ 3987#define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ 3988#define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 3989#define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ 3990#define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ 3991#define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ 3992#define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 3993#define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */ 3994#define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */ 3995#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */ 3996#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ 3997#define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */ 3998#define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */ 3999#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */ 4000#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ 4001#define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */ 4002#define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */ 4003#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */ 4004#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ 4005#define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */ 4006#define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */ 4007#define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */ 4008#define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ 4009#define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */ 4010#define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */ 4011#define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */ 4012#define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ 4013#define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 4014#define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 4015#define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 4016#define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 4017#define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 4018#define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 4019#define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 4020#define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 4021 4022/* 4023 * R1848 (0x738) - Interrupt Status 1 Mask 4024 */ 4025#define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ 4026#define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ 4027#define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ 4028#define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ 4029#define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ 4030#define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ 4031#define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ 4032#define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ 4033#define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ 4034#define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ 4035#define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ 4036#define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ 4037#define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 4038#define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 4039#define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 4040#define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 4041#define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 4042#define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 4043#define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 4044#define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 4045#define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 4046#define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 4047#define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 4048#define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 4049#define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 4050#define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 4051#define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 4052#define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 4053#define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 4054#define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 4055#define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 4056#define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 4057#define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 4058#define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 4059#define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 4060#define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 4061#define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 4062#define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 4063#define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 4064#define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 4065#define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 4066#define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 4067#define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 4068#define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 4069#define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 4070#define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 4071#define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 4072#define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 4073#define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 4074#define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 4075#define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 4076#define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 4077#define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 4078#define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 4079#define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 4080#define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 4081 4082/* 4083 * R1849 (0x739) - Interrupt Status 2 Mask 4084 */ 4085#define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ 4086#define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ 4087#define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ 4088#define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ 4089#define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ 4090#define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ 4091#define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ 4092#define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ 4093#define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ 4094#define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ 4095#define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ 4096#define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 4097#define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ 4098#define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ 4099#define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ 4100#define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 4101#define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ 4102#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ 4103#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */ 4104#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ 4105#define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ 4106#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ 4107#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */ 4108#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ 4109#define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ 4110#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ 4111#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */ 4112#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ 4113#define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */ 4114#define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */ 4115#define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */ 4116#define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ 4117#define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */ 4118#define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */ 4119#define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */ 4120#define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ 4121#define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 4122#define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 4123#define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 4124#define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 4125#define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 4126#define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 4127#define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 4128#define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 4129#define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ 4130#define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ 4131#define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ 4132#define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ 4133#define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ 4134#define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ 4135#define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ 4136#define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ 4137 4138/* 4139 * R1856 (0x740) - Interrupt Control 4140 */ 4141#define WM8995_IM_IRQ 0x0001 /* IM_IRQ */ 4142#define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 4143#define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */ 4144#define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */ 4145 4146/* 4147 * R2048 (0x800) - Left PDM Speaker 1 4148 */ 4149#define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */ 4150#define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */ 4151#define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */ 4152#define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */ 4153#define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */ 4154#define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */ 4155#define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */ 4156#define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 4157#define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */ 4158#define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */ 4159#define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */ 4160#define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */ 4161#define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */ 4162#define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */ 4163#define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */ 4164 4165/* 4166 * R2049 (0x801) - Right PDM Speaker 1 4167 */ 4168#define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */ 4169#define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */ 4170#define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */ 4171#define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */ 4172#define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */ 4173#define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */ 4174#define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */ 4175#define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 4176#define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */ 4177#define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */ 4178#define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */ 4179#define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */ 4180#define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */ 4181#define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */ 4182#define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */ 4183 4184/* 4185 * R2050 (0x802) - PDM Speaker 1 Mute Sequence 4186 */ 4187#define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 4188#define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 4189#define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 4190 4191/* 4192 * R2056 (0x808) - Left PDM Speaker 2 4193 */ 4194#define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */ 4195#define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */ 4196#define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */ 4197#define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */ 4198#define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */ 4199#define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */ 4200#define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */ 4201#define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 4202#define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */ 4203#define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */ 4204#define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */ 4205#define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */ 4206#define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */ 4207#define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */ 4208#define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */ 4209 4210/* 4211 * R2057 (0x809) - Right PDM Speaker 2 4212 */ 4213#define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */ 4214#define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */ 4215#define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */ 4216#define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */ 4217#define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */ 4218#define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */ 4219#define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */ 4220#define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 4221#define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */ 4222#define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */ 4223#define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */ 4224#define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */ 4225#define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */ 4226#define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */ 4227#define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */ 4228 4229/* 4230 * R2058 (0x80A) - PDM Speaker 2 Mute Sequence 4231 */ 4232#define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 4233#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 4234#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 4235 4236#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 4237 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 4238 snd_soc_dapm_get_volsw, wm8995_put_class_w) 4239 4240struct wm8995_reg_access { 4241 u16 read; 4242 u16 write; 4243 u16 vol; 4244}; 4245 4246/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 4247enum clk_src { 4248 WM8995_SYSCLK_MCLK1 = 1, 4249 WM8995_SYSCLK_MCLK2, 4250 WM8995_SYSCLK_FLL1, 4251 WM8995_SYSCLK_FLL2, 4252 WM8995_SYSCLK_OPCLK 4253}; 4254 4255#define WM8995_FLL1 1 4256#define WM8995_FLL2 2 4257 4258#define WM8995_FLL_SRC_MCLK1 1 4259#define WM8995_FLL_SRC_MCLK2 2 4260#define WM8995_FLL_SRC_LRCLK 3 4261#define WM8995_FLL_SRC_BCLK 4 4262 4263#endif /* _WM8995_H */