cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl_micfil.h (4601B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * PDM Microphone Interface for the NXP i.MX SoC
      4 * Copyright 2018 NXP
      5 */
      6
      7#ifndef _FSL_MICFIL_H
      8#define _FSL_MICFIL_H
      9
     10/* MICFIL Register Map */
     11#define REG_MICFIL_CTRL1		0x00
     12#define REG_MICFIL_CTRL2		0x04
     13#define REG_MICFIL_STAT			0x08
     14#define REG_MICFIL_FIFO_CTRL		0x10
     15#define REG_MICFIL_FIFO_STAT		0x14
     16#define REG_MICFIL_DATACH0		0x24
     17#define REG_MICFIL_DATACH1		0x28
     18#define REG_MICFIL_DATACH2		0x2C
     19#define REG_MICFIL_DATACH3		0x30
     20#define REG_MICFIL_DATACH4		0x34
     21#define REG_MICFIL_DATACH5		0x38
     22#define REG_MICFIL_DATACH6		0x3C
     23#define REG_MICFIL_DATACH7		0x40
     24#define REG_MICFIL_DC_CTRL		0x64
     25#define REG_MICFIL_OUT_CTRL		0x74
     26#define REG_MICFIL_OUT_STAT		0x7C
     27#define REG_MICFIL_VAD0_CTRL1		0x90
     28#define REG_MICFIL_VAD0_CTRL2		0x94
     29#define REG_MICFIL_VAD0_STAT		0x98
     30#define REG_MICFIL_VAD0_SCONFIG		0x9C
     31#define REG_MICFIL_VAD0_NCONFIG		0xA0
     32#define REG_MICFIL_VAD0_NDATA		0xA4
     33#define REG_MICFIL_VAD0_ZCD		0xA8
     34
     35/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
     36#define MICFIL_CTRL1_MDIS		BIT(31)
     37#define MICFIL_CTRL1_DOZEN		BIT(30)
     38#define MICFIL_CTRL1_PDMIEN		BIT(29)
     39#define MICFIL_CTRL1_DBG		BIT(28)
     40#define MICFIL_CTRL1_SRES		BIT(27)
     41#define MICFIL_CTRL1_DBGE		BIT(26)
     42
     43#define MICFIL_CTRL1_DISEL_DISABLE	0
     44#define MICFIL_CTRL1_DISEL_DMA		1
     45#define MICFIL_CTRL1_DISEL_IRQ		2
     46#define MICFIL_CTRL1_DISEL		GENMASK(25, 24)
     47#define MICFIL_CTRL1_ERREN		BIT(23)
     48#define MICFIL_CTRL1_CHEN(ch)		BIT(ch)
     49
     50/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
     51#define MICFIL_CTRL2_QSEL_SHIFT		25
     52#define MICFIL_CTRL2_QSEL		GENMASK(27, 25)
     53#define MICFIL_QSEL_MEDIUM_QUALITY	0
     54#define MICFIL_QSEL_HIGH_QUALITY	1
     55#define MICFIL_QSEL_LOW_QUALITY		7
     56#define MICFIL_QSEL_VLOW0_QUALITY	6
     57#define MICFIL_QSEL_VLOW1_QUALITY	5
     58#define MICFIL_QSEL_VLOW2_QUALITY	4
     59
     60#define MICFIL_CTRL2_CICOSR		GENMASK(19, 16)
     61#define MICFIL_CTRL2_CLKDIV		GENMASK(7, 0)
     62
     63/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
     64#define MICFIL_STAT_BSY_FIL		BIT(31)
     65#define MICFIL_STAT_FIR_RDY		BIT(30)
     66#define MICFIL_STAT_LOWFREQF		BIT(29)
     67#define MICFIL_STAT_CHXF(ch)		BIT(ch)
     68
     69/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
     70#define MICFIL_FIFO_CTRL_FIFOWMK	GENMASK(2, 0)
     71
     72/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
     73#define MICFIL_FIFO_STAT_FIFOX_OVER(ch)	BIT(ch)
     74#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)	BIT((ch) + 8)
     75
     76/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
     77#define MICFIL_VAD0_CTRL1_CHSEL		GENMASK(26, 24)
     78#define MICFIL_VAD0_CTRL1_CICOSR	GENMASK(19, 16)
     79#define MICFIL_VAD0_CTRL1_INITT		GENMASK(12, 8)
     80#define MICFIL_VAD0_CTRL1_ST10		BIT(4)
     81#define MICFIL_VAD0_CTRL1_ERIE		BIT(3)
     82#define MICFIL_VAD0_CTRL1_IE		BIT(2)
     83#define MICFIL_VAD0_CTRL1_RST		BIT(1)
     84#define MICFIL_VAD0_CTRL1_EN		BIT(0)
     85
     86/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
     87#define MICFIL_VAD0_CTRL2_FRENDIS	BIT(31)
     88#define MICFIL_VAD0_CTRL2_PREFEN	BIT(30)
     89#define MICFIL_VAD0_CTRL2_FOUTDIS	BIT(28)
     90#define MICFIL_VAD0_CTRL2_FRAMET	GENMASK(21, 16)
     91#define MICFIL_VAD0_CTRL2_INPGAIN	GENMASK(11, 8)
     92#define MICFIL_VAD0_CTRL2_HPF		GENMASK(1, 0)
     93
     94/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
     95#define MICFIL_VAD0_SCONFIG_SFILEN		BIT(31)
     96#define MICFIL_VAD0_SCONFIG_SMAXEN		BIT(30)
     97#define MICFIL_VAD0_SCONFIG_SGAIN		GENMASK(3, 0)
     98
     99/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
    100#define MICFIL_VAD0_NCONFIG_NFILAUT		BIT(31)
    101#define MICFIL_VAD0_NCONFIG_NMINEN		BIT(30)
    102#define MICFIL_VAD0_NCONFIG_NDECEN		BIT(29)
    103#define MICFIL_VAD0_NCONFIG_NOREN		BIT(28)
    104#define MICFIL_VAD0_NCONFIG_NFILADJ		GENMASK(12, 8)
    105#define MICFIL_VAD0_NCONFIG_NGAIN		GENMASK(3, 0)
    106
    107/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
    108#define MICFIL_VAD0_ZCD_ZCDTH		GENMASK(25, 16)
    109#define MICFIL_VAD0_ZCD_ZCDADJ		GENMASK(11, 8)
    110#define MICFIL_VAD0_ZCD_ZCDAND		BIT(4)
    111#define MICFIL_VAD0_ZCD_ZCDAUT		BIT(2)
    112#define MICFIL_VAD0_ZCD_ZCDEN		BIT(0)
    113
    114/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
    115#define MICFIL_VAD0_STAT_INITF		BIT(31)
    116#define MICFIL_VAD0_STAT_INSATF		BIT(16)
    117#define MICFIL_VAD0_STAT_EF		BIT(15)
    118#define MICFIL_VAD0_STAT_IF		BIT(0)
    119
    120/* MICFIL Output Control Register */
    121#define MICFIL_OUTGAIN_CHX_SHIFT(v)	(4 * (v))
    122
    123/* Constants */
    124#define MICFIL_OUTPUT_CHANNELS		8
    125#define MICFIL_FIFO_NUM			8
    126
    127#define FIFO_PTRWID			3
    128#define FIFO_LEN			BIT(FIFO_PTRWID)
    129
    130#define MICFIL_IRQ_LINES		2
    131#define MICFIL_MAX_RETRY		25
    132#define MICFIL_SLEEP_MIN		90000 /* in us */
    133#define MICFIL_SLEEP_MAX		100000 /* in us */
    134#define MICFIL_DMA_MAXBURST_RX		6
    135
    136#endif /* _FSL_MICFIL_H */