cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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skl-ssp-clk.h (2382B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  skl-ssp-clk.h - Skylake ssp clock information and ipc structure
      4 *
      5 *  Copyright (C) 2017 Intel Corp
      6 *  Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
      7 *  Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
      8 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      9 *
     10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     11 */
     12
     13#ifndef SOUND_SOC_SKL_SSP_CLK_H
     14#define SOUND_SOC_SKL_SSP_CLK_H
     15
     16#define SKL_MAX_SSP		6
     17/* xtal/cardinal/pll, parent of ssp clocks and mclk */
     18#define SKL_MAX_CLK_SRC		3
     19#define SKL_MAX_SSP_CLK_TYPES	3 /* mclk, sclk, sclkfs */
     20
     21#define SKL_MAX_CLK_CNT		(SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
     22
     23/* Max number of configurations supported for each clock */
     24#define SKL_MAX_CLK_RATES	10
     25
     26#define SKL_SCLK_OFS		SKL_MAX_SSP
     27#define SKL_SCLKFS_OFS		(SKL_SCLK_OFS + SKL_MAX_SSP)
     28
     29enum skl_clk_type {
     30	SKL_MCLK,
     31	SKL_SCLK,
     32	SKL_SCLK_FS,
     33};
     34
     35enum skl_clk_src_type {
     36	SKL_XTAL,
     37	SKL_CARDINAL,
     38	SKL_PLL,
     39};
     40
     41struct skl_clk_parent_src {
     42	u8 clk_id;
     43	const char *name;
     44	unsigned long rate;
     45	const char *parent_name;
     46};
     47
     48struct skl_tlv_hdr {
     49	u32 type;
     50	u32 size;
     51};
     52
     53struct skl_dmactrl_mclk_cfg {
     54	struct skl_tlv_hdr hdr;
     55	/* DMA Clk TLV params */
     56	u32 clk_warm_up:16;
     57	u32 mclk:1;
     58	u32 warm_up_over:1;
     59	u32 rsvd0:14;
     60	u32 clk_stop_delay:16;
     61	u32 keep_running:1;
     62	u32 clk_stop_over:1;
     63	u32 rsvd1:14;
     64};
     65
     66struct skl_dmactrl_sclkfs_cfg {
     67	struct skl_tlv_hdr hdr;
     68	/* DMA SClk&FS  TLV params */
     69	u32 sampling_frequency;
     70	u32 bit_depth;
     71	u32 channel_map;
     72	u32 channel_config;
     73	u32 interleaving_style;
     74	u32 number_of_channels : 8;
     75	u32 valid_bit_depth : 8;
     76	u32 sample_type : 8;
     77	u32 reserved : 8;
     78};
     79
     80union skl_clk_ctrl_ipc {
     81	struct skl_dmactrl_mclk_cfg mclk;
     82	struct skl_dmactrl_sclkfs_cfg sclk_fs;
     83};
     84
     85struct skl_clk_rate_cfg_table {
     86	unsigned long rate;
     87	union skl_clk_ctrl_ipc dma_ctl_ipc;
     88	void *config;
     89};
     90
     91/*
     92 * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
     93 * all possible clocks ssp can generate for that platform.
     94 */
     95struct skl_ssp_clk {
     96	const char *name;
     97	const char *parent_name;
     98	struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
     99};
    100
    101struct skl_clk_pdata {
    102	struct skl_clk_parent_src *parent_clks;
    103	int num_clks;
    104	struct skl_ssp_clk *ssp_clks;
    105	void *pvt_data;
    106};
    107
    108#endif /* SOUND_SOC_SKL_SSP_CLK_H */