lpass-ipq806x.c (5294B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-ipq806x.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 * Splited out the IPQ8064 soc specific from lpass-cpu.c 7 */ 8 9#include <linux/clk.h> 10#include <linux/device.h> 11#include <linux/err.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/platform_device.h> 16#include <sound/pcm.h> 17#include <sound/soc.h> 18#include <sound/soc-dai.h> 19 20#include "lpass-lpaif-reg.h" 21#include "lpass.h" 22 23enum lpaif_i2s_ports { 24 IPQ806X_LPAIF_I2S_PORT_CODEC_SPK, 25 IPQ806X_LPAIF_I2S_PORT_CODEC_MIC, 26 IPQ806X_LPAIF_I2S_PORT_SEC_SPK, 27 IPQ806X_LPAIF_I2S_PORT_SEC_MIC, 28 IPQ806X_LPAIF_I2S_PORT_MI2S, 29}; 30 31enum lpaif_dma_channels { 32 IPQ806X_LPAIF_RDMA_CHAN_MI2S, 33 IPQ806X_LPAIF_RDMA_CHAN_PCM0, 34 IPQ806X_LPAIF_RDMA_CHAN_PCM1, 35}; 36 37static struct snd_soc_dai_driver ipq806x_lpass_cpu_dai_driver = { 38 .id = IPQ806X_LPAIF_I2S_PORT_MI2S, 39 .playback = { 40 .stream_name = "lpass-cpu-playback", 41 .formats = SNDRV_PCM_FMTBIT_S16 | 42 SNDRV_PCM_FMTBIT_S24 | 43 SNDRV_PCM_FMTBIT_S32, 44 .rates = SNDRV_PCM_RATE_8000 | 45 SNDRV_PCM_RATE_16000 | 46 SNDRV_PCM_RATE_32000 | 47 SNDRV_PCM_RATE_48000 | 48 SNDRV_PCM_RATE_96000, 49 .rate_min = 8000, 50 .rate_max = 96000, 51 .channels_min = 1, 52 .channels_max = 8, 53 }, 54 .probe = &asoc_qcom_lpass_cpu_dai_probe, 55 .ops = &asoc_qcom_lpass_cpu_dai_ops, 56}; 57 58static int ipq806x_lpass_init(struct platform_device *pdev) 59{ 60 struct lpass_data *drvdata = platform_get_drvdata(pdev); 61 struct device *dev = &pdev->dev; 62 int ret; 63 64 drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk"); 65 if (IS_ERR(drvdata->ahbix_clk)) { 66 dev_err(dev, "error getting ahbix-clk: %ld\n", 67 PTR_ERR(drvdata->ahbix_clk)); 68 ret = PTR_ERR(drvdata->ahbix_clk); 69 goto err_ahbix_clk; 70 } 71 72 ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY); 73 if (ret) { 74 dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret); 75 goto err_ahbix_clk; 76 } 77 dev_dbg(dev, "set ahbix_clk rate to %lu\n", 78 clk_get_rate(drvdata->ahbix_clk)); 79 80 ret = clk_prepare_enable(drvdata->ahbix_clk); 81 if (ret) { 82 dev_err(dev, "error enabling ahbix_clk: %d\n", ret); 83 goto err_ahbix_clk; 84 } 85 86err_ahbix_clk: 87 return ret; 88} 89 90static int ipq806x_lpass_exit(struct platform_device *pdev) 91{ 92 struct lpass_data *drvdata = platform_get_drvdata(pdev); 93 94 clk_disable_unprepare(drvdata->ahbix_clk); 95 96 return 0; 97} 98 99static int ipq806x_lpass_alloc_dma_channel(struct lpass_data *drvdata, int dir, unsigned int dai_id) 100{ 101 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 102 return IPQ806X_LPAIF_RDMA_CHAN_MI2S; 103 else /* Capture currently not implemented */ 104 return -EINVAL; 105} 106 107static int ipq806x_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id) 108{ 109 return 0; 110} 111 112static struct lpass_variant ipq806x_data = { 113 .i2sctrl_reg_base = 0x0010, 114 .i2sctrl_reg_stride = 0x04, 115 .i2s_ports = 5, 116 .irq_reg_base = 0x3000, 117 .irq_reg_stride = 0x1000, 118 .irq_ports = 3, 119 .rdma_reg_base = 0x6000, 120 .rdma_reg_stride = 0x1000, 121 .rdma_channels = 4, 122 .wrdma_reg_base = 0xB000, 123 .wrdma_reg_stride = 0x1000, 124 .wrdma_channel_start = 5, 125 .wrdma_channels = 4, 126 .loopback = REG_FIELD_ID(0x0010, 15, 15, 5, 0x4), 127 .spken = REG_FIELD_ID(0x0010, 14, 14, 5, 0x4), 128 .spkmode = REG_FIELD_ID(0x0010, 10, 13, 5, 0x4), 129 .spkmono = REG_FIELD_ID(0x0010, 9, 9, 5, 0x4), 130 .micen = REG_FIELD_ID(0x0010, 8, 8, 5, 0x4), 131 .micmode = REG_FIELD_ID(0x0010, 4, 7, 5, 0x4), 132 .micmono = REG_FIELD_ID(0x0010, 3, 3, 5, 0x4), 133 .wssrc = REG_FIELD_ID(0x0010, 2, 2, 5, 0x4), 134 .bitwidth = REG_FIELD_ID(0x0010, 0, 1, 5, 0x4), 135 136 .rdma_dyncclk = REG_FIELD_ID(0x6000, 12, 12, 4, 0x1000), 137 .rdma_bursten = REG_FIELD_ID(0x6000, 11, 11, 4, 0x1000), 138 .rdma_wpscnt = REG_FIELD_ID(0x6000, 8, 10, 4, 0x1000), 139 .rdma_intf = REG_FIELD_ID(0x6000, 4, 7, 4, 0x1000), 140 .rdma_fifowm = REG_FIELD_ID(0x6000, 1, 3, 4, 0x1000), 141 .rdma_enable = REG_FIELD_ID(0x6000, 0, 0, 4, 0x1000), 142 143 .wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 4, 0x1000), 144 .wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 4, 0x1000), 145 .wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 4, 0x1000), 146 .wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 4, 0x1000), 147 .wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 4, 0x1000), 148 .wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 4, 0x1000), 149 150 .dai_driver = &ipq806x_lpass_cpu_dai_driver, 151 .num_dai = 1, 152 .dai_osr_clk_names = (const char *[]) { 153 "mi2s-osr-clk", 154 }, 155 .dai_bit_clk_names = (const char *[]) { 156 "mi2s-bit-clk", 157 }, 158 .init = ipq806x_lpass_init, 159 .exit = ipq806x_lpass_exit, 160 .alloc_dma_channel = ipq806x_lpass_alloc_dma_channel, 161 .free_dma_channel = ipq806x_lpass_free_dma_channel, 162}; 163 164static const struct of_device_id ipq806x_lpass_cpu_device_id[] __maybe_unused = { 165 { .compatible = "qcom,lpass-cpu", .data = &ipq806x_data }, 166 {} 167}; 168MODULE_DEVICE_TABLE(of, ipq806x_lpass_cpu_device_id); 169 170static struct platform_driver ipq806x_lpass_cpu_platform_driver = { 171 .driver = { 172 .name = "lpass-cpu", 173 .of_match_table = of_match_ptr(ipq806x_lpass_cpu_device_id), 174 }, 175 .probe = asoc_qcom_lpass_cpu_platform_probe, 176 .remove = asoc_qcom_lpass_cpu_platform_remove, 177}; 178module_platform_driver(ipq806x_lpass_cpu_platform_driver); 179 180MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 181MODULE_LICENSE("GPL v2");