acp-dsp-offset.h (2700B)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11#ifndef _ACP_DSP_IP_OFFSET_H 12#define _ACP_DSP_IP_OFFSET_H 13 14/* Registers from ACP_DMA_0 block */ 15#define ACP_DMA_CNTL_0 0x00 16#define ACP_DMA_DSCR_STRT_IDX_0 0x20 17#define ACP_DMA_DSCR_CNT_0 0x40 18#define ACP_DMA_PRIO_0 0x60 19#define ACP_DMA_CUR_DSCR_0 0x80 20#define ACP_DMA_ERR_STS_0 0xC0 21#define ACP_DMA_DESC_BASE_ADDR 0xE0 22#define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4 23#define ACP_DMA_CH_STS 0xE8 24#define ACP_DMA_CH_GROUP 0xEC 25#define ACP_DMA_CH_RST_STS 0xF0 26 27/* Registers from ACP_DSP_0 block */ 28#define ACP_DSP0_RUNSTALL 0x414 29 30/* Registers from ACP_AXI2AXIATU block */ 31#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC00 32#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC04 33#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC08 34#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C 35#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0xC10 36#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0xC14 37#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0xC18 38#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0xC1C 39#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20 40#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24 41#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0xC28 42#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0xC2C 43#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0xC30 44#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0xC34 45#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0xC38 46#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0xC3C 47#define ACPAXI2AXI_ATU_CTRL 0xC40 48#define ACP_SOFT_RESET 0x1000 49 50#define ACP_I2S_PIN_CONFIG 0x1400 51 52/* Registers from ACP_PGFSM block */ 53#define ACP_PGFSM_CONTROL 0x141C 54#define ACP_PGFSM_STATUS 0x1420 55 56/* Registers from ACP_INTR block */ 57#define ACP_EXTERNAL_INTR_ENB 0x1800 58#define ACP_EXTERNAL_INTR_CNTL 0x1804 59#define ACP_EXTERNAL_INTR_STAT 0x1808 60#define ACP_DSP_SW_INTR_CNTL 0x1814 61#define ACP_DSP_SW_INTR_STAT 0x1818 62#define ACP_SW_INTR_TRIG 0x181C 63#define ACP_ERROR_STATUS 0x18C4 64#define ACP_AXI2DAGB_SEM_0 0x1880 65 66/* Registers from ACP_SHA block */ 67#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70 68#define ACP_SHA_DMA_CMD 0x1CB0 69#define ACP_SHA_MSG_LENGTH 0x1CB4 70#define ACP_SHA_DMA_STRT_ADDR 0x1CB8 71#define ACP_SHA_DMA_DESTINATION_ADDR 0x1CBC 72#define ACP_SHA_DMA_CMD_STS 0x1CC0 73#define ACP_SHA_DMA_ERR_STATUS 0x1CC4 74#define ACP_SHA_TRANSFER_BYTE_CNT 0x1CC8 75#define ACP_SHA_PSP_ACK 0x1C74 76 77#define ACP_SCRATCH_REG_0 0x10000 78 79#endif