cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pci-tng.c (6964B)


      1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
      2//
      3// This file is provided under a dual BSD/GPLv2 license.  When using or
      4// redistributing this file, you may do so under either license.
      5//
      6// Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
      7//
      8// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
      9//
     10
     11#include <linux/module.h>
     12#include <linux/pci.h>
     13#include <sound/soc-acpi.h>
     14#include <sound/soc-acpi-intel-match.h>
     15#include <sound/sof.h>
     16#include "../ops.h"
     17#include "atom.h"
     18#include "../sof-pci-dev.h"
     19#include "../sof-audio.h"
     20
     21/* platform specific devices */
     22#include "shim.h"
     23
     24static struct snd_soc_acpi_mach sof_tng_machines[] = {
     25	{
     26		.id = "INT343A",
     27		.drv_name = "edison",
     28		.sof_tplg_filename = "sof-byt.tplg",
     29	},
     30	{}
     31};
     32
     33static const struct snd_sof_debugfs_map tng_debugfs[] = {
     34	{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
     35	 SOF_DEBUGFS_ACCESS_ALWAYS},
     36	{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
     37	 SOF_DEBUGFS_ACCESS_ALWAYS},
     38	{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
     39	 SOF_DEBUGFS_ACCESS_ALWAYS},
     40	{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
     41	 SOF_DEBUGFS_ACCESS_ALWAYS},
     42	{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
     43	 SOF_DEBUGFS_ACCESS_ALWAYS},
     44	{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
     45	 SOF_DEBUGFS_ACCESS_D0_ONLY},
     46	{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
     47	 SOF_DEBUGFS_ACCESS_D0_ONLY},
     48	{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
     49	 SOF_DEBUGFS_ACCESS_ALWAYS},
     50};
     51
     52static int tangier_pci_probe(struct snd_sof_dev *sdev)
     53{
     54	struct snd_sof_pdata *pdata = sdev->pdata;
     55	const struct sof_dev_desc *desc = pdata->desc;
     56	struct pci_dev *pci = to_pci_dev(sdev->dev);
     57	const struct sof_intel_dsp_desc *chip;
     58	u32 base, size;
     59	int ret;
     60
     61	chip = get_chip_info(sdev->pdata);
     62	if (!chip) {
     63		dev_err(sdev->dev, "error: no such device supported\n");
     64		return -EIO;
     65	}
     66
     67	sdev->num_cores = chip->cores_num;
     68
     69	/* DSP DMA can only access low 31 bits of host memory */
     70	ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
     71	if (ret < 0) {
     72		dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
     73		return ret;
     74	}
     75
     76	/* LPE base */
     77	base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
     78	size = pci_resource_len(pci, desc->resindex_lpe_base);
     79	if (size < PCI_BAR_SIZE) {
     80		dev_err(sdev->dev, "error: I/O region is too small.\n");
     81		return -ENODEV;
     82	}
     83
     84	dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
     85	sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
     86	if (!sdev->bar[DSP_BAR]) {
     87		dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
     88			base, size);
     89		return -ENODEV;
     90	}
     91	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
     92
     93	/* IMR base - optional */
     94	if (desc->resindex_imr_base == -1)
     95		goto irq;
     96
     97	base = pci_resource_start(pci, desc->resindex_imr_base);
     98	size = pci_resource_len(pci, desc->resindex_imr_base);
     99
    100	/* some BIOSes don't map IMR */
    101	if (base == 0x55aa55aa || base == 0x0) {
    102		dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
    103		goto irq;
    104	}
    105
    106	dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
    107	sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
    108	if (!sdev->bar[IMR_BAR]) {
    109		dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
    110			base, size);
    111		return -ENODEV;
    112	}
    113	dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
    114
    115irq:
    116	/* register our IRQ */
    117	sdev->ipc_irq = pci->irq;
    118	dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
    119	ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
    120					atom_irq_handler, atom_irq_thread,
    121					0, "AudioDSP", sdev);
    122	if (ret < 0) {
    123		dev_err(sdev->dev, "error: failed to register IRQ %d\n",
    124			sdev->ipc_irq);
    125		return ret;
    126	}
    127
    128	/* enable BUSY and disable DONE Interrupt by default */
    129	snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
    130				  SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
    131				  SHIM_IMRX_DONE);
    132
    133	/* set default mailbox offset for FW ready message */
    134	sdev->dsp_box.offset = MBOX_OFFSET;
    135
    136	return ret;
    137}
    138
    139struct snd_sof_dsp_ops sof_tng_ops = {
    140	/* device init */
    141	.probe		= tangier_pci_probe,
    142
    143	/* DSP core boot / reset */
    144	.run		= atom_run,
    145	.reset		= atom_reset,
    146
    147	/* Register IO */
    148	.write		= sof_io_write,
    149	.read		= sof_io_read,
    150	.write64	= sof_io_write64,
    151	.read64		= sof_io_read64,
    152
    153	/* Block IO */
    154	.block_read	= sof_block_read,
    155	.block_write	= sof_block_write,
    156
    157	/* Mailbox IO */
    158	.mailbox_read	= sof_mailbox_read,
    159	.mailbox_write	= sof_mailbox_write,
    160
    161	/* doorbell */
    162	.irq_handler	= atom_irq_handler,
    163	.irq_thread	= atom_irq_thread,
    164
    165	/* ipc */
    166	.send_msg	= atom_send_msg,
    167	.get_mailbox_offset = atom_get_mailbox_offset,
    168	.get_window_offset = atom_get_window_offset,
    169
    170	.ipc_msg_data	= sof_ipc_msg_data,
    171	.set_stream_data_offset = sof_set_stream_data_offset,
    172
    173	/* machine driver */
    174	.machine_select = atom_machine_select,
    175	.machine_register = sof_machine_register,
    176	.machine_unregister = sof_machine_unregister,
    177	.set_mach_params = atom_set_mach_params,
    178
    179	/* debug */
    180	.debug_map	= tng_debugfs,
    181	.debug_map_count	= ARRAY_SIZE(tng_debugfs),
    182	.dbg_dump	= atom_dump,
    183	.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
    184
    185	/* stream callbacks */
    186	.pcm_open	= sof_stream_pcm_open,
    187	.pcm_close	= sof_stream_pcm_close,
    188
    189	/*Firmware loading */
    190	.load_firmware	= snd_sof_load_firmware_memcpy,
    191
    192	/* DAI drivers */
    193	.drv = atom_dai,
    194	.num_drv = 3, /* we have only 3 SSPs on byt*/
    195
    196	/* ALSA HW info flags */
    197	.hw_info =	SNDRV_PCM_INFO_MMAP |
    198			SNDRV_PCM_INFO_MMAP_VALID |
    199			SNDRV_PCM_INFO_INTERLEAVED |
    200			SNDRV_PCM_INFO_PAUSE |
    201			SNDRV_PCM_INFO_BATCH,
    202
    203	.dsp_arch_ops = &sof_xtensa_arch_ops,
    204};
    205
    206const struct sof_intel_dsp_desc tng_chip_info = {
    207	.cores_num = 1,
    208	.host_managed_cores_mask = 1,
    209	.hw_ip_version = SOF_INTEL_TANGIER,
    210};
    211
    212static const struct sof_dev_desc tng_desc = {
    213	.machines		= sof_tng_machines,
    214	.resindex_lpe_base	= 3,	/* IRAM, but subtract IRAM offset */
    215	.resindex_pcicfg_base	= -1,
    216	.resindex_imr_base	= 0,
    217	.irqindex_host_ipc	= -1,
    218	.chip_info = &tng_chip_info,
    219	.ipc_supported_mask	= BIT(SOF_IPC),
    220	.ipc_default		= SOF_IPC,
    221	.default_fw_path = {
    222		[SOF_IPC] = "intel/sof",
    223	},
    224	.default_tplg_path = {
    225		[SOF_IPC] = "intel/sof-tplg",
    226	},
    227	.default_fw_filename = {
    228		[SOF_IPC] = "sof-byt.ri",
    229	},
    230	.nocodec_tplg_filename = "sof-byt.tplg",
    231	.ops = &sof_tng_ops,
    232};
    233
    234/* PCI IDs */
    235static const struct pci_device_id sof_pci_ids[] = {
    236	{ PCI_DEVICE(0x8086, 0x119a),
    237		.driver_data = (unsigned long)&tng_desc},
    238	{ 0, }
    239};
    240MODULE_DEVICE_TABLE(pci, sof_pci_ids);
    241
    242/* pci_driver definition */
    243static struct pci_driver snd_sof_pci_intel_tng_driver = {
    244	.name = "sof-audio-pci-intel-tng",
    245	.id_table = sof_pci_ids,
    246	.probe = sof_pci_probe,
    247	.remove = sof_pci_remove,
    248	.shutdown = sof_pci_shutdown,
    249	.driver = {
    250		.pm = &sof_pci_pm,
    251	},
    252};
    253module_pci_driver(snd_sof_pci_intel_tng_driver);
    254
    255MODULE_LICENSE("Dual BSD/GPL");
    256MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
    257MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
    258MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
    259MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);