cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spdif_out_regs.h (2169B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * SPEAr SPDIF OUT controller header file
      4 *
      5 * Copyright (ST) 2011 Vipin Kumar (vipin.kumar@st.com)
      6 */
      7
      8#ifndef SPDIF_OUT_REGS_H
      9#define SPDIF_OUT_REGS_H
     10
     11#define SPDIF_OUT_SOFT_RST	0x00
     12	#define SPDIF_OUT_RESET		(1 << 0)
     13#define SPDIF_OUT_FIFO_DATA	0x04
     14#define SPDIF_OUT_INT_STA	0x08
     15#define SPDIF_OUT_INT_STA_CLR	0x0C
     16	#define SPDIF_INT_UNDERFLOW	(1 << 0)
     17	#define SPDIF_INT_EODATA	(1 << 1)
     18	#define SPDIF_INT_EOBLOCK	(1 << 2)
     19	#define SPDIF_INT_EOLATENCY	(1 << 3)
     20	#define SPDIF_INT_EOPD_DATA	(1 << 4)
     21	#define SPDIF_INT_MEMFULLREAD	(1 << 5)
     22	#define SPDIF_INT_EOPD_PAUSE	(1 << 6)
     23
     24#define SPDIF_OUT_INT_EN	0x10
     25#define SPDIF_OUT_INT_EN_SET	0x14
     26#define SPDIF_OUT_INT_EN_CLR	0x18
     27#define SPDIF_OUT_CTRL		0x1C
     28	#define SPDIF_OPMODE_MASK	(7 << 0)
     29	#define SPDIF_OPMODE_OFF	(0 << 0)
     30	#define SPDIF_OPMODE_MUTE_PCM	(1 << 0)
     31	#define SPDIF_OPMODE_MUTE_PAUSE	(2 << 0)
     32	#define SPDIF_OPMODE_AUD_DATA	(3 << 0)
     33	#define SPDIF_OPMODE_ENCODE	(4 << 0)
     34	#define SPDIF_STATE_NORMAL	(1 << 3)
     35	#define SPDIF_DIVIDER_MASK	(0xff << 5)
     36	#define SPDIF_DIVIDER_SHIFT	(5)
     37	#define SPDIF_SAMPLEREAD_MASK	(0x1ffff << 15)
     38	#define SPDIF_SAMPLEREAD_SHIFT	(15)
     39#define SPDIF_OUT_STA		0x20
     40#define SPDIF_OUT_PA_PB		0x24
     41#define SPDIF_OUT_PC_PD		0x28
     42#define SPDIF_OUT_CL1		0x2C
     43#define SPDIF_OUT_CR1		0x30
     44#define SPDIF_OUT_CL2_CR2_UV	0x34
     45#define SPDIF_OUT_PAUSE_LAT	0x38
     46#define SPDIF_OUT_FRMLEN_BRST	0x3C
     47#define SPDIF_OUT_CFG		0x40
     48	#define SPDIF_OUT_MEMFMT_16_0	(0 << 5)
     49	#define SPDIF_OUT_MEMFMT_16_16	(1 << 5)
     50	#define SPDIF_OUT_VALID_DMA	(0 << 3)
     51	#define SPDIF_OUT_VALID_HW	(1 << 3)
     52	#define SPDIF_OUT_USER_DMA	(0 << 2)
     53	#define SPDIF_OUT_USER_HW	(1 << 2)
     54	#define SPDIF_OUT_CHNLSTA_DMA	(0 << 1)
     55	#define SPDIF_OUT_CHNLSTA_HW	(1 << 1)
     56	#define SPDIF_OUT_PARITY_HW	(0 << 0)
     57	#define SPDIF_OUT_PARITY_DMA	(1 << 0)
     58	#define SPDIF_OUT_FDMA_TRIG_2	(2 << 8)
     59	#define SPDIF_OUT_FDMA_TRIG_6	(6 << 8)
     60	#define SPDIF_OUT_FDMA_TRIG_8	(8 << 8)
     61	#define SPDIF_OUT_FDMA_TRIG_10	(10 << 8)
     62	#define SPDIF_OUT_FDMA_TRIG_12	(12 << 8)
     63	#define SPDIF_OUT_FDMA_TRIG_16	(16 << 8)
     64	#define SPDIF_OUT_FDMA_TRIG_18	(18 << 8)
     65
     66#endif /* SPDIF_OUT_REGS_H */