tegra186_asrc.h (4583B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * tegra186_asrc.h - Definitions for Tegra186 ASRC driver 4 * 5 * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. 6 * 7 */ 8 9#ifndef __TEGRA186_ASRC_H__ 10#define __TEGRA186_ASRC_H__ 11 12/* ASRC stream related offset */ 13#define TEGRA186_ASRC_CFG 0x0 14#define TEGRA186_ASRC_RATIO_INT_PART 0x4 15#define TEGRA186_ASRC_RATIO_FRAC_PART 0x8 16#define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc 17#define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x10 18#define TEGRA186_ASRC_TX_THRESHOLD 0x14 19#define TEGRA186_ASRC_RX_THRESHOLD 0x18 20#define TEGRA186_ASRC_RATIO_COMP 0x1c 21#define TEGRA186_ASRC_RX_STATUS 0x20 22#define TEGRA186_ASRC_RX_CIF_CTRL 0x24 23#define TEGRA186_ASRC_TX_STATUS 0x2c 24#define TEGRA186_ASRC_TX_CIF_CTRL 0x30 25#define TEGRA186_ASRC_ENABLE 0x38 26#define TEGRA186_ASRC_SOFT_RESET 0x3c 27#define TEGRA186_ASRC_STATUS 0x4c 28#define TEGRA186_ASRC_STATEBUF_ADDR 0x5c 29#define TEGRA186_ASRC_STATEBUF_CFG 0x60 30#define TEGRA186_ASRC_INSAMPLEBUF_ADDR 0x64 31#define TEGRA186_ASRC_INSAMPLEBUF_CFG 0x68 32#define TEGRA186_ASRC_OUTSAMPLEBUF_ADDR 0x6c 33#define TEGRA186_ASRC_OUTSAMPLEBUF_CFG 0x70 34 35/* ASRC Global registers offset */ 36#define TEGRA186_ASRC_GLOBAL_ENB 0x2f4 37#define TEGRA186_ASRC_GLOBAL_SOFT_RESET 0x2f8 38#define TEGRA186_ASRC_GLOBAL_CG 0x2fc 39#define TEGRA186_ASRC_GLOBAL_CFG 0x300 40#define TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR 0x304 41#define TEGRA186_ASRC_GLOBAL_SCRATCH_CFG 0x308 42#define TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL 0x30c 43#define TEGRA186_ASRC_RATIO_UPD_RX_STATUS 0x310 44#define TEGRA186_ASRC_GLOBAL_STATUS 0x314 45#define TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS 0x318 46#define TEGRA186_ASRC_GLOBAL_INT_STATUS 0x324 47#define TEGRA186_ASRC_GLOBAL_INT_MASK 0x328 48#define TEGRA186_ASRC_GLOBAL_INT_SET 0x32c 49#define TEGRA186_ASRC_GLOBAL_INT_CLEAR 0x330 50#define TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG 0x334 51#define TEGRA186_ASRC_GLOBAL_APR_CTRL 0x1000 52#define TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL 0x1004 53#define TEGRA186_ASRC_GLOBAL_DISARM_APR 0x1008 54#define TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL 0x100c 55#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS 0x1010 56#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL 0x1014 57#define TEGRA186_ASRC_CYA 0x1018 58 59#define TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE 0xaaaa 60#define TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG 0x00201002 61#define TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG 0x00201002 62 63#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_28BIT_PRECISION 0 64#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_32BIT_PRECISION 1 65 66#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT 31 67#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT) 68#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT) 69#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE (0 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT) 70 71#define TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT 0 72#define TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK (1 << TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT) 73 74#define TEGRA186_ASRC_STREAM_EN_SHIFT 0 75#define TEGRA186_ASRC_STREAM_EN (1 << TEGRA186_ASRC_STREAM_EN_SHIFT) 76#define TEGRA186_ASRC_GLOBAL_EN_SHIFT 0 77#define TEGRA186_ASRC_GLOBAL_EN (1 << TEGRA186_ASRC_GLOBAL_EN_SHIFT) 78 79#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT 0 80#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT) 81#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT 0 82#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT) 83#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT 0 84#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT) 85 86#define TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK 0x1f 87#define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK 0xffffffff 88 89#define TEGRA186_ASRC_STREAM_STRIDE 0x80 90#define TEGRA186_ASRC_STREAM_MAX 0x6 91#define TEGRA186_ASRC_STREAM_LIMIT 0x2f0 92 93#define TEGRA186_ASRC_RATIO_SOURCE_ARAD 0x0 94#define TEGRA186_ASRC_RATIO_SOURCE_SW 0x1 95 96#define TEGRA186_ASRC_ARAM_START_ADDR 0x3f800000 97 98struct tegra186_asrc_lane { 99 unsigned int int_part; 100 unsigned int frac_part; 101 unsigned int ratio_source; 102 unsigned int hwcomp_disable; 103 unsigned int input_thresh; 104 unsigned int output_thresh; 105}; 106 107struct tegra186_asrc { 108 struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX]; 109 struct regmap *regmap; 110}; 111 112#endif