cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra20_das.h (4011B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * tegra20_das.h - Definitions for Tegra20 DAS driver
      4 *
      5 * Author: Stephen Warren <swarren@nvidia.com>
      6 * Copyright (C) 2010,2012 - NVIDIA, Inc.
      7 */
      8
      9#ifndef __TEGRA20_DAS_H__
     10#define __TEGRA20_DAS_H__
     11
     12/* Register TEGRA20_DAS_DAP_CTRL_SEL */
     13#define TEGRA20_DAS_DAP_CTRL_SEL			0x00
     14#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT			5
     15#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE			4
     16#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P		31
     17#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S		1
     18#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P	30
     19#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S	1
     20#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P	29
     21#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S	1
     22#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P		0
     23#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S		5
     24
     25/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
     26#define TEGRA20_DAS_DAP_SEL_DAC1	0
     27#define TEGRA20_DAS_DAP_SEL_DAC2	1
     28#define TEGRA20_DAS_DAP_SEL_DAC3	2
     29#define TEGRA20_DAS_DAP_SEL_DAP1	16
     30#define TEGRA20_DAS_DAP_SEL_DAP2	17
     31#define TEGRA20_DAS_DAP_SEL_DAP3	18
     32#define TEGRA20_DAS_DAP_SEL_DAP4	19
     33#define TEGRA20_DAS_DAP_SEL_DAP5	20
     34
     35/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
     36#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL			0x40
     37#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT		3
     38#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE		4
     39#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P	28
     40#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S	4
     41#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P	24
     42#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S	4
     43#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P	0
     44#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S	4
     45
     46/*
     47 * Values for:
     48 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
     49 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
     50 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
     51 */
     52#define TEGRA20_DAS_DAC_SEL_DAP1	0
     53#define TEGRA20_DAS_DAC_SEL_DAP2	1
     54#define TEGRA20_DAS_DAC_SEL_DAP3	2
     55#define TEGRA20_DAS_DAC_SEL_DAP4	3
     56#define TEGRA20_DAS_DAC_SEL_DAP5	4
     57
     58/*
     59 * Names/IDs of the DACs/DAPs.
     60 */
     61
     62#define TEGRA20_DAS_DAP_ID_1 0
     63#define TEGRA20_DAS_DAP_ID_2 1
     64#define TEGRA20_DAS_DAP_ID_3 2
     65#define TEGRA20_DAS_DAP_ID_4 3
     66#define TEGRA20_DAS_DAP_ID_5 4
     67
     68#define TEGRA20_DAS_DAC_ID_1 0
     69#define TEGRA20_DAS_DAC_ID_2 1
     70#define TEGRA20_DAS_DAC_ID_3 2
     71
     72struct tegra20_das {
     73	struct device *dev;
     74	struct regmap *regmap;
     75};
     76
     77/*
     78 * Terminology:
     79 * DAS: Digital audio switch (HW module controlled by this driver)
     80 * DAP: Digital audio port (port/pins on Tegra device)
     81 * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
     82 *
     83 * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
     84 * DAC, or another DAP. When DAPs are connected, one must be the master and
     85 * one the slave. Each DAC allows selection of a specific DAP for input, to
     86 * cater for the case where N DAPs are connected to 1 DAC for broadcast
     87 * output.
     88 *
     89 * This driver is dumb; no attempt is made to ensure that a valid routing
     90 * configuration is programmed.
     91 */
     92
     93/*
     94 * Connect a DAP to a DAC
     95 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
     96 * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
     97 */
     98extern int tegra20_das_connect_dap_to_dac(int dap, int dac);
     99
    100/*
    101 * Connect a DAP to another DAP
    102 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
    103 * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
    104 * master: Is this DAP the master (1) or slave (0)
    105 * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
    106 * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
    107 */
    108extern int tegra20_das_connect_dap_to_dap(int dap, int otherdap,
    109					  int master, int sdata1rx,
    110					  int sdata2rx);
    111
    112/*
    113 * Connect a DAC's input to a DAP
    114 * (DAC outputs are selected by the DAP)
    115 * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
    116 * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
    117 */
    118extern int tegra20_das_connect_dac_to_dap(int dac, int dap);
    119
    120#endif