tegra210_adx.h (2559B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * tegra210_adx.h - Definitions for Tegra210 ADX driver 4 * 5 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. 6 * 7 */ 8 9#ifndef __TEGRA210_ADX_H__ 10#define __TEGRA210_ADX_H__ 11 12/* Register offsets from TEGRA210_ADX*_BASE */ 13#define TEGRA210_ADX_RX_STATUS 0x0c 14#define TEGRA210_ADX_RX_INT_STATUS 0x10 15#define TEGRA210_ADX_RX_INT_MASK 0x14 16#define TEGRA210_ADX_RX_INT_SET 0x18 17#define TEGRA210_ADX_RX_INT_CLEAR 0x1c 18#define TEGRA210_ADX_RX_CIF_CTRL 0x20 19#define TEGRA210_ADX_TX_STATUS 0x4c 20#define TEGRA210_ADX_TX_INT_STATUS 0x50 21#define TEGRA210_ADX_TX_INT_MASK 0x54 22#define TEGRA210_ADX_TX_INT_SET 0x58 23#define TEGRA210_ADX_TX_INT_CLEAR 0x5c 24#define TEGRA210_ADX_TX1_CIF_CTRL 0x60 25#define TEGRA210_ADX_TX2_CIF_CTRL 0x64 26#define TEGRA210_ADX_TX3_CIF_CTRL 0x68 27#define TEGRA210_ADX_TX4_CIF_CTRL 0x6c 28#define TEGRA210_ADX_ENABLE 0x80 29#define TEGRA210_ADX_SOFT_RESET 0x84 30#define TEGRA210_ADX_CG 0x88 31#define TEGRA210_ADX_STATUS 0x8c 32#define TEGRA210_ADX_INT_STATUS 0x90 33#define TEGRA210_ADX_CTRL 0xa4 34#define TEGRA210_ADX_IN_BYTE_EN0 0xa8 35#define TEGRA210_ADX_IN_BYTE_EN1 0xac 36#define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 37#define TEGRA210_ADX_CFG_RAM_DATA 0xbc 38 39/* Fields in TEGRA210_ADX_ENABLE */ 40#define TEGRA210_ADX_ENABLE_SHIFT 0 41 42/* Fields in TEGRA210_ADX_CFG_RAM_CTRL */ 43#define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0 44 45#define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14 46#define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) 47 48#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 49#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) 50 51#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 52#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) 53 54/* Fields in TEGRA210_ADX_SOFT_RESET */ 55#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 56#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 57#define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 58#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 59 60#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 61#define TEGRA210_ADX_RAM_DEPTH 16 62#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 63#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 64#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 65 66struct tegra210_adx { 67 struct regmap *regmap; 68 unsigned int map[TEGRA210_ADX_RAM_DEPTH]; 69 unsigned int byte_mask[2]; 70}; 71 72#endif