cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra210_dmic.h (2286B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * tegra210_dmic.h - Definitions for Tegra210 DMIC driver
      4 *
      5 * Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
      6 *
      7 */
      8
      9#ifndef __TEGRA210_DMIC_H__
     10#define __TEGRA210_DMIC_H__
     11
     12/* Register offsets from DMIC BASE */
     13#define TEGRA210_DMIC_TX_STATUS				0x0c
     14#define TEGRA210_DMIC_TX_INT_STATUS			0x10
     15#define TEGRA210_DMIC_TX_INT_MASK			0x14
     16#define TEGRA210_DMIC_TX_INT_SET			0x18
     17#define TEGRA210_DMIC_TX_INT_CLEAR			0x1c
     18#define TEGRA210_DMIC_TX_CIF_CTRL			0x20
     19#define TEGRA210_DMIC_ENABLE				0x40
     20#define TEGRA210_DMIC_SOFT_RESET			0x44
     21#define TEGRA210_DMIC_CG				0x48
     22#define TEGRA210_DMIC_STATUS				0x4c
     23#define TEGRA210_DMIC_INT_STATUS			0x50
     24#define TEGRA210_DMIC_CTRL				0x64
     25#define TEGRA210_DMIC_DBG_CTRL				0x70
     26#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4		0x88
     27#define TEGRA210_DMIC_LP_FILTER_GAIN			0x8c
     28#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0		0x90
     29#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1		0x94
     30#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2		0x98
     31#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3		0x9c
     32#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4		0xa0
     33#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0		0xa4
     34#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1		0xa8
     35#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2		0xac
     36#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3		0xb0
     37#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4		0xb4
     38
     39/* Fields in TEGRA210_DMIC_CTRL */
     40#define CH_SEL_SHIFT					8
     41#define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK		(0x3 << CH_SEL_SHIFT)
     42#define LRSEL_POL_SHIFT					4
     43#define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK		(0x1 << LRSEL_POL_SHIFT)
     44#define OSR_SHIFT					0
     45#define TEGRA210_DMIC_CTRL_OSR_MASK			(0x3 << OSR_SHIFT)
     46
     47#define DMIC_OSR_FACTOR					64
     48
     49#define DEFAULT_GAIN_Q23				0x800000
     50
     51/* Max boost gain factor used for mixer control */
     52#define MAX_BOOST_GAIN 25599
     53
     54enum tegra_dmic_ch_select {
     55	DMIC_CH_SELECT_LEFT,
     56	DMIC_CH_SELECT_RIGHT,
     57	DMIC_CH_SELECT_STEREO,
     58};
     59
     60enum tegra_dmic_osr {
     61	DMIC_OSR_64,
     62	DMIC_OSR_128,
     63	DMIC_OSR_256,
     64};
     65
     66enum tegra_dmic_lrsel {
     67	DMIC_LRSEL_LEFT,
     68	DMIC_LRSEL_RIGHT,
     69};
     70
     71struct tegra210_dmic {
     72	struct clk *clk_dmic;
     73	struct regmap *regmap;
     74	unsigned int mono_to_stereo;
     75	unsigned int stereo_to_mono;
     76	unsigned int boost_gain;
     77	unsigned int ch_select;
     78	unsigned int osr_val;
     79	unsigned int lrsel;
     80};
     81
     82#endif