cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

tegra210_mixer.h (4103B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * tegra210_mixer.h - Definitions for Tegra210 MIXER driver
      4 *
      5 * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
      6 *
      7 */
      8
      9#ifndef __TEGRA210_MIXER_H__
     10#define __TEGRA210_MIXER_H__
     11
     12/* XBAR_RX related MIXER offsets */
     13#define TEGRA210_MIXER_RX1_SOFT_RESET	0x04
     14#define TEGRA210_MIXER_RX1_STATUS	0x10
     15#define TEGRA210_MIXER_RX1_CIF_CTRL	0x24
     16#define TEGRA210_MIXER_RX1_CTRL		0x28
     17#define TEGRA210_MIXER_RX1_PEAK_CTRL	0x2c
     18#define TEGRA210_MIXER_RX1_SAMPLE_COUNT	0x30
     19
     20/* XBAR_TX related MIXER offsets */
     21#define TEGRA210_MIXER_TX1_ENABLE	0x280
     22#define TEGRA210_MIXER_TX1_SOFT_RESET	0x284
     23#define TEGRA210_MIXER_TX1_STATUS	0x290
     24#define TEGRA210_MIXER_TX1_INT_STATUS	0x294
     25#define TEGRA210_MIXER_TX1_INT_MASK	0x298
     26#define TEGRA210_MIXER_TX1_INT_SET	0x29c
     27#define TEGRA210_MIXER_TX1_INT_CLEAR	0x2a0
     28#define TEGRA210_MIXER_TX1_CIF_CTRL	0x2a4
     29#define TEGRA210_MIXER_TX1_ADDER_CONFIG	0x2a8
     30
     31/* MIXER related offsets */
     32#define TEGRA210_MIXER_ENABLE			0x400
     33#define TEGRA210_MIXER_SOFT_RESET		0x404
     34#define TEGRA210_MIXER_CG			0x408
     35#define TEGRA210_MIXER_STATUS			0x410
     36#define TEGRA210_MIXER_INT_STATUS		0x414
     37#define TEGRA210_MIXER_GAIN_CFG_RAM_CTRL	0x42c
     38#define TEGRA210_MIXER_GAIN_CFG_RAM_DATA	0x430
     39#define TEGRA210_MIXER_PEAKM_RAM_CTRL		0x434
     40#define TEGRA210_MIXER_PEAKM_RAM_DATA		0x438
     41#define TEGRA210_MIXER_CTRL			0x43c
     42
     43#define TEGRA210_MIXER_TX2_ADDER_CONFIG	(TEGRA210_MIXER_TX1_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
     44#define TEGRA210_MIXER_TX3_ADDER_CONFIG	(TEGRA210_MIXER_TX2_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
     45#define TEGRA210_MIXER_TX4_ADDER_CONFIG	(TEGRA210_MIXER_TX3_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
     46#define TEGRA210_MIXER_TX5_ADDER_CONFIG	(TEGRA210_MIXER_TX4_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
     47
     48#define TEGRA210_MIXER_TX2_ENABLE	(TEGRA210_MIXER_TX1_ENABLE + TEGRA210_MIXER_REG_STRIDE)
     49#define TEGRA210_MIXER_TX3_ENABLE	(TEGRA210_MIXER_TX2_ENABLE + TEGRA210_MIXER_REG_STRIDE)
     50#define TEGRA210_MIXER_TX4_ENABLE	(TEGRA210_MIXER_TX3_ENABLE + TEGRA210_MIXER_REG_STRIDE)
     51#define TEGRA210_MIXER_TX5_ENABLE	(TEGRA210_MIXER_TX4_ENABLE + TEGRA210_MIXER_REG_STRIDE)
     52
     53/* Fields in TEGRA210_MIXER_ENABLE */
     54#define TEGRA210_MIXER_ENABLE_SHIFT	0
     55#define TEGRA210_MIXER_ENABLE_MASK	(1 << TEGRA210_MIXER_ENABLE_SHIFT)
     56#define TEGRA210_MIXER_EN		(1 << TEGRA210_MIXER_ENABLE_SHIFT)
     57
     58/* Fields in TEGRA210_MIXER_GAIN_CFG_RAM_CTRL */
     59#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0		0x0
     60#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE		0x10
     61
     62#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT		14
     63#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_MASK		(1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT)
     64#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_WRITE		(1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT)
     65
     66#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT	13
     67#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_MASK	(1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT)
     68#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN	(1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT)
     69
     70#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT	12
     71#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_MASK	(1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT)
     72#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN	(1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT)
     73
     74#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT		0
     75#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_MASK		(0x1ff << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT)
     76
     77#define TEGRA210_MIXER_REG_STRIDE	0x40
     78#define TEGRA210_MIXER_RX_MAX		10
     79#define TEGRA210_MIXER_RX_LIMIT		(TEGRA210_MIXER_RX_MAX * TEGRA210_MIXER_REG_STRIDE)
     80#define TEGRA210_MIXER_TX_MAX		5
     81#define TEGRA210_MIXER_TX_LIMIT		(TEGRA210_MIXER_RX_LIMIT + (TEGRA210_MIXER_TX_MAX * TEGRA210_MIXER_REG_STRIDE))
     82
     83#define REG_CFG_DONE_TRIGGER	0xf
     84#define VAL_CFG_DONE_TRIGGER	0x1
     85
     86#define NUM_GAIN_POLY_COEFFS 9
     87#define NUM_DURATION_PARMS 4
     88
     89struct tegra210_mixer_gain_params {
     90	int poly_coeff[NUM_GAIN_POLY_COEFFS];
     91	int gain_value;
     92	int duration[NUM_DURATION_PARMS];
     93};
     94
     95struct tegra210_mixer {
     96	int gain_value[TEGRA210_MIXER_RX_MAX];
     97	struct regmap *regmap;
     98};
     99
    100#endif