msr-index.h (39743B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14/* x86-64 specific MSRs */ 15#define MSR_EFER 0xc0000080 /* extended feature register */ 16#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25/* EFER bits: */ 26#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27#define _EFER_LME 8 /* Long mode enable */ 28#define _EFER_LMA 10 /* Long mode active (read-only) */ 29#define _EFER_NX 11 /* No execute enable */ 30#define _EFER_SVME 12 /* Enable virtualization */ 31#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34#define EFER_SCE (1<<_EFER_SCE) 35#define EFER_LME (1<<_EFER_LME) 36#define EFER_LMA (1<<_EFER_LMA) 37#define EFER_NX (1<<_EFER_NX) 38#define EFER_SVME (1<<_EFER_SVME) 39#define EFER_LMSLE (1<<_EFER_LMSLE) 40#define EFER_FFXSR (1<<_EFER_FFXSR) 41 42/* Intel MSRs. Some also available on other CPUs */ 43 44#define MSR_TEST_CTRL 0x00000033 45#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54 55#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 57 58#define MSR_PPIN_CTL 0x0000004e 59#define MSR_PPIN 0x0000004f 60 61#define MSR_IA32_PERFCTR0 0x000000c1 62#define MSR_IA32_PERFCTR1 0x000000c2 63#define MSR_FSB_FREQ 0x000000cd 64#define MSR_PLATFORM_INFO 0x000000ce 65#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 66#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67 68#define MSR_IA32_UMWAIT_CONTROL 0xe1 69#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71/* 72 * The time field is bit[31:2], but representing a 32bit value with 73 * bit[1:0] zero. 74 */ 75#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76 77/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 78#define MSR_IA32_CORE_CAPS 0x000000cf 79#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 80#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 81#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 82#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 83 84#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 85#define NHM_C3_AUTO_DEMOTE (1UL << 25) 86#define NHM_C1_AUTO_DEMOTE (1UL << 26) 87#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 88#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 89#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 90 91#define MSR_MTRRcap 0x000000fe 92 93#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 94#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 95#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 96#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 97#define ARCH_CAP_SSB_NO BIT(4) /* 98 * Not susceptible to Speculative Store Bypass 99 * attack, so no Speculative Store Bypass 100 * control required. 101 */ 102#define ARCH_CAP_MDS_NO BIT(5) /* 103 * Not susceptible to 104 * Microarchitectural Data 105 * Sampling (MDS) vulnerabilities. 106 */ 107#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 108 * The processor is not susceptible to a 109 * machine check error due to modifying the 110 * code page size along with either the 111 * physical address or cache type 112 * without TLB invalidation. 113 */ 114#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 115#define ARCH_CAP_TAA_NO BIT(8) /* 116 * Not susceptible to 117 * TSX Async Abort (TAA) vulnerabilities. 118 */ 119#define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 120 * Not susceptible to SBDR and SSDP 121 * variants of Processor MMIO stale data 122 * vulnerabilities. 123 */ 124#define ARCH_CAP_FBSDP_NO BIT(14) /* 125 * Not susceptible to FBSDP variant of 126 * Processor MMIO stale data 127 * vulnerabilities. 128 */ 129#define ARCH_CAP_PSDP_NO BIT(15) /* 130 * Not susceptible to PSDP variant of 131 * Processor MMIO stale data 132 * vulnerabilities. 133 */ 134#define ARCH_CAP_FB_CLEAR BIT(17) /* 135 * VERW clears CPU fill buffer 136 * even on MDS_NO CPUs. 137 */ 138#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 139 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 140 * bit available to control VERW 141 * behavior. 142 */ 143 144#define MSR_IA32_FLUSH_CMD 0x0000010b 145#define L1D_FLUSH BIT(0) /* 146 * Writeback and invalidate the 147 * L1 data cache. 148 */ 149 150#define MSR_IA32_BBL_CR_CTL 0x00000119 151#define MSR_IA32_BBL_CR_CTL3 0x0000011e 152 153#define MSR_IA32_TSX_CTRL 0x00000122 154#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 155#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 156 157#define MSR_IA32_MCU_OPT_CTRL 0x00000123 158#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 159#define RTM_ALLOW BIT(1) /* TSX development mode */ 160#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 161 162#define MSR_IA32_SYSENTER_CS 0x00000174 163#define MSR_IA32_SYSENTER_ESP 0x00000175 164#define MSR_IA32_SYSENTER_EIP 0x00000176 165 166#define MSR_IA32_MCG_CAP 0x00000179 167#define MSR_IA32_MCG_STATUS 0x0000017a 168#define MSR_IA32_MCG_CTL 0x0000017b 169#define MSR_ERROR_CONTROL 0x0000017f 170#define MSR_IA32_MCG_EXT_CTL 0x000004d0 171 172#define MSR_OFFCORE_RSP_0 0x000001a6 173#define MSR_OFFCORE_RSP_1 0x000001a7 174#define MSR_TURBO_RATIO_LIMIT 0x000001ad 175#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 176#define MSR_TURBO_RATIO_LIMIT2 0x000001af 177 178#define MSR_LBR_SELECT 0x000001c8 179#define MSR_LBR_TOS 0x000001c9 180 181#define MSR_IA32_POWER_CTL 0x000001fc 182#define MSR_IA32_POWER_CTL_BIT_EE 19 183 184/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 185#define MSR_INTEGRITY_CAPS 0x000002d9 186#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 187#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 188 189#define MSR_LBR_NHM_FROM 0x00000680 190#define MSR_LBR_NHM_TO 0x000006c0 191#define MSR_LBR_CORE_FROM 0x00000040 192#define MSR_LBR_CORE_TO 0x00000060 193 194#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 195#define LBR_INFO_MISPRED BIT_ULL(63) 196#define LBR_INFO_IN_TX BIT_ULL(62) 197#define LBR_INFO_ABORT BIT_ULL(61) 198#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 199#define LBR_INFO_CYCLES 0xffff 200#define LBR_INFO_BR_TYPE_OFFSET 56 201#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 202 203#define MSR_ARCH_LBR_CTL 0x000014ce 204#define ARCH_LBR_CTL_LBREN BIT(0) 205#define ARCH_LBR_CTL_CPL_OFFSET 1 206#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 207#define ARCH_LBR_CTL_STACK_OFFSET 3 208#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 209#define ARCH_LBR_CTL_FILTER_OFFSET 16 210#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 211#define MSR_ARCH_LBR_DEPTH 0x000014cf 212#define MSR_ARCH_LBR_FROM_0 0x00001500 213#define MSR_ARCH_LBR_TO_0 0x00001600 214#define MSR_ARCH_LBR_INFO_0 0x00001200 215 216#define MSR_IA32_PEBS_ENABLE 0x000003f1 217#define MSR_PEBS_DATA_CFG 0x000003f2 218#define MSR_IA32_DS_AREA 0x00000600 219#define MSR_IA32_PERF_CAPABILITIES 0x00000345 220#define PERF_CAP_METRICS_IDX 15 221#define PERF_CAP_PT_IDX 16 222 223#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 224 225#define MSR_IA32_RTIT_CTL 0x00000570 226#define RTIT_CTL_TRACEEN BIT(0) 227#define RTIT_CTL_CYCLEACC BIT(1) 228#define RTIT_CTL_OS BIT(2) 229#define RTIT_CTL_USR BIT(3) 230#define RTIT_CTL_PWR_EVT_EN BIT(4) 231#define RTIT_CTL_FUP_ON_PTW BIT(5) 232#define RTIT_CTL_FABRIC_EN BIT(6) 233#define RTIT_CTL_CR3EN BIT(7) 234#define RTIT_CTL_TOPA BIT(8) 235#define RTIT_CTL_MTC_EN BIT(9) 236#define RTIT_CTL_TSC_EN BIT(10) 237#define RTIT_CTL_DISRETC BIT(11) 238#define RTIT_CTL_PTW_EN BIT(12) 239#define RTIT_CTL_BRANCH_EN BIT(13) 240#define RTIT_CTL_EVENT_EN BIT(31) 241#define RTIT_CTL_NOTNT BIT_ULL(55) 242#define RTIT_CTL_MTC_RANGE_OFFSET 14 243#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 244#define RTIT_CTL_CYC_THRESH_OFFSET 19 245#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 246#define RTIT_CTL_PSB_FREQ_OFFSET 24 247#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 248#define RTIT_CTL_ADDR0_OFFSET 32 249#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 250#define RTIT_CTL_ADDR1_OFFSET 36 251#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 252#define RTIT_CTL_ADDR2_OFFSET 40 253#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 254#define RTIT_CTL_ADDR3_OFFSET 44 255#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 256#define MSR_IA32_RTIT_STATUS 0x00000571 257#define RTIT_STATUS_FILTEREN BIT(0) 258#define RTIT_STATUS_CONTEXTEN BIT(1) 259#define RTIT_STATUS_TRIGGEREN BIT(2) 260#define RTIT_STATUS_BUFFOVF BIT(3) 261#define RTIT_STATUS_ERROR BIT(4) 262#define RTIT_STATUS_STOPPED BIT(5) 263#define RTIT_STATUS_BYTECNT_OFFSET 32 264#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 265#define MSR_IA32_RTIT_ADDR0_A 0x00000580 266#define MSR_IA32_RTIT_ADDR0_B 0x00000581 267#define MSR_IA32_RTIT_ADDR1_A 0x00000582 268#define MSR_IA32_RTIT_ADDR1_B 0x00000583 269#define MSR_IA32_RTIT_ADDR2_A 0x00000584 270#define MSR_IA32_RTIT_ADDR2_B 0x00000585 271#define MSR_IA32_RTIT_ADDR3_A 0x00000586 272#define MSR_IA32_RTIT_ADDR3_B 0x00000587 273#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 274#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 275#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 276 277#define MSR_MTRRfix64K_00000 0x00000250 278#define MSR_MTRRfix16K_80000 0x00000258 279#define MSR_MTRRfix16K_A0000 0x00000259 280#define MSR_MTRRfix4K_C0000 0x00000268 281#define MSR_MTRRfix4K_C8000 0x00000269 282#define MSR_MTRRfix4K_D0000 0x0000026a 283#define MSR_MTRRfix4K_D8000 0x0000026b 284#define MSR_MTRRfix4K_E0000 0x0000026c 285#define MSR_MTRRfix4K_E8000 0x0000026d 286#define MSR_MTRRfix4K_F0000 0x0000026e 287#define MSR_MTRRfix4K_F8000 0x0000026f 288#define MSR_MTRRdefType 0x000002ff 289 290#define MSR_IA32_CR_PAT 0x00000277 291 292#define MSR_IA32_DEBUGCTLMSR 0x000001d9 293#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 294#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 295#define MSR_IA32_LASTINTFROMIP 0x000001dd 296#define MSR_IA32_LASTINTTOIP 0x000001de 297 298#define MSR_IA32_PASID 0x00000d93 299#define MSR_IA32_PASID_VALID BIT_ULL(31) 300 301/* DEBUGCTLMSR bits (others vary by model): */ 302#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 303#define DEBUGCTLMSR_BTF_SHIFT 1 304#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 305#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 306#define DEBUGCTLMSR_TR (1UL << 6) 307#define DEBUGCTLMSR_BTS (1UL << 7) 308#define DEBUGCTLMSR_BTINT (1UL << 8) 309#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 310#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 311#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 312#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 313#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 314#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 315 316#define MSR_PEBS_FRONTEND 0x000003f7 317 318#define MSR_IA32_MC0_CTL 0x00000400 319#define MSR_IA32_MC0_STATUS 0x00000401 320#define MSR_IA32_MC0_ADDR 0x00000402 321#define MSR_IA32_MC0_MISC 0x00000403 322 323/* C-state Residency Counters */ 324#define MSR_PKG_C3_RESIDENCY 0x000003f8 325#define MSR_PKG_C6_RESIDENCY 0x000003f9 326#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 327#define MSR_PKG_C7_RESIDENCY 0x000003fa 328#define MSR_CORE_C3_RESIDENCY 0x000003fc 329#define MSR_CORE_C6_RESIDENCY 0x000003fd 330#define MSR_CORE_C7_RESIDENCY 0x000003fe 331#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 332#define MSR_PKG_C2_RESIDENCY 0x0000060d 333#define MSR_PKG_C8_RESIDENCY 0x00000630 334#define MSR_PKG_C9_RESIDENCY 0x00000631 335#define MSR_PKG_C10_RESIDENCY 0x00000632 336 337/* Interrupt Response Limit */ 338#define MSR_PKGC3_IRTL 0x0000060a 339#define MSR_PKGC6_IRTL 0x0000060b 340#define MSR_PKGC7_IRTL 0x0000060c 341#define MSR_PKGC8_IRTL 0x00000633 342#define MSR_PKGC9_IRTL 0x00000634 343#define MSR_PKGC10_IRTL 0x00000635 344 345/* Run Time Average Power Limiting (RAPL) Interface */ 346 347#define MSR_VR_CURRENT_CONFIG 0x00000601 348#define MSR_RAPL_POWER_UNIT 0x00000606 349 350#define MSR_PKG_POWER_LIMIT 0x00000610 351#define MSR_PKG_ENERGY_STATUS 0x00000611 352#define MSR_PKG_PERF_STATUS 0x00000613 353#define MSR_PKG_POWER_INFO 0x00000614 354 355#define MSR_DRAM_POWER_LIMIT 0x00000618 356#define MSR_DRAM_ENERGY_STATUS 0x00000619 357#define MSR_DRAM_PERF_STATUS 0x0000061b 358#define MSR_DRAM_POWER_INFO 0x0000061c 359 360#define MSR_PP0_POWER_LIMIT 0x00000638 361#define MSR_PP0_ENERGY_STATUS 0x00000639 362#define MSR_PP0_POLICY 0x0000063a 363#define MSR_PP0_PERF_STATUS 0x0000063b 364 365#define MSR_PP1_POWER_LIMIT 0x00000640 366#define MSR_PP1_ENERGY_STATUS 0x00000641 367#define MSR_PP1_POLICY 0x00000642 368 369#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 370#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 371#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 372 373/* Config TDP MSRs */ 374#define MSR_CONFIG_TDP_NOMINAL 0x00000648 375#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 376#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 377#define MSR_CONFIG_TDP_CONTROL 0x0000064B 378#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 379 380#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 381 382#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 383#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 384#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 385#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 386 387#define MSR_CORE_C1_RES 0x00000660 388#define MSR_MODULE_C6_RES_MS 0x00000664 389 390#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 391#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 392 393#define MSR_ATOM_CORE_RATIOS 0x0000066a 394#define MSR_ATOM_CORE_VIDS 0x0000066b 395#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 396#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 397 398#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 399#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 400#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 401 402/* Control-flow Enforcement Technology MSRs */ 403#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 404#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 405#define CET_SHSTK_EN BIT_ULL(0) 406#define CET_WRSS_EN BIT_ULL(1) 407#define CET_ENDBR_EN BIT_ULL(2) 408#define CET_LEG_IW_EN BIT_ULL(3) 409#define CET_NO_TRACK_EN BIT_ULL(4) 410#define CET_SUPPRESS_DISABLE BIT_ULL(5) 411#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 412#define CET_SUPPRESS BIT_ULL(10) 413#define CET_WAIT_ENDBR BIT_ULL(11) 414 415#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 416#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 417#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 418#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 419#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 420 421/* Hardware P state interface */ 422#define MSR_PPERF 0x0000064e 423#define MSR_PERF_LIMIT_REASONS 0x0000064f 424#define MSR_PM_ENABLE 0x00000770 425#define MSR_HWP_CAPABILITIES 0x00000771 426#define MSR_HWP_REQUEST_PKG 0x00000772 427#define MSR_HWP_INTERRUPT 0x00000773 428#define MSR_HWP_REQUEST 0x00000774 429#define MSR_HWP_STATUS 0x00000777 430 431/* CPUID.6.EAX */ 432#define HWP_BASE_BIT (1<<7) 433#define HWP_NOTIFICATIONS_BIT (1<<8) 434#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 435#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 436#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 437 438/* IA32_HWP_CAPABILITIES */ 439#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 440#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 441#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 442#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 443 444/* IA32_HWP_REQUEST */ 445#define HWP_MIN_PERF(x) (x & 0xff) 446#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 447#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 448#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 449#define HWP_EPP_PERFORMANCE 0x00 450#define HWP_EPP_BALANCE_PERFORMANCE 0x80 451#define HWP_EPP_BALANCE_POWERSAVE 0xC0 452#define HWP_EPP_POWERSAVE 0xFF 453#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 454#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 455 456/* IA32_HWP_STATUS */ 457#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 458#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 459 460/* IA32_HWP_INTERRUPT */ 461#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 462#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 463 464#define MSR_AMD64_MC0_MASK 0xc0010044 465 466#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 467#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 468#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 469#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 470 471#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 472 473/* These are consecutive and not in the normal 4er MCE bank block */ 474#define MSR_IA32_MC0_CTL2 0x00000280 475#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 476 477#define MSR_P6_PERFCTR0 0x000000c1 478#define MSR_P6_PERFCTR1 0x000000c2 479#define MSR_P6_EVNTSEL0 0x00000186 480#define MSR_P6_EVNTSEL1 0x00000187 481 482#define MSR_KNC_PERFCTR0 0x00000020 483#define MSR_KNC_PERFCTR1 0x00000021 484#define MSR_KNC_EVNTSEL0 0x00000028 485#define MSR_KNC_EVNTSEL1 0x00000029 486 487/* Alternative perfctr range with full access. */ 488#define MSR_IA32_PMC0 0x000004c1 489 490/* Auto-reload via MSR instead of DS area */ 491#define MSR_RELOAD_PMC0 0x000014c1 492#define MSR_RELOAD_FIXED_CTR0 0x00001309 493 494/* 495 * AMD64 MSRs. Not complete. See the architecture manual for a more 496 * complete list. 497 */ 498#define MSR_AMD64_PATCH_LEVEL 0x0000008b 499#define MSR_AMD64_TSC_RATIO 0xc0000104 500#define MSR_AMD64_NB_CFG 0xc001001f 501#define MSR_AMD64_PATCH_LOADER 0xc0010020 502#define MSR_AMD_PERF_CTL 0xc0010062 503#define MSR_AMD_PERF_STATUS 0xc0010063 504#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 505#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 506#define MSR_AMD64_OSVW_STATUS 0xc0010141 507#define MSR_AMD_PPIN_CTL 0xc00102f0 508#define MSR_AMD_PPIN 0xc00102f1 509#define MSR_AMD64_CPUID_FN_1 0xc0011004 510#define MSR_AMD64_LS_CFG 0xc0011020 511#define MSR_AMD64_DC_CFG 0xc0011022 512#define MSR_AMD64_BU_CFG2 0xc001102a 513#define MSR_AMD64_IBSFETCHCTL 0xc0011030 514#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 515#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 516#define MSR_AMD64_IBSFETCH_REG_COUNT 3 517#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 518#define MSR_AMD64_IBSOPCTL 0xc0011033 519#define MSR_AMD64_IBSOPRIP 0xc0011034 520#define MSR_AMD64_IBSOPDATA 0xc0011035 521#define MSR_AMD64_IBSOPDATA2 0xc0011036 522#define MSR_AMD64_IBSOPDATA3 0xc0011037 523#define MSR_AMD64_IBSDCLINAD 0xc0011038 524#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 525#define MSR_AMD64_IBSOP_REG_COUNT 7 526#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 527#define MSR_AMD64_IBSCTL 0xc001103a 528#define MSR_AMD64_IBSBRTARGET 0xc001103b 529#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 530#define MSR_AMD64_IBSOPDATA4 0xc001103d 531#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 532#define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 533#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 534#define MSR_AMD64_SEV_ES_GHCB 0xc0010130 535#define MSR_AMD64_SEV 0xc0010131 536#define MSR_AMD64_SEV_ENABLED_BIT 0 537#define MSR_AMD64_SEV_ES_ENABLED_BIT 1 538#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 539#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 540#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 541#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 542 543#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 544 545/* AMD Collaborative Processor Performance Control MSRs */ 546#define MSR_AMD_CPPC_CAP1 0xc00102b0 547#define MSR_AMD_CPPC_ENABLE 0xc00102b1 548#define MSR_AMD_CPPC_CAP2 0xc00102b2 549#define MSR_AMD_CPPC_REQ 0xc00102b3 550#define MSR_AMD_CPPC_STATUS 0xc00102b4 551 552#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 553#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 554#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 555#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 556 557#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 558#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 559#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 560#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 561 562/* AMD Performance Counter Global Status and Control MSRs */ 563#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 564#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 565#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 566 567/* Fam 17h MSRs */ 568#define MSR_F17H_IRPERF 0xc00000e9 569 570/* Fam 16h MSRs */ 571#define MSR_F16H_L2I_PERF_CTL 0xc0010230 572#define MSR_F16H_L2I_PERF_CTR 0xc0010231 573#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 574#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 575#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 576#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 577 578/* Fam 15h MSRs */ 579#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 580#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 581#define MSR_F15H_PERF_CTL 0xc0010200 582#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 583#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 584#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 585#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 586#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 587#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 588 589#define MSR_F15H_PERF_CTR 0xc0010201 590#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 591#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 592#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 593#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 594#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 595#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 596 597#define MSR_F15H_NB_PERF_CTL 0xc0010240 598#define MSR_F15H_NB_PERF_CTR 0xc0010241 599#define MSR_F15H_PTSC 0xc0010280 600#define MSR_F15H_IC_CFG 0xc0011021 601#define MSR_F15H_EX_CFG 0xc001102c 602 603/* Fam 10h MSRs */ 604#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 605#define FAM10H_MMIO_CONF_ENABLE (1<<0) 606#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 607#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 608#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 609#define FAM10H_MMIO_CONF_BASE_SHIFT 20 610#define MSR_FAM10H_NODE_ID 0xc001100c 611#define MSR_F10H_DECFG 0xc0011029 612#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 613#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 614 615/* K8 MSRs */ 616#define MSR_K8_TOP_MEM1 0xc001001a 617#define MSR_K8_TOP_MEM2 0xc001001d 618#define MSR_AMD64_SYSCFG 0xc0010010 619#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 620#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 621#define MSR_K8_INT_PENDING_MSG 0xc0010055 622/* C1E active bits in int pending message */ 623#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 624#define MSR_K8_TSEG_ADDR 0xc0010112 625#define MSR_K8_TSEG_MASK 0xc0010113 626#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 627#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 628#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 629 630/* K7 MSRs */ 631#define MSR_K7_EVNTSEL0 0xc0010000 632#define MSR_K7_PERFCTR0 0xc0010004 633#define MSR_K7_EVNTSEL1 0xc0010001 634#define MSR_K7_PERFCTR1 0xc0010005 635#define MSR_K7_EVNTSEL2 0xc0010002 636#define MSR_K7_PERFCTR2 0xc0010006 637#define MSR_K7_EVNTSEL3 0xc0010003 638#define MSR_K7_PERFCTR3 0xc0010007 639#define MSR_K7_CLK_CTL 0xc001001b 640#define MSR_K7_HWCR 0xc0010015 641#define MSR_K7_HWCR_SMMLOCK_BIT 0 642#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 643#define MSR_K7_HWCR_IRPERF_EN_BIT 30 644#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 645#define MSR_K7_FID_VID_CTL 0xc0010041 646#define MSR_K7_FID_VID_STATUS 0xc0010042 647 648/* K6 MSRs */ 649#define MSR_K6_WHCR 0xc0000082 650#define MSR_K6_UWCCR 0xc0000085 651#define MSR_K6_EPMR 0xc0000086 652#define MSR_K6_PSOR 0xc0000087 653#define MSR_K6_PFIR 0xc0000088 654 655/* Centaur-Hauls/IDT defined MSRs. */ 656#define MSR_IDT_FCR1 0x00000107 657#define MSR_IDT_FCR2 0x00000108 658#define MSR_IDT_FCR3 0x00000109 659#define MSR_IDT_FCR4 0x0000010a 660 661#define MSR_IDT_MCR0 0x00000110 662#define MSR_IDT_MCR1 0x00000111 663#define MSR_IDT_MCR2 0x00000112 664#define MSR_IDT_MCR3 0x00000113 665#define MSR_IDT_MCR4 0x00000114 666#define MSR_IDT_MCR5 0x00000115 667#define MSR_IDT_MCR6 0x00000116 668#define MSR_IDT_MCR7 0x00000117 669#define MSR_IDT_MCR_CTRL 0x00000120 670 671/* VIA Cyrix defined MSRs*/ 672#define MSR_VIA_FCR 0x00001107 673#define MSR_VIA_LONGHAUL 0x0000110a 674#define MSR_VIA_RNG 0x0000110b 675#define MSR_VIA_BCR2 0x00001147 676 677/* Transmeta defined MSRs */ 678#define MSR_TMTA_LONGRUN_CTRL 0x80868010 679#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 680#define MSR_TMTA_LRTI_READOUT 0x80868018 681#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 682 683/* Intel defined MSRs. */ 684#define MSR_IA32_P5_MC_ADDR 0x00000000 685#define MSR_IA32_P5_MC_TYPE 0x00000001 686#define MSR_IA32_TSC 0x00000010 687#define MSR_IA32_PLATFORM_ID 0x00000017 688#define MSR_IA32_EBL_CR_POWERON 0x0000002a 689#define MSR_EBC_FREQUENCY_ID 0x0000002c 690#define MSR_SMI_COUNT 0x00000034 691 692/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 693#define MSR_IA32_FEAT_CTL 0x0000003a 694#define FEAT_CTL_LOCKED BIT(0) 695#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 696#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 697#define FEAT_CTL_SGX_LC_ENABLED BIT(17) 698#define FEAT_CTL_SGX_ENABLED BIT(18) 699#define FEAT_CTL_LMCE_ENABLED BIT(20) 700 701#define MSR_IA32_TSC_ADJUST 0x0000003b 702#define MSR_IA32_BNDCFGS 0x00000d90 703 704#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 705 706#define MSR_IA32_XFD 0x000001c4 707#define MSR_IA32_XFD_ERR 0x000001c5 708#define MSR_IA32_XSS 0x00000da0 709 710#define MSR_IA32_APICBASE 0x0000001b 711#define MSR_IA32_APICBASE_BSP (1<<8) 712#define MSR_IA32_APICBASE_ENABLE (1<<11) 713#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 714 715#define MSR_IA32_UCODE_WRITE 0x00000079 716#define MSR_IA32_UCODE_REV 0x0000008b 717 718/* Intel SGX Launch Enclave Public Key Hash MSRs */ 719#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 720#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 721#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 722#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 723 724#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 725#define MSR_IA32_SMBASE 0x0000009e 726 727#define MSR_IA32_PERF_STATUS 0x00000198 728#define MSR_IA32_PERF_CTL 0x00000199 729#define INTEL_PERF_CTL_MASK 0xffff 730 731/* AMD Branch Sampling configuration */ 732#define MSR_AMD_DBG_EXTN_CFG 0xc000010f 733#define MSR_AMD_SAMP_BR_FROM 0xc0010300 734 735#define MSR_IA32_MPERF 0x000000e7 736#define MSR_IA32_APERF 0x000000e8 737 738#define MSR_IA32_THERM_CONTROL 0x0000019a 739#define MSR_IA32_THERM_INTERRUPT 0x0000019b 740 741#define THERM_INT_HIGH_ENABLE (1 << 0) 742#define THERM_INT_LOW_ENABLE (1 << 1) 743#define THERM_INT_PLN_ENABLE (1 << 24) 744 745#define MSR_IA32_THERM_STATUS 0x0000019c 746 747#define THERM_STATUS_PROCHOT (1 << 0) 748#define THERM_STATUS_POWER_LIMIT (1 << 10) 749 750#define MSR_THERM2_CTL 0x0000019d 751 752#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 753 754#define MSR_IA32_MISC_ENABLE 0x000001a0 755 756#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 757 758#define MSR_MISC_FEATURE_CONTROL 0x000001a4 759#define MSR_MISC_PWR_MGMT 0x000001aa 760 761#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 762#define ENERGY_PERF_BIAS_PERFORMANCE 0 763#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 764#define ENERGY_PERF_BIAS_NORMAL 6 765#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 766#define ENERGY_PERF_BIAS_POWERSAVE 15 767 768#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 769 770#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 771#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 772#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 773 774#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 775 776#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 777#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 778#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 779#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 780 781/* Thermal Thresholds Support */ 782#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 783#define THERM_SHIFT_THRESHOLD0 8 784#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 785#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 786#define THERM_SHIFT_THRESHOLD1 16 787#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 788#define THERM_STATUS_THRESHOLD0 (1 << 6) 789#define THERM_LOG_THRESHOLD0 (1 << 7) 790#define THERM_STATUS_THRESHOLD1 (1 << 8) 791#define THERM_LOG_THRESHOLD1 (1 << 9) 792 793/* MISC_ENABLE bits: architectural */ 794#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 795#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 796#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 797#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 798#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 799#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 800#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 801#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 802#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 803#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 804#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 805#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 806#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 807#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 808#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 809#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 810#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 811#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 812#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 813#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 814 815/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 816#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 817#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 818#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 819#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 820#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 821#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 822#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 823#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 824#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 825#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 826#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 827#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 828#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 829#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 830#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 831#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 832#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 833#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 834#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 835#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 836#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 837#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 838#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 839#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 840#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 841#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 842#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 843#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 844#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 845#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 846 847/* MISC_FEATURES_ENABLES non-architectural features */ 848#define MSR_MISC_FEATURES_ENABLES 0x00000140 849 850#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 851#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 852#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 853 854#define MSR_IA32_TSC_DEADLINE 0x000006E0 855 856 857#define MSR_TSX_FORCE_ABORT 0x0000010F 858 859#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 860#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 861#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 862#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 863#define MSR_TFA_SDV_ENABLE_RTM_BIT 2 864#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 865 866/* P4/Xeon+ specific */ 867#define MSR_IA32_MCG_EAX 0x00000180 868#define MSR_IA32_MCG_EBX 0x00000181 869#define MSR_IA32_MCG_ECX 0x00000182 870#define MSR_IA32_MCG_EDX 0x00000183 871#define MSR_IA32_MCG_ESI 0x00000184 872#define MSR_IA32_MCG_EDI 0x00000185 873#define MSR_IA32_MCG_EBP 0x00000186 874#define MSR_IA32_MCG_ESP 0x00000187 875#define MSR_IA32_MCG_EFLAGS 0x00000188 876#define MSR_IA32_MCG_EIP 0x00000189 877#define MSR_IA32_MCG_RESERVED 0x0000018a 878 879/* Pentium IV performance counter MSRs */ 880#define MSR_P4_BPU_PERFCTR0 0x00000300 881#define MSR_P4_BPU_PERFCTR1 0x00000301 882#define MSR_P4_BPU_PERFCTR2 0x00000302 883#define MSR_P4_BPU_PERFCTR3 0x00000303 884#define MSR_P4_MS_PERFCTR0 0x00000304 885#define MSR_P4_MS_PERFCTR1 0x00000305 886#define MSR_P4_MS_PERFCTR2 0x00000306 887#define MSR_P4_MS_PERFCTR3 0x00000307 888#define MSR_P4_FLAME_PERFCTR0 0x00000308 889#define MSR_P4_FLAME_PERFCTR1 0x00000309 890#define MSR_P4_FLAME_PERFCTR2 0x0000030a 891#define MSR_P4_FLAME_PERFCTR3 0x0000030b 892#define MSR_P4_IQ_PERFCTR0 0x0000030c 893#define MSR_P4_IQ_PERFCTR1 0x0000030d 894#define MSR_P4_IQ_PERFCTR2 0x0000030e 895#define MSR_P4_IQ_PERFCTR3 0x0000030f 896#define MSR_P4_IQ_PERFCTR4 0x00000310 897#define MSR_P4_IQ_PERFCTR5 0x00000311 898#define MSR_P4_BPU_CCCR0 0x00000360 899#define MSR_P4_BPU_CCCR1 0x00000361 900#define MSR_P4_BPU_CCCR2 0x00000362 901#define MSR_P4_BPU_CCCR3 0x00000363 902#define MSR_P4_MS_CCCR0 0x00000364 903#define MSR_P4_MS_CCCR1 0x00000365 904#define MSR_P4_MS_CCCR2 0x00000366 905#define MSR_P4_MS_CCCR3 0x00000367 906#define MSR_P4_FLAME_CCCR0 0x00000368 907#define MSR_P4_FLAME_CCCR1 0x00000369 908#define MSR_P4_FLAME_CCCR2 0x0000036a 909#define MSR_P4_FLAME_CCCR3 0x0000036b 910#define MSR_P4_IQ_CCCR0 0x0000036c 911#define MSR_P4_IQ_CCCR1 0x0000036d 912#define MSR_P4_IQ_CCCR2 0x0000036e 913#define MSR_P4_IQ_CCCR3 0x0000036f 914#define MSR_P4_IQ_CCCR4 0x00000370 915#define MSR_P4_IQ_CCCR5 0x00000371 916#define MSR_P4_ALF_ESCR0 0x000003ca 917#define MSR_P4_ALF_ESCR1 0x000003cb 918#define MSR_P4_BPU_ESCR0 0x000003b2 919#define MSR_P4_BPU_ESCR1 0x000003b3 920#define MSR_P4_BSU_ESCR0 0x000003a0 921#define MSR_P4_BSU_ESCR1 0x000003a1 922#define MSR_P4_CRU_ESCR0 0x000003b8 923#define MSR_P4_CRU_ESCR1 0x000003b9 924#define MSR_P4_CRU_ESCR2 0x000003cc 925#define MSR_P4_CRU_ESCR3 0x000003cd 926#define MSR_P4_CRU_ESCR4 0x000003e0 927#define MSR_P4_CRU_ESCR5 0x000003e1 928#define MSR_P4_DAC_ESCR0 0x000003a8 929#define MSR_P4_DAC_ESCR1 0x000003a9 930#define MSR_P4_FIRM_ESCR0 0x000003a4 931#define MSR_P4_FIRM_ESCR1 0x000003a5 932#define MSR_P4_FLAME_ESCR0 0x000003a6 933#define MSR_P4_FLAME_ESCR1 0x000003a7 934#define MSR_P4_FSB_ESCR0 0x000003a2 935#define MSR_P4_FSB_ESCR1 0x000003a3 936#define MSR_P4_IQ_ESCR0 0x000003ba 937#define MSR_P4_IQ_ESCR1 0x000003bb 938#define MSR_P4_IS_ESCR0 0x000003b4 939#define MSR_P4_IS_ESCR1 0x000003b5 940#define MSR_P4_ITLB_ESCR0 0x000003b6 941#define MSR_P4_ITLB_ESCR1 0x000003b7 942#define MSR_P4_IX_ESCR0 0x000003c8 943#define MSR_P4_IX_ESCR1 0x000003c9 944#define MSR_P4_MOB_ESCR0 0x000003aa 945#define MSR_P4_MOB_ESCR1 0x000003ab 946#define MSR_P4_MS_ESCR0 0x000003c0 947#define MSR_P4_MS_ESCR1 0x000003c1 948#define MSR_P4_PMH_ESCR0 0x000003ac 949#define MSR_P4_PMH_ESCR1 0x000003ad 950#define MSR_P4_RAT_ESCR0 0x000003bc 951#define MSR_P4_RAT_ESCR1 0x000003bd 952#define MSR_P4_SAAT_ESCR0 0x000003ae 953#define MSR_P4_SAAT_ESCR1 0x000003af 954#define MSR_P4_SSU_ESCR0 0x000003be 955#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 956 957#define MSR_P4_TBPU_ESCR0 0x000003c2 958#define MSR_P4_TBPU_ESCR1 0x000003c3 959#define MSR_P4_TC_ESCR0 0x000003c4 960#define MSR_P4_TC_ESCR1 0x000003c5 961#define MSR_P4_U2L_ESCR0 0x000003b0 962#define MSR_P4_U2L_ESCR1 0x000003b1 963 964#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 965 966/* Intel Core-based CPU performance counters */ 967#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 968#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 969#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 970#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 971#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 972#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 973#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 974#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 975 976#define MSR_PERF_METRICS 0x00000329 977 978/* PERF_GLOBAL_OVF_CTL bits */ 979#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 980#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 981#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 982#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 983#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 984#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 985 986/* Geode defined MSRs */ 987#define MSR_GEODE_BUSCONT_CONF0 0x00001900 988 989/* Intel VT MSRs */ 990#define MSR_IA32_VMX_BASIC 0x00000480 991#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 992#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 993#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 994#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 995#define MSR_IA32_VMX_MISC 0x00000485 996#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 997#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 998#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 999#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1000#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1001#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1002#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1003#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1004#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1005#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1006#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1007#define MSR_IA32_VMX_VMFUNC 0x00000491 1008 1009/* VMX_BASIC bits and bitmasks */ 1010#define VMX_BASIC_VMCS_SIZE_SHIFT 32 1011#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1012#define VMX_BASIC_64 0x0001000000000000LLU 1013#define VMX_BASIC_MEM_TYPE_SHIFT 50 1014#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1015#define VMX_BASIC_MEM_TYPE_WB 6LLU 1016#define VMX_BASIC_INOUT 0x0040000000000000LLU 1017 1018/* MSR_IA32_VMX_MISC bits */ 1019#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1020#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1021#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1022/* AMD-V MSRs */ 1023 1024#define MSR_VM_CR 0xc0010114 1025#define MSR_VM_IGNNE 0xc0010115 1026#define MSR_VM_HSAVE_PA 0xc0010117 1027 1028/* Hardware Feedback Interface */ 1029#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 1030#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 1031 1032#endif /* _ASM_X86_MSR_INDEX_H */