cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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perf_regs.h (1403B)


      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2#ifndef _ASM_X86_PERF_REGS_H
      3#define _ASM_X86_PERF_REGS_H
      4
      5enum perf_event_x86_regs {
      6	PERF_REG_X86_AX,
      7	PERF_REG_X86_BX,
      8	PERF_REG_X86_CX,
      9	PERF_REG_X86_DX,
     10	PERF_REG_X86_SI,
     11	PERF_REG_X86_DI,
     12	PERF_REG_X86_BP,
     13	PERF_REG_X86_SP,
     14	PERF_REG_X86_IP,
     15	PERF_REG_X86_FLAGS,
     16	PERF_REG_X86_CS,
     17	PERF_REG_X86_SS,
     18	PERF_REG_X86_DS,
     19	PERF_REG_X86_ES,
     20	PERF_REG_X86_FS,
     21	PERF_REG_X86_GS,
     22	PERF_REG_X86_R8,
     23	PERF_REG_X86_R9,
     24	PERF_REG_X86_R10,
     25	PERF_REG_X86_R11,
     26	PERF_REG_X86_R12,
     27	PERF_REG_X86_R13,
     28	PERF_REG_X86_R14,
     29	PERF_REG_X86_R15,
     30	/* These are the limits for the GPRs. */
     31	PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
     32	PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
     33
     34	/* These all need two bits set because they are 128bit */
     35	PERF_REG_X86_XMM0  = 32,
     36	PERF_REG_X86_XMM1  = 34,
     37	PERF_REG_X86_XMM2  = 36,
     38	PERF_REG_X86_XMM3  = 38,
     39	PERF_REG_X86_XMM4  = 40,
     40	PERF_REG_X86_XMM5  = 42,
     41	PERF_REG_X86_XMM6  = 44,
     42	PERF_REG_X86_XMM7  = 46,
     43	PERF_REG_X86_XMM8  = 48,
     44	PERF_REG_X86_XMM9  = 50,
     45	PERF_REG_X86_XMM10 = 52,
     46	PERF_REG_X86_XMM11 = 54,
     47	PERF_REG_X86_XMM12 = 56,
     48	PERF_REG_X86_XMM13 = 58,
     49	PERF_REG_X86_XMM14 = 60,
     50	PERF_REG_X86_XMM15 = 62,
     51
     52	/* These include both GPRs and XMMX registers */
     53	PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2,
     54};
     55
     56#define PERF_REG_EXTENDED_MASK	(~((1ULL << PERF_REG_X86_XMM0) - 1))
     57
     58#endif /* _ASM_X86_PERF_REGS_H */