cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cheatsheet.txt (2048B)


      1                                  Prior Operation     Subsequent Operation
      2                                  ---------------  ---------------------------
      3                               C  Self  R  W  RMW  Self  R  W  DR  DW  RMW  SV
      4                              --  ----  -  -  ---  ----  -  -  --  --  ---  --
      5
      6Relaxed store                        Y                                       Y
      7Relaxed load                         Y                          Y   Y        Y
      8Relaxed RMW operation                Y                          Y   Y        Y
      9rcu_dereference()                    Y                          Y   Y        Y
     10Successful *_acquire()               R                   Y  Y   Y   Y    Y   Y
     11Successful *_release()         C        Y  Y    Y     W                      Y
     12smp_rmb()                               Y       R        Y      Y        R
     13smp_wmb()                                  Y    W           Y       Y    W
     14smp_mb() & synchronize_rcu()  CP        Y  Y    Y        Y  Y   Y   Y    Y
     15Successful full non-void RMW  CP     Y  Y  Y    Y     Y  Y  Y   Y   Y    Y   Y
     16smp_mb__before_atomic()       CP        Y  Y    Y        a  a   a   a    Y
     17smp_mb__after_atomic()        CP        a  a    Y        Y  Y   Y   Y    Y
     18
     19
     20Key:	Relaxed:  A relaxed operation is either READ_ONCE(), WRITE_ONCE(),
     21		  a *_relaxed() RMW operation, an unsuccessful RMW
     22		  operation, a non-value-returning RMW operation such
     23		  as atomic_inc(), or one of the atomic*_read() and
     24		  atomic*_set() family of operations.
     25	C:	  Ordering is cumulative
     26	P:	  Ordering propagates
     27	R:	  Read, for example, READ_ONCE(), or read portion of RMW
     28	W:	  Write, for example, WRITE_ONCE(), or write portion of RMW
     29	Y:	  Provides ordering
     30	a:	  Provides ordering given intervening RMW atomic operation
     31	DR:	  Dependent read (address dependency)
     32	DW:	  Dependent write (address, data, or control dependency)
     33	RMW:	  Atomic read-modify-write operation
     34	SELF:	  Orders self, as opposed to accesses before and/or after
     35	SV:	  Orders later accesses to the same variable