cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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SB+fencembonceonces.litmus (499B)

      1C SB+fencembonceonces
      2
      3(*
      4 * Result: Never
      5 *
      6 * This litmus test demonstrates that full memory barriers suffice to
      7 * order the store-buffering pattern, where each process writes to the
      8 * variable that the preceding process reads.  (Locking and RCU can also
      9 * suffice, but not much else.)
     10 *)
     11
     12{}
     13
     14P0(int *x, int *y)
     15{
     16	int r0;
     17
     18	WRITE_ONCE(*x, 1);
     19	smp_mb();
     20	r0 = READ_ONCE(*y);
     21}
     22
     23P1(int *x, int *y)
     24{
     25	int r0;
     26
     27	WRITE_ONCE(*y, 1);
     28	smp_mb();
     29	r0 = READ_ONCE(*x);
     30}
     31
     32exists (0:r0=0 /\ 1:r0=0)