cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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Z6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus (980B)

      1C Z6.0+pooncerelease+poacquirerelease+fencembonceonce
      2
      3(*
      4 * Result: Sometimes
      5 *
      6 * This litmus test shows that a release-acquire chain, while sufficient
      7 * when there is but one non-reads-from (AKA non-rf) link, does not suffice
      8 * if there is more than one.  Of the three processes, only P1() reads from
      9 * P0's write, which means that there are two non-rf links: P1() to P2()
     10 * is a write-to-write link (AKA a "coherence" or just "co" link) and P2()
     11 * to P0() is a read-to-write link (AKA a "from-reads" or just "fr" link).
     12 * When there are two or more non-rf links, you typically will need one
     13 * full barrier for each non-rf link.  (Exceptions include some cases
     14 * involving locking.)
     15 *)
     16
     17{}
     18
     19P0(int *x, int *y)
     20{
     21	WRITE_ONCE(*x, 1);
     22	smp_store_release(y, 1);
     23}
     24
     25P1(int *y, int *z)
     26{
     27	int r0;
     28
     29	r0 = smp_load_acquire(y);
     30	smp_store_release(z, 1);
     31}
     32
     33P2(int *x, int *z)
     34{
     35	int r1;
     36
     37	WRITE_ONCE(*z, 2);
     38	smp_mb();
     39	r1 = READ_ONCE(*x);
     40}
     41
     42exists (1:r0=1 /\ z=2 /\ 2:r1=0)