cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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itrace.txt (2596B)


      1		i	synthesize instructions events
      2		b	synthesize branches events (branch misses for Arm SPE)
      3		c	synthesize branches events (calls only)
      4		r	synthesize branches events (returns only)
      5		x	synthesize transactions events
      6		w	synthesize ptwrite events
      7		p	synthesize power events (incl. PSB events for Intel PT)
      8		o	synthesize other events recorded due to the use
      9			of aux-output (refer to perf record)
     10		I	synthesize interrupt or similar (asynchronous) events
     11			(e.g. Intel PT Event Trace)
     12		e	synthesize error events
     13		d	create a debug log
     14		f	synthesize first level cache events
     15		m	synthesize last level cache events
     16		M	synthesize memory events
     17		t	synthesize TLB events
     18		a	synthesize remote access events
     19		g	synthesize a call chain (use with i or x)
     20		G	synthesize a call chain on existing event records
     21		l	synthesize last branch entries (use with i or x)
     22		L	synthesize last branch entries on existing event records
     23		s       skip initial number of events
     24		q	quicker (less detailed) decoding
     25		A	approximate IPC
     26		Z	prefer to ignore timestamps (so-called "timeless" decoding)
     27
     28	The default is all events i.e. the same as --itrace=ibxwpe,
     29	except for perf script where it is --itrace=ce
     30
     31	In addition, the period (default 100000, except for perf script where it is 1)
     32	for instructions events can be specified in units of:
     33
     34		i	instructions
     35		t	ticks
     36		ms	milliseconds
     37		us	microseconds
     38		ns	nanoseconds (default)
     39
     40	Also the call chain size (default 16, max. 1024) for instructions or
     41	transactions events can be specified.
     42
     43	Also the number of last branch entries (default 64, max. 1024) for
     44	instructions or transactions events can be specified.
     45
     46	Similar to options g and l, size may also be specified for options G and L.
     47	On x86, note that G and L work poorly when data has been recorded with
     48	large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
     49
     50	It is also possible to skip events generated (instructions, branches, transactions,
     51	ptwrite, power) at the beginning. This is useful to ignore initialization code.
     52
     53	--itrace=i0nss1000000
     54
     55	skips the first million instructions.
     56
     57	The 'e' option may be followed by flags which affect what errors will or
     58	will not be reported. Each flag must be preceded by either '+' or '-'.
     59	The flags are:
     60		o	overflow
     61		l	trace data lost
     62
     63	If supported, the 'd' option may be followed by flags which affect what
     64	debug messages will or will not be logged. Each flag must be preceded
     65	by either '+' or '-'. The flags are:
     66		a	all perf events
     67		o	output to stdout
     68
     69	If supported, the 'q' option may be repeated to increase the effect.